KR100652373B1 - Cell Searcher and cell searching method of the W-CDMA using common partial correlation for primary and secondary synchronization code - Google Patents

Abstract

A wideband CDMA cell searcher using a common partial correlation for PSC and SSC and a method thereof are disclosed. The cell searcher of the wideband CDMA uses a single correlator to calculate partial correlation values that can be commonly used in the PSC / SSC code, store them in a predetermined memory, and reuse them. We adopt a pipeline structure that performs correlation on the code at the same time.

Description

Cell Searcher and cell searching method of the W-CDMA using common partial correlation for primary and secondary synchronization code}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a cell searcher of a conventional sequential search structure.

2 is a block diagram illustrating a conventional matching filter for detecting slot synchronization signals.

3 is a block diagram showing a conventional SSC correlator.

4 is a block diagram illustrating a broadband CDMA cell searcher of a pipeline structure according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a PSC / SSC correlator of FIG. 4.

FIG. 6 is a conceptual diagram of the PSC / SSC correlator of FIG. 5.

7 is a graph comparing synchronization acquisition time in serial and pipeline structures.

The present invention relates to wideband code division multiple access (W-CDMA) communications, and more particularly to a cell searcher for W-CDMA communications.

Mobile communication systems have been developed into first generation analog cellular, 2.5 generation personal communication systems (PCS), and third generation international mobile telecommunication-2000 (IMT-2000). Currently, up to 2.5 generations have been commercialized and serviced, but the third generation of IMT-2000 is being piloted. The third generation mobile communication system currently under development adopts 3GPP (3rd Generation Partnership Project) -driven asynchronous and 3GPP2-driven synchronous methods as standards. W-CDMA is asynchronous among three generations of IMT-2000. In such a W-CDMA scheme, since all base stations, ie, cells, do not have to have the same reference time, various types of cells can be easily installed. Mobile stations communicate with the cell, which relays the call connections of the mobile stations. The mobile stations must acquire a scrambling code of the corresponding cell through cell search to succeed in call connection.

1 is a block diagram illustrating a cell searcher 100 of a conventional serial search structure. Referring to FIG. 1, the cell searcher 100 of the conventional sequential search structure includes a radio frequency (RF) module 110, a matched filtering and PSC detector 120, a correlation calculation and an SSC detector 130, and a pilot. (pilot) detector 140 is provided. The RF module 110 receives the airwaves of the wireless W-CDMA channel to extract the baseband signal, and then converts the baseband analog signal into a digital signal to output the received W-CDMA stream (RX). One frame of the received W-CDMA stream RX consists of 15 slots, one slot consists of 10 symbols, and one symbol consists of 256 chips. One frame corresponds to 10 msec.

In the W-CDMA system, the cell search process consists of three steps. First, the matched filtering and the PSC detector 120 may use a matched filter as shown in FIG. 2 to store a correlation value X calculated in a predetermined unit (for example, a symbol) by several slots. Accumulate over and estimate the peak to obtain a slot synchronization signal (SLS). In the matched filter of FIG. 2, through the multipliers 220 and the adder 230, the register stream 210 causes the receive stream RX 'to move a signal between the chip and the chip. A correlation value X of a predetermined unit is output by taking a correlation between signals delayed in multiples of the time taken 'and a primary synchronization code (PSC) code (PSC (0) to PSC (N)).

In the second step cell search, the correlation calculation and the SSC detector 130 uses the SSC correlator as shown in FIG. 3 in response to the slot synchronization signal SLS, and selects a predetermined unit (for example, 256 chips). Frame synchronization signal (FRS) and scrambling code group information (SCG) of a cell to which a mobile station belongs by accumulating the correlation values K1 to KN calculated over a plurality of slots and estimating peaks. ). The SSC correlator of FIG. 3, through multipliers 310 and summers 320, correlates a received stream RX with a secondary synchronization code (SSC) code (SSC (0) to SSC (N)). , And outputs correlation values K1 to KN in a predetermined unit.

In a third step cell search, in response to the frame synchronization signal FRS, the pilot detector 140 receives all scrambling codes and a received stream RX belonging to a code group indicated by the scrambling code group information SCG. The correlation is taken to estimate the scrambling code of the corresponding cell. Such a conventional cell searcher 100 is well shown in the international patent application "PCT / US2000-17898".

As described above, the conventional cell searcher 100 sequentially searches for synchronization acquisition in three steps. That is, since the correlation value (or partial correlation value) calculation for the PSC of the first step or the correlation value (or partial correlation value) calculation for the SSC of the second step cannot be performed simultaneously and sequentially, the cell search time is There is a problem of lengthening.

Accordingly, an object of the present invention is to provide a cell searcher for wideband CDMA that performs PSC and SSC correlation in a pipelined structure by using common partial correlation for PSC and SSC.

 Another object of the present invention is to provide a cell search method for wideband CDMA that performs PSC and SSC correlation in a pipeline structure.

The cell searcher of the wideband CDMA according to the present invention for achieving the above technical problem is characterized by comprising a PSC (primary synchronization code) / SSC (secondary synchronization code) correlator, PSC detector, SSC detector, and pilot detector . The PSC / SSC correlator calculates partial correlation values commonly used for PSC correlation and SSC correlation from a received stream, and accumulates the partial correlation values to generate a PSC correlation value and an SSC correlation value. The PSC detector accumulates the PSC correlation value over a plurality of slots and estimates a peak to generate a slot sync signal. The SSC detector accumulates the SSC correlation value over a plurality of slots, estimates peaks, and generates scrambling code group information of the cell to which the frame synchronization signal belongs and the mobile station. The pilot detector correlates all the scrambling codes belonging to the code group corresponding to the scrambling code group information with the received stream to generate a scrambling code of the corresponding cell. The PSC / SSC correlator stores the partial correlation values and reuses the correlations in a pipelined form for PSC and SSC codes.

The PSC / SSC correlator includes a partial correlation part and a PSC / SSC correlation value output part. The partial correlation part may include the first partial correlation values by using the signals delayed 'the time taken for the signal to move between the chip and the chip by a multiple unit' and the first coefficients corresponding thereto. Generate a partial correlation value and a second partial correlation value. The PSC / SSC correlation value output unit generates and outputs the PSC correlation value and the SSC correlation value using the first partial correlation value, the second partial correlation value, second coefficients, and third coefficients. The PSC / SSC correlator may determine the timing under the control of the slot synchronization signal to generate the first partial correlation value, the second partial correlation value, the PSC correlation value, and the SSC correlation value.

According to another aspect of the present invention, there is provided a cell search method of wideband CDMA, which calculates partial correlation values commonly used for PSC correlation and SSC correlation from a received stream, and accumulates the partial correlation values to accumulate PSC correlation. Generating a value and an SSC correlation value; Accumulating the PSC correlation value over a plurality of slots and estimating a peak to generate a slot synchronization signal; Accumulating the SSC correlation value over a plurality of slots and estimating a peak to generate scrambling code group information of a cell to which a frame sync signal and a mobile station belong; And generating a scrambling code of a corresponding cell by taking a correlation between all scrambling codes belonging to a code group corresponding to the scrambling code group information and the received stream.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a block diagram illustrating a broadband CDMA cell searcher 400 of a pipeline structure according to an embodiment of the present invention. Referring to FIG. 4, the wideband CDMA cell searcher 400 includes a radio frequency (RF) module 410, a primary synchronization code (PSC) / secondary synchronization code (SSC) correlator 420, and a PSC detector ( 430, an SSC detector 440, and a pilot detector 450.

The RF module 410 receives airwaves of a wireless W-CDMA channel, extracts a baseband signal, and converts the baseband analog signal into a digital signal to output a received W-CDMA stream (RX). As described above, one frame of the received W-CDMA stream (RX) consists of 15 slots, one slot consists of 10 symbols, and one symbol consists of 256 chips. It is composed. One frame corresponds to 10 msec.

The PSC / SSC correlator 420 calculates partial correlation values (Xa, Xb) commonly used for PSC correlation and SSC correlation from the received stream (RX), and calculates the partial correlation values (Xa). , Xb) is accumulated to generate a PSC correlation value X and an SSC correlation value Y. The PSC / SSC correlator 420 stores the partial correlation values Xa and Xb in a predetermined memory and reuses them in calculating the PSC correlation value X and the SSC correlation value Y. Correlate the SSC code in a pipeline at the same time. The operation of the PSC / SSC correlator 420 is described in detail in FIGS. 5 and 6.

In the present invention, in order to perform PSC correlation and SSC correlation, partial correlation values for calculating the PSC correlation value (X) and the SSC correlation value (Y) by analyzing the conventional PSC code and SSC code ( Xa, Xb) were introduced. See the paper "Siemens and Texas Instruments, Generalized hierarchical Golay sequence for PSC with low complexity correlation using pruned efficient Golay correlators, 3GPP Tech.Doc., Tdoc R1-99554, Cheju, Korea, June 1999". The PSC correlation value X correlated with (RX) is shown in [Equation 1]. In Equation 1, SD _j is 16 signals in which the reception stream RX is delayed by a predetermined sample time unit (chip unit), and the first coefficients x _j and the second coefficients a _i are coefficients associated with the PSC code. .

[Equation 1]

If Equation 1 is expressed as an equation including partial correlation values Xa and Xb, Equation 2 is obtained. In Equation 2, the first partial correlation value Xa is one of eight chip signals from j = 1 to j = 8 of the delayed 16 chip signals and corresponding first coefficients x _j . This is the result of multiplying eight coefficients. The second partial correlation value Xb is accumulated by multiplying 8 chip signals from j = 9 to j = 16 of the delayed 16 chip signals by 8 coefficients of the first coefficients x _j corresponding thereto. One result. Using Equation 2, the SSC correlation value Y that correlates the SSC code and the reception stream RX is shown in Equation 3 below. In Equation 3, the third coefficients k _i are coefficients associated with the SSC code. In Equations 1 to 3, for partial correlation values Xa and Xb for 16 chip signals, again from i = 1 to i = 16. If this process is repeated 16 times, a correlation of 256 chips (one symbol) is made. Hereinafter, it is assumed that the PSC correlation value X and the SSC correlation value Y are generated in one symbol unit (256 chips) through an iteration operation on 16 chips.

[Equation 2]

[Equation 3]

Meanwhile, the PSC detector 430 accumulates the PSC correlation value X over a plurality of slots and estimates a peak among the accumulated values to generate a slot sync signal SLS. The SSC detector 440 accumulates the SSC correlation value Y over a plurality of slots, and performs a 16-point fast Hadamard transform (FHT) operation on the accumulated values, and estimates a peak from the FHT calculated value. The frame synchronization signal FRS and the scrambling code group information SCG of the cell to which the mobile station belongs are generated. FHT calculations are well documented in "Fast Transforms, Algorithms, Analysis, Applications," by D.F.Elliot and K.R.Rao, published in 1982 by NewYork, Academic Press. The pilot detector 450 correlates all scrambling codes belonging to a code group corresponding to the scrambling code group information SCG with the reception stream RX, and generates a scrambling code of the corresponding cell. When the mobile station acquires the scrambling code of the corresponding cell through the cell search, the mobile station succeeds in call connection and performs necessary communication through the connected cell.

5 is a block diagram illustrating the PSC / SSC correlator 420 of FIG. 4. FIG. 6 is a conceptual diagram of the PSC / SSC correlator 420 of FIG. 5. Referring to FIG. 5, the PSC / SSC correlator 420 includes a partial correlator 421 and a PSC / SSC correlation value output unit 427.

The partial correlator 421 uses the delayed signals and the first coefficients x _j corresponding to the received stream RX in multiples of the time taken for the signal to move between the chip and the chip. The first partial correlation value Xa and the second partial correlation value Xb which are the partial correlation values Xa and Xb are generated. Here, eight delayed signals and eight (x ₁ to x ₈ ) of the first coefficients (x _j ) are used first, so that the first partial correlation value (Xa) is calculated, and then the subsequent delayed eight The second partial correlation value Xb is calculated using eight signals (x ₉ to x ₁₆ ) among the signals and the first coefficients x _j . That is, as shown in Equation 2, the first partial correlation value Xa includes 8 chip signals among the delayed 16 chip signals and 8 coefficients among the first coefficients x _j corresponding thereto. is a result of multiplying (x ₁ to x ₈ ) and the second partial correlation value Xb is the other 8 chip signals among the delayed 16 chip signals and the first coefficients x _j corresponding thereto. This is the result of multiplying the other eight coefficients (x ₉ to x ₁₆ ).

In FIG. 5, the partial correlator 421 includes registers 422, a first signal selector 423, a first multiplier 424, a first accumulator 425, and a memory 426. It is provided. The registers 422 generate signals in which the time taken for the signal to move between the chip and the chip from the receive stream RX is delayed by a multiple of a unit. The registers 422 of FIG. 5 are the same as the registers 501 of FIG. 6.

The first signal selector 423 sequentially selects and outputs any one of the first coefficients x _j and one of the delayed signals corresponding thereto. The first multiplier 424 first multiplies the selected coefficient by the selected delay signal. The first accumulator 425 accumulates the first multiplication result. The memory 426 stores the cumulative result, outputs the first eight cumulative results (j = 1 to 8) as the first partial correlation value Xa, and accumulates the next eight times (j = 9 to 16). The result is output as the second partial correlation value Xb. Here, the registers 422, the first signal selector 423, the first multiplier 424, the first accumulator 425, and the memory 426 generate timing information from the slot synchronization signal SLS. It operates under the control of a predetermined controller (not shown).

Since the multipliers 502 of FIG. 6 perform a standardized operation, the first multiplier 424 has a structure with hardware minimized together with the first signal selector 423. Summer 503 and memory 504 of FIG. 6 correspond to first accumulator 425 and memory 426 of FIG. 5.

In FIG. 5, the PSC / SSC correlation value output section 427 includes a PSC correlation value output section 436 and an SSC correlation value output section 437. Here, the PSC correlation value output unit 436 and the SSC correlation value output unit 437 also operate under the control of a predetermined controller (not shown) that generates timing information from the slot synchronization signal SLS. The PSC correlation value output unit 436 includes an adder 428, a second coefficient selector 429, a second multiplier 430, and a second accumulator 431. The summer 428 sums the first partial correlation value Xa and the second partial correlation value Xb. The second coefficient selector sequentially selects the second coefficients a _i one by one and outputs 16 times (i = 1 to 16). The second multiplier 430 second multiplies the selected one of the second coefficients a _i by the sum result. The second accumulator 431 accumulates the second multiplication result over a symbol unit, and generates and outputs the PSC correlation value X. The second accumulator 431 repeatedly accumulates 16 times 16 times (i = 1 to 16) in order to output the cumulative result in symbol units as the PSC correlation value (X).

The summer 428 and the second multiplier 430 operate with the summers 505 to 507 and the multipliers 508 to 510 of FIG. 6, and thus the second signal selector 429 and the second signal selector 429. It is a structure with hardware minimized together. The summer 511 of FIG. 6 corresponds to the second accumulator 431 of FIG. 5.

In FIG. 5, the SSC correlation value output unit 437 includes a subtractor 432, a third coefficient selector 433, a third multiplier 434, and a third accumulator 435. The subtractor subtracts the second partial correlation value Xb from the first partial correlation value Xa. The third coefficient selector 433 sequentially selects and outputs the third coefficients k _i one by one. The third multiplier 434 a coefficient selected one of the second coefficients (a _i) to the subtraction result multiplied by the third. The third accumulator 435 accumulates the third multiplication result over a predetermined unit, and generates and outputs the SSC correlation value Y. The third accumulator 435 iteratively accumulates 16 times (i = 1 to 16) 16 times to output the cumulative result in symbol units as the SSC correlation value (Y).

The subtractor 432 and the third multiplier 434 are minimized together with the third signal selector 433 because the subtractors 512 to 514 and the multipliers 515 to 517 of FIG. It is a structure with hardware. The summer 518 of FIG. 6 corresponds to the third accumulator 435 of FIG. 5.

7 is a graph comparing synchronization acquisition time in serial and pipeline structures. The graph of FIG. 7 shows a synchronization signal and scrambling code acquisition time during an initial cell search in a flat fading channel (9.26 Hz Doppler). This simulation result is a measure when using the attenuation coefficients α = 0.5, β = 0.1 and γ = 0.1. In FIG. 7, the solid line is the result when performing the PSC correlation and the SSC correlation of the pipeline structure according to the present invention, and the dotted line is the result in the conventional serial structure which performs the sequential correlation. As shown in FIG. 7, in the pipeline structure according to the present invention, it can be seen that the acquisition time of the synchronization signal and the scrambling code appear more than three times faster in the initial cell search.

As described above, in the wideband CDMA cell searcher according to an embodiment of the present invention, the partial correlation values Xa and Xb that can be commonly used in the PSC / SSC code are calculated by the PSC / SSC correlator 420 to be predetermined. Through a method of storing in the memory 426 and reusing the same, a pipeline structure that simultaneously correlates PSC and SSC codes by a single correlator 420 is adopted. Therefore, since the first and second stage searches can be performed simultaneously by performing the correlation in the form of pipeline rather than the sequential search, it has superior search performance than the conventional sequential search method.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the broadband CDMA cell searcher according to the present invention stores and reuses partial correlation values in one circuit, thereby reducing hardware size by minimizing the summer, multiplier, etc. required for the data path. Can be. In addition, since the cell search time can be reduced through pipelined correlation, it is suitable for a small and low power system. In the conventional SSC correlation circuit, the hardware increases in proportion to the search index (number of chips), whereas in the present invention, since there is almost no separate delay cycle required for SSC correlation, an index (number of chips) that can be searched simultaneously without additional hardware is provided. It can greatly increase. Accordingly, the first stage search time can be reduced by easing the requirement for the number of peaks estimated by the first stage search.

Claims (20)

PSC / PSC that calculates partial correlation values commonly used for primary synchronization code (PSC) correlation and secondary synchronization code (SSC) correlation from a received stream, and accumulates the partial correlation values to generate a PSC correlation value and an SSC correlation value. SSC correlator; A PSC detector accumulating the PSC correlation value over a plurality of slots and estimating a peak to generate a slot synchronization signal; An SSC detector that accumulates the SSC correlation value over a plurality of slots, estimates peaks, and generates scrambling code group information of a cell to which a frame synchronization signal belongs and a mobile station; And And a pilot detector for correlating all the scrambling codes belonging to a code group corresponding to the scrambling code group information with the received stream to generate a scrambling code of a corresponding cell. The method of claim 1, wherein the PSC / SSC correlator, Storing and reusing the partial correlation values to perform correlation in a pipelined form simultaneously for PSC and SSC codes. The method of claim 2, wherein the PSC / SSC correlator, The first partial correlation value and the second partial correlation value are the first partial correlation value and the first partial correlation value, using the signals delayed by a multiple of the time taken for the signal to move between the chip and the chip, and corresponding first coefficients. A partial correlator for generating a value; And And a PSC / SSC correlation value output unit configured to generate and output the PSC correlation value and the SSC correlation value using the first partial correlation value, the second partial correlation value, second coefficients, and third coefficients. Featuring a wideband CDMA cell navigator. The method of claim 3, wherein the PSC / SSC correlator, And determining the timing under the control of the slot synchronization signal to generate the first partial correlation value, the second partial correlation value, the PSC correlation value, and the SSC correlation value. The method of claim 3, wherein the partial correlation unit, Registers for generating the delayed signals from the receive stream; A signal selector for sequentially selecting and outputting any one of the first coefficients and the delayed signals corresponding thereto; A multiplier for first multiplying the selected coefficient by the selected delay signal; An accumulator for accumulating the first multiplication result; And And a memory for storing the accumulated result and outputting the first partial correlation value and the second partial correlation value. The method of claim 5, wherein the PSC / SSC correlation value output unit, A PSC correlation value output unit configured to generate the PSC correlation value by using the sum of the first partial correlation value and the second partial correlation value and the second coefficients; And And a SSC correlation value output unit which generates the SSC correlation value by using the value obtained by subtracting the second partial correlation value from the first partial correlation value and the third coefficients. The method of claim 6, wherein the PSC correlation value output unit, A summer for summing the first partial correlation value and the second partial correlation value; A coefficient selector for sequentially selecting and outputting the second coefficients one by one; A multiplier for multiplying a selected one of the second coefficients by the sum result; And And accumulating the second multiplication result over a symbol unit to generate the PSC correlation value. The method of claim 6, wherein the SSC correlation value output unit, A subtractor for subtracting the second partial correlation value from the first partial correlation value; A coefficient selector for sequentially selecting and outputting the third coefficients one by one; A multiplier for multiplying a selected one of the second coefficients by the subtraction result; And And an accumulator for accumulating the third multiplication result over a symbol unit to generate the SSC correlation value. delete The method of claim 7 or 8, wherein the first partial correlation value, A result of multiplying 8 chip signals among the delayed 16 chip signals by 8 coefficients of the first coefficients corresponding thereto, and the second partial correlation value is obtained by stacking the other 8 chip signals among the delayed 16 chip signals. And a result obtained by multiplying the other eight coefficients among the first coefficients corresponding thereto. Calculating partial correlation values commonly used for PSC correlation and SSC correlation from a received stream, and accumulating the partial correlation values to generate a PSC correlation value and an SSC correlation value; Accumulating the PSC correlation value over a plurality of slots and estimating a peak to generate a slot synchronization signal; Accumulating the SSC correlation value over a plurality of slots and estimating peaks to generate scrambling code group information of a cell to which a frame synchronization signal belongs and a mobile station; And And generating a scrambling code of a corresponding cell by correlating all the scrambling codes belonging to a code group corresponding to the scrambling code group information with the received stream. The method of claim 11, wherein the generating of the PSC correlation value and the SSC correlation value comprises: And storing the partial correlation values and reusing them to simultaneously perform correlation in the form of a pipeline for PSC and SSC codes. The method of claim 12, wherein the generating of the PSC correlation value and the SSC correlation value comprises: The first partial correlation value and the second partial correlation value are the first partial correlation value and the first partial correlation value, using the signals delayed by a multiple of the time taken for the signal to move between the chip and the chip, and corresponding first coefficients. Generating a value; And And generating and outputting the PSC correlation value and the SSC correlation value using the first partial correlation value, the second partial correlation value, second coefficients, and third coefficients. Navigation method. The method of claim 13, wherein the generating of the PSC correlation value and the SSC correlation value comprises: And determining the timing under the control of the slot synchronization signal to generate the first partial correlation value, the second partial correlation value, the PSC correlation value, and the SSC correlation value. The method of claim 13, wherein the generating of the first partial correlation value and the second partial correlation value comprises: Generating the delayed signals from the received stream; Sequentially selecting and outputting any one of the first coefficients and one of the delayed signals corresponding thereto; First multiplying the selected coefficient by the selected delay signal; Accumulating the first multiplication result; And Storing the cumulative result and outputting the first partial correlation value and the second partial correlation value. The method of claim 15, wherein the outputting the PSC correlation value and the SSC correlation value comprises: Generating and outputting the PSC correlation value using the sum of the first partial correlation value and the second partial correlation value and the second coefficients; And And generating and outputting the SSC correlation value by using the value obtained by subtracting the second partial correlation value from the first partial correlation value and the third coefficients. The method of claim 16, wherein generating the PSC correlation value comprises: Summing the first partial correlation value and the second partial correlation value; Selecting and outputting the second coefficients one by one; Second multiplying a selected one of the second coefficients by the sum result; And Accumulating the second multiplication result over a symbol unit to generate the PSC correlation value. The method of claim 16, wherein generating the SSC correlation value comprises: Subtracting the second partial correlation value from the first partial correlation value; Selecting and outputting the third coefficients one by one; Third multiplying a selected one of the second coefficients by the subtraction result; And Accumulating the third multiplication result over a symbol unit to generate the SSC correlation value. delete The method of claim 17 or 18, wherein the first partial correlation value, A result of multiplying 8 chip signals among the delayed 16 chip signals by 8 coefficients of the first coefficients corresponding thereto, and the second partial correlation value is obtained by stacking the other 8 chip signals among the delayed 16 chip signals. And a result of multiplying the other eight coefficients among the first coefficients corresponding to each other.

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