KR100651473B1 - A high speed turbo decoder using pipe-line processing - Google Patents

Abstract

The present invention relates to a turbo code decoder, and more particularly to a hardware module using a pipeline technique in order to overcome the time delay caused by the iterative decoding of the turbo code decoder and to improve fast error correction capability. A fast turbo code decoder for constructing and decoding.

The high-speed turbo code decoder of the present invention includes a first decoding unit which receives an information signal and performs decoding, and a second decoding unit that performs decoding by inputting a decoding signal output through the information signal and the first decoding unit. N turbo coded decode cells, each of which consists of negative turbo coded decode cells connected in series to each other to perform decoding; And N-1 memory modules that are serially connected to each other and sequentially transfer the information signals to the corresponding turbo coded decode cells for decoding each clock.

Therefore, according to the present invention, it is possible to considerably speed up the decoding time by updating the hardware configuration by using a pipeline method for the time delay resulting from the repetitive performance of the conventional turbo code decoder. In particular, there is an advantage that can be applied to the implementation of a system that requires strong error correction in real time.

Turbo code, error correction

Description

A high speed turbo decoder using pipe-line processing             

1 is a block diagram of a general turbo coder;

2 is a block diagram of a conventional turbo code decoder;

3 is a block diagram of a fast turbo code decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

324: first decoding unit 328: second decoding unit

320, 340, 360: decoding cell 301, 302: memory module

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a turbo code decoder, and more particularly, to a turbo code decoder that can speed up a decoding time using a pipeline technique.

로 접근한다고 증명되어 지금까지의 에러 정정 코드중 가장 좋은 BER성능을 보이고 있다. 이와 같이 강력한 에러 정정 능력으로 인해 최근 해당 분야의 연구가 집중되고 있다.
The turbo code has a bit error rate (BER) at a code rate of 1/2 and an Eb / nO of 0.7 dB, which is nearly the performance of the Shannon limit, which is recognized as a mathematical error correction limit.

It has been proved to have the best BER performance among the error correction codes so far. Due to such strong error correction ability, recent researches in the relevant fields have been concentrated.

First, a general turbo code encoding process will be described with reference to the turbo encoder of FIG. 1.

(102)를 얻고, 정보신호(101)를 N 정보비트의 프레임과 동일한 크기를 갖는 인터리버(interleaver)(110)를 통과시켜 얻은 신호(103)를 또 다른 제2 RSC부호기(120)를 통과하여

(104)를 얻은 후 송신하게 된다. 따라서 터보부호의 출력은 제 1 RSC부호기(102)의 출력뿐만 아니라 인터리버(110)를 통해 변형된 출력으로 인해 이중의 패리티 정보를 지니게 된다. 그래서, 터보부호기에서 원하는 부호율을 얻기 위해

(102)과

(104)를 천공기(130)를 통해 출력신호를 천공한다. 예를 들어, 부호율을 1/2로 하기 위해서는

(102)과

(104)를 번갈아 한번씩 출력되도록 천공하면 된다. 이렇게 천공하여 최종적으로 얻은 패리티 비트 Y(105)를 X(101)와 함께 전송한다.
The turbo code has a structure in which two simple RSC (recursive systematic convolutional) coders, which make a parity symbol using an input composed of a frame of N information bits, are connected in parallel. Referring to FIG. 1, the turbo encoder sets an information bit as one output X 101, and passes the information signal 101 through the first RSC encoder 100.

(102), the signal 103 obtained by passing the information signal 101 through an interleaver (110) having the same size as a frame of N information bits is passed through another second RSC encoder (120)

After getting 104, it will be sent. Accordingly, the output of the turbo code has dual parity information due to the output of the first RSC encoder 102 as well as the output modified through the interleaver 110. So, to get the desired code rate in the turbo encoder

102 and

The punch 104 outputs the output signal through the puncher 130. For example, to make the code rate 1/2

102 and

Alternately, drill 104 so that it is output one by one. The parity bit Y 105 obtained through the puncturing is transmitted together with the X 101.

In order to decorate the codewords encoded by the turbo code, a decoder as shown in FIG. 2 is connected in series and decoded. Each decoder must have a soft output on its soft input. Unlike conventional decoders such as concatenated codes, turbo coded decoders can perform additional decoding by exchanging additional information between two decoders. do.

As shown in FIG. 2, decoding of a codeword encoded by a turbo code is as follows.

First, when X 201 and Y 202 are signals through which a codeword of a turbo encoder as shown in FIG. 1 passes through a channel, X 201 is a signal through which information bits pass through a channel, and Y 202 is represented by a signal. The parity bit is the signal that passed through the channel. First, X 201 is sent to the first decoder, and the received parity signal Y 202 is sent to the first decoder DEC1 210 and the second decoder DEC2.

The first decoder 210 decodes using X 201 and Y 202 and then interleaves the output 205 of the first decoder 210 again with the signal 206 and Y 202. Decode by using the second decoder 230. At this time, the first decoder 210 using the signal 208 deinterleaving the output signal 207 of the second decoder 230 and the received signals X 201 and Y 202 for repeated decoding. Decrypt again. This iterative decoding can be done until the desired performance is achieved.

As described above, the turbo code decoder performs iterative decoding using feedback to two decoders. If the number of iterations is N, the feedback loop must be rotated N times. Therefore, if the time taken for the first decoding is T ', the total decoding time T for the N times repeated becomes N * T'.

When a large amount of data needs to be sent in real time, such as a DVD system or digital broadcasting, which is currently important, a high speed error correction system is required.

In order to use the turbo code with excellent error correction capability, fast error correction, which is one of the requirements, does not satisfy this problem. This is because, as described above, since the same operation is repeated several times in a simple hardware configuration, when the information should be transmitted in real time, it has to wait until the previous information is decoded (N * T₁).

The present invention is to solve the above problems, turbo code decoder that can perform a fast error correction by using a pipelined technique of changing the time delay on the hardware caused by several repetitions to the concept of space at the same time The purpose is to provide.

In order to achieve the above object, a high-speed turbo code decoder according to the present invention includes a first decoder for receiving an information signal and performing decoding, and a decoding signal output through the information signal and the first decoder as an input. N turbo code decoding cells configured to perform decoding by connecting a turbo code decoding cell comprising a second decoder to perform decoding; And N-1 memory units connected in series to each other and sequentially transferring the information signals to the corresponding turbo coded decoding cells for decoding each clock.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a pipelined turbo decoder according to the present invention, wherein the decoder of the present invention includes N decoder cells 320, 340, ..., 360 and N-1 memory modules 301, 302 connected in series with each other. ..)

 First, the information signal R 310 is sent to the first decoder cell 320. Here, the information signal R 310 refers to the values of X 201 and Y 202 in FIG. 2, and the decoding procedure of the information signal R 310 in the first decoder cell 320 is similar to that of FIG. 2. same. That is, information corresponding to X 201 of the information signal R 310 is sent to the first decoding unit 324 of the first module 320, and the information corresponding to Y 202 is transmitted to the first decoding unit 324. And a decoded signal 311 which is sent to the second decoder 328 to decode once. At this time, the interleaver is included in the first decoder 324 and the deinterleaver is included in the second decoder 328.

Meanwhile, the first information signal R 310 is stored in the first memory module 301. This is to send the information signal R to the second decoder cell 340.

Now, by using the decoded signal 311 obtained from the first decoder cell 320 and the information signal stored in the first memory module 302, a second decoding is performed in the same manner as in the first module 320 to perform the decoded signal 312. You get At this time, the information signal in the first memory module 301 is transferred to the second memory module 302 and sent to the decoded signal 312 and the third decoder cell 340.

Meanwhile, the first decoder cell 320 receives another information signal and performs decoding in the same manner as described above. That is, when the first information of the plurality of information is input to the first decoder cell 320 according to the process of FIG. 3, when the information is passed to the second decoder cell 340, the second information R is input again. do. When the first information is passed to the third decoder cell, the second information is passed to the second decoder cell 340 and the third information is input to the first decoder cell 320.

In this manner, the time delay occurs in the same manner as the conventional method until the first information is output as the decoded signal C value. However, from the following information, the conventional method has to wait for N times of repetition, whereas the decoder of the present invention outputs the decoded signal C at the first repetition time.

Therefore, if the turbo code decoder configured to perform N repetitions receives M pieces of information, the conventional method performs N repetitions for each input data, resulting in a total processing time of N * M * T1. On the other hand, in the turbo code decoder cell constructed using the pipeline scheme as shown in FIG. 3, N iterations are performed only for the first information, and after that, the next data is decoded and output for each iteration time. 1) * T1 can significantly reduce the decoding time.

As described above, according to the present invention, it is possible to considerably speed up the decoding time by updating the hardware configuration by using a pipeline method for the time delay coming from the repetitive performance of the conventional turbo code decoder. In particular, there is an advantage that can be applied to the implementation of a high-density DVD (DVD) that requires a strong error correction in real time and a digital broadcast system for error-free broadcast reception.

Claims (1)

In the turbo decoder to decode the signal encoded and transmitted by the turbo encoder, A turbo code decoder cell comprising a first decoder that receives an information signal and performs decoding and a second decoder that performs decoding by inputting the information signal and a decoding signal output through the first decoder are serially connected to each other. N turbo coded decoded cells connected to perform decoding; And A high speed turbo code decoder using a pipeline, comprising: N-1 memory modules sequentially connected to each other and sequentially transmitting the information signal to a corresponding turbo code decoding cell where decoding is performed for each clock.

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