KR100650521B1 - Clock and data recovery circuit and method using it - Google Patents

Abstract

The clock / data recovery circuit of the present invention includes a phase detector for detecting a phase difference between input data and a generation clock and outputting a phase difference signal, a charge pump for adjusting a voltage at an output terminal according to the phase difference signal, and a preset reference. Compare the voltage and the voltage of the charge pump output stage to increase the integrated voltage when the charge pump output terminal voltage is greater than the reference voltage, and to reduce and output the integral voltage when the charge pump output stage voltage is less than the reference voltage A voltage integrator for outputting a control voltage by adding a voltage integrator, an output terminal voltage of the charge pump and an integrated voltage of the differential voltage integrator, and a voltage controlled oscillator for oscillating a generation clock having a frequency proportional to the control voltage. do.

The clock / data recovery operation of the present invention is a macroadjustment process at the beginning of operation by a low frequency boosting loop including a differential voltage integrator, and a fine adjustment process by a fine fixed loop in which a phase detector performs a main function except a differential voltage integrator. It is divided into two parts.

Clock Recovery, Data Recovery, Clock Sync, Phase Detection, Phase Lock

Description

CLOCK AND DATA RECOVERY CIRCUIT AND METHOD USING IT}             

1 is a block diagram showing a conventional clock / data recovery circuit;

2 is a block diagram showing a clock / data recovery circuit of the present invention;

3 is a graph showing the relationship between the charge pump output voltage and the oscillation frequency of the clock / data recovery circuit of the present invention;

4 is a graph showing the change over time of the charge pump output voltage of the clock / data recovery circuit of the present invention;

5 is a graph showing a change over time of the output voltage of the differential voltage amplifier of the clock / data recovery circuit of the present invention;

6 is a graph showing a change over time of the clock frequency oscillated in the clock / data recovery circuit of the present invention;

7 is a circuit diagram showing the structure of a phase detector and a charge pump used in an embodiment of the present invention;

8 is a circuit diagram showing the structure of a phase detector used in another embodiment of the present invention;

9 is a circuit diagram showing the structure of a charge pump used in another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

22: phase detector 24: charge pump

25: voltage mixer 26: voltage controlled oscillator

27: differential voltage integrator 28: data recovery unit

The present invention relates to a clock / data recovery circuit, and more particularly, to a clock / data recovery circuit for setting frequency and phase to input data.

In the field of digital data communication, the operation timing of the receiving side and the transmitting side must be aligned so that each other can communicate smoothly and accurately. For this purpose, the frequency and phase of the clock, which is the reference of operation of the receiver and the transmitter, should be synchronized with each other. In addition, by fitting the received signal mixed with the high-frequency noise signal to the transition form of the reference clock, noise can be removed from the received signal.

It is common for the receiving side to synchronize with the frequency and phase of the clock required by the calling party. For this purpose, the calling party releases the synchronization clock separately from the communication data so that the calling party uses the synchronization clock as a reference clock. If the transmitting side transmits digital communication data in accordance with a synchronous clock, the receiving side extracts a reference clock from the received data. The latter method is widely used for the efficiency of communication channel usage.

The clock / data recovery circuit is to restore a reference clock from the received (input) received data and to remove noise of the received data with the restored reference clock. FIG. 1 illustrates a conventional clock / data recovery circuit. It is. The illustrated clock / data recovery circuit includes a frequency acquisition loop loop2 for acquiring the frequency of the reference clock included in the input data, and a phase locked loop for aligning the phase of the generated clock with the reference clock included in the input data. loop1).

The initial state of the loop switch 11 of the clock / data recovery circuit is connected to the frequency acquisition loop loop2. In the frequency acquisition loop loop2, a phase / frequency detector 13 compares the output clock frequency of the voltage-controlled oscillator with the frequency of the input data at the initial stage of the frequency acquisition loop loop2. 2 charge pump 15 is driven to adjust the control voltage of the voltage control oscillator (16, Voltage Control Oscillator). As a result, when the output clock frequency of the voltage controlled oscillator 16 matches the frequency of the input data, the loop switch 11 is switched to the phase locked loop loop1.

In the phase locked loop loop1, the first charge pump 14 is driven by the phase shift of the clock output from the voltage controlled oscillator 16 and the phase of the input data so that the frequency of the output clock of the voltage controlled oscillator 16 is increased. It varies slightly, and the phase of the output clock and the input data are aligned in the process of minute variation of the clock frequency.

The conventional clock / frequency recovery circuit may be embodied so as to omit the second charge pump 15 and to serve as the first charge pump 14, depending on the implementation. However, the loop and phase / phase using the phase detector 12 may be implemented. The loop using the frequency detector 13 is always separated.

Since the input data is a variable data value rather than a clock, no transition occurs every clock period. When the phase / frequency detector 13 tries to adjust the correct phase and frequency, the frequency decreases again in the continuous data portion. This is because ripples are severely generated at the output frequency, and the phase and frequency detector 13 alone cannot accurately match the phase and frequency.

On the other hand, the phase detector 12 cannot be used in an initial state where the frequency of the input data cannot be determined because the two signals to be compared can operate only when the frequencies are similar.

In the conventional clock / frequency recovery circuit, since the frequency of the generated clock is different from the input data frequency at the beginning of the clock and data recovery operation, the clock / frequency recovery circuit adjusts the frequency to a somewhat similar frequency using a phase / frequency detector. It helps to overcome the narrow frequency detection range of the phase detector.

However, in the prior art, since switching for two loops is required, additional circuits necessary for switching and determining whether to switch are required, and thus there is a problem in design convenience and cost, and switching is an unstable factor in operation. There is also a problem in terms of stability of the entire circuit.

The present invention has been made to solve the above problems, and an object thereof is to provide a clock / data recovery circuit having a low manufacturing cost.

It is another object of the present invention to provide a clock / data recovery circuit using only a phase detector and having a wide frequency acquisition range.

Another object of the present invention is to provide a clock / data recovery circuit in which switching to a driving loop does not occur during a clock / data recovery operation.

Another object of the present invention is to provide a clock / data recovery circuit for recovering clock and data without using a separate external reference frequency.

Clock / data recovery circuit of the present invention for achieving the above object,
A phase detector for detecting a phase difference between the input data and the generated clock and outputting a phase difference signal, a charge pump for adjusting the voltage at the output terminal according to the phase difference signal, a preset reference voltage and the voltage at the charge pump output terminal A differential voltage integrator for increasing and outputting an integrated voltage when the charge pump output terminal voltage is greater than the reference voltage, and decreasing and outputting an integrated voltage when the charge pump output terminal voltage is smaller than the reference voltage; and an output terminal voltage of the charge pump. And a voltage mixer for outputting a control voltage by adding the integrated voltage of the differential voltage integrator and a voltage controlled oscillator for oscillating a generation clock having a frequency proportional to the control voltage.

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Clock / data recovery method of the present invention for achieving the above object,
Oscillating a clock having a frequency proportional to a control voltage obtained by adding the first voltage and the second voltage, and fixing the first voltage and gradually increasing the second voltage to increase the frequency of the clock to an approximate target value. And when the frequency of the clock reaches the approximate target value, compares the phase of the clock with the increased frequency and the external input data, adjusts the first voltage according to a phase difference, and phases the clock and the external input data. Coinciding with and lowering the first voltage and raising the second voltage to have a final convergence value.

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The restored data is output by synchronizing the input data with the oscillated clock.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

( Example  One)

The clock / data recovery circuit of this embodiment shown in FIG. 2 includes a phase detector 22, a charge pump 24, a differential voltage integrator 27, a voltage mixer 25, and a voltage controlled oscillator 26. Is made of. In order to maintain the potential of the output, an integral capacitor C3 is added to the differential voltage integrator 27 and pumping capacitors C1 and C2 are added to the charge pump 24. A data recovery unit 28 is further included for generating alignment data in which the input data is aligned with the generation clock of the voltage controlled oscillator 26.

The phase detector 22 of the present embodiment is for synchronizing the input data with the generated clock output by the voltage controlled oscillator 26. The phase detector 22 coincides with the falling edge of the clock with the transition time of the individual bit values of the data. The final purpose is to implement a hogge phase detector as shown in FIG. The phase detector 22 outputs the UP signal longer than the DN signal if the phase of the input data is earlier than the phase of the clock, and outputs the DN signal longer than the UP signal if it is behind the clock.

The charge pump 24 receiving the UP signal performs an operation of adding positive charge to the pumping capacitors C1 and C2 to increase the charge pump output voltage Vf, and the charge pump receiving the DN signal. 24 performs an operation of removing the positive charge accumulated in the pumping capacitor to lower the charge pump output voltage Vf.

The differential voltage integrator 27 is implemented with a trans-conductance amplifier and an added integrating capacitor C3. The output terminal of the transconductance amplifier is connected to the integrating capacitor C3, and both input terminals are connected. It is connected to the output terminal of the charge pump 24 and the reference voltage (Vref) terminal. The amplification value of the differential voltage integrator 27 should be adjusted to be an appropriate value. If the amplification value is too large, variation in the output value of the differential voltage integrator is accelerated, and a ripple occurs in the frequency value of the generated clock. If the amplification value is too small, the variation in the differential voltage integrator 27 output value is slowed. The time required for frequency acquisition of the clock / frequency recovery circuit becomes long.

In the present exemplary embodiment, the differential voltage integrator 27 increases the voltage Vg of the integrated capacitor when the charge pump output voltage Vf is greater than the charge pump output voltage Vf compared to the reference voltage Vref. If the pump output voltage Vf is smaller, the voltage Vg of the integrating capacitor is reduced, thereby performing a function similar to that of the charge pump.

The voltage mixer 25 determines a control voltage Vc to be input to the voltage controlled oscillator 26 by applying a constant equation to the output voltage Vf of the charge pump and the output voltage Vg of the differential voltage integrator. The formula to be applied is Vc = Ka.Vf + Kb.Vg (Ka, Kb is a constant).

The frequency of the generated clock output from the voltage controlled oscillator 26 has a characteristic in direct proportion to the input voltage.

An output terminal of the charge pump 24, one end is connected to the output terminal and the other end is connected to the first capacitor (C1) (R1); A first capacitor C1 having one end connected to the resistance element R1 and the other end connected to ground; And a second capacitor C2 having one end connected to the output terminal and the other end connected to the ground. The added capacitor and the resistance element serve as a pumping capacitor which accumulates the charge pumped by the charge pump and maintains the output voltage, and serves as a kind of low pass filter which sets the bandwidth and provides stability.

The clock / data recovery operation of the clock / data recovery circuit of this embodiment will be described below. The clock / data recovery operation of the present embodiment includes a macro adjustment process using a cyclic loop (low frequency boosting loop) including a differential voltage integrator 27 and a cyclic loop (fine fixed loop) excluding the differential voltage integrator 27. The fine tuning process is performed simultaneously by means of a fine loop.

Initially, the operation of the low frequency boosting loop becomes more dominant. According to the initial state, the charge pump output voltage (first voltage, Vf) is set to be higher than the reference voltage Vref, and the initial operation of the voltage controlled oscillator 26 is performed. Since the oscillation frequency must be lower than the target frequency, the differential voltage integrator output voltage (second voltage, Vg) is set to a sufficiently low value. Since the frequency of the initial generation clock oscillated in the voltage controlled oscillator 26 is significantly lower than the data rate of the inputted data, the average output of the phase detector 22 output is " 0 ". That is, in the case of the hog type phase detector of FIG. 5, the periods during which the UP signal and the DN signal are activated are the same. Therefore, the charge pump output voltage Vf has a constant value except for the ripple, which means that the frequency adjustment function by the phase detector 22 and the charge pump 24 does not occur effectively.

On the other hand, the differential voltage integrator 27 receives a fixed reference voltage (Vref) and a charge pump output voltage (Vg) unchanged in the initial state, the difference value is amplified by a specified multiple (Gm) to integrate the capacitor It charges (C3), which causes the control voltage (Vc) to increase slowly. As the differential voltage integrator output voltage Vg increases, the equation (Vc = Ka · Vf + Kb · Vg) is applied by the voltage mixer 25, so that the control voltage Vc also increases. Therefore, in the initial state, the frequency of the generated clock output by the voltage controlled oscillator 26 gradually increases from a low frequency to a high frequency.

When the increasing frequency of the generated clock falls within the detection range of the phase detector 22, the phase detector 22 which outputs only an average "0" ripple until then shows an output of increasing average value. That is, the process of adjusting the frequency and phase by the phase detector 22 and the charge pump 24 (fine fixed loop) is activated.

Although the operation of the differential voltage integrator 27 does not stop at this time, however, once the micro fixed loop is activated, since the variation of the charge pump output voltage Vf is much faster than the differential voltage integrator output voltage Vg, the control voltage The variation in Vc is driven by a fine locked loop that varies the charge pump output voltage Vf. The variation of the control voltage Vc due to the fine fixed loop changes the generation clock frequency output by the voltage controlled oscillator 26. During this process, if the generation clock and the frequency and phase of the input data coincide with each other, the charge pump 24 pumps an average charge of zero. This is called initial locking.

Although the frequency and phase of the generated clock and the input data coincide with the initial locking, the differential voltage integrator output voltage (Vg) continues to increase slowly because the charge pump output voltage (Vf) is still higher than the reference voltage (Vref). To maintain phase alignment, the fine lock loop causes the charge pump output voltage (Vf) to decrease. The process continues until the charge pump output voltage Vf becomes equal to the reference voltage Vref, and once the charge pump output voltage Vf and the reference voltage Vref become equal, the charge pump output voltage Vf ), The differential voltage integrator output voltage (Vg), the control voltage (Vc) and the oscillation frequency of the voltage controlled oscillator 26 are fixed. This time is called last locking.

If the reference voltage Vref is given to a rather high value, the first locking does not occur when the charge pump output voltage Vf is higher than the reference voltage Vref as described above. Since the charge pump output voltage Vf is lower than the reference voltage Vref at the time of initial locking, the differential voltage integrator 27 removes the charge of the integrating capacitor C3 to drop the output terminal voltage Vg. In order to maintain phase alignment, the fine locked loop causes the charge pump output voltage (Vf) to increase. The process continues until the charge pump output voltage Vf becomes equal to the reference voltage Vref, such that the charge pump output voltage Vf, the differential voltage integrator output voltage Vg, the control voltage Vc and the voltage controlled oscillator The oscillation frequency of (26) is fixed.

In order to ensure smooth operation over a wider frequency range, it is desirable to set the reference voltage Vref in the center region on the frequency-voltage curve of the voltage controlled oscillator 26.

The phase detector 22 of this embodiment performs not only phase locking but also frequency acquisition. However, the phase detector 22 has to be close to the target frequency in order to perform the frequency acquisition operation, and the differential voltage integrator 27 performs the operation of bringing the initial generated clock closer to the target frequency.

The clock / data recovery operation according to the present embodiment consists of two iterations of a low frequency boosting loop and a fine fixed loop. There is no switching between loops, and the two loops are always performed together, and the phase detector 22 is performed. Is different from the prior art in that the function is performed not only in the fine fixed loop but also in the low frequency boosting loop.

The data recovery unit 28 of this embodiment is the same as the prior art implementation, and restores data based on the generated clock oscillated at the frequencies secured in the two loops.

3 is a graph showing the relationship between the charge pump output voltage (Vf) and the oscillation frequency over time, line A is the charge pump output voltage (Vf) and the oscillation frequency when the differential voltage integrator output voltage (Vg) is the initial value Line B is the characteristic curve of the charge pump output voltage (Vf) and oscillation frequency when the differential voltage integrator output voltage (Vg) is initially locked. Line C is the last of the differential voltage integrator output voltage (Vg). It is the characteristic curve of the charge pump output voltage (Vf) and oscillation frequency when the value is locked.

The oscillation frequency (point a) according to the initial control voltage Vc is gradually increased by the operation of the low frequency boosting loop of the present embodiment, and when it is within the detection range of the fine locked loop, it is initially locked by the fine locked loop (point b). ). Subsequently, due to the interaction between the low frequency boosting loop and the fine fixed loop, the charge pump output voltage Vf is reduced and fixed to the reference voltage Vref while maintaining the same oscillation frequency (point c).

Fig. 4 is a MATLAB simulation showing the operation of the clock / data recovery circuit of this embodiment when the generation clock frequency falls within the detection range of the phase detector 22, and includes the charge pump output voltage Vf and the differential voltage integrator output voltage ( Vg) and oscillation frequency are shown as time functions. If the difference between the oscillation frequency and the input data frequency is larger than the detection range of the phase detector 22, the charge pump output voltage Vf maintains its initial value, and the differential voltage integrator output voltage Vg and the oscillation frequency are linearly Increasing, this section is omitted for clarity. As the oscillation frequency approaches the input data frequency, the peak-peak voltage of the charge pump output voltage Vf becomes large. After the initial locking, the charge pump output voltage Vf drops and the rate of increase of the differential voltage integrator output voltage Vg is slowed down according to the reduced difference between the reference voltage Vref and the charge pump output voltage Vf. When the charge pump output voltage Vf is fixed to the reference voltage Vref through the above process, the differential voltage integrator output voltage Vg does not change any more. The control voltage Vc and the oscillation frequency maintain the same value as the input data frequency from the first locking to the last locking.

( Example  2)

The clock / data recovery circuit of this embodiment replaces the phase detector 22 and the charge pump 24 with the phase detector shown in FIG. 8 and the charge pump shown in FIG. 9 in the clock / data recovery circuit of the first embodiment. will be.

The phase detector 22 used in the present embodiment includes: a first D flip-flop for receiving data and a clock; And a second D flip flop that receives an output of the first D flip flop and an inverted clock.

The charge pump 24 used in the present embodiment includes: a first bypass switch unit that is turned on when the input and the output of the first D flip-flop are the same so that power current flows through the bypass path; A first pumping switch unit which is turned on when the first bypass switch is turned off to perform a pumping operation with a power current (pumping current); A second bypass switch unit which is turned on when the input and the output of the second D flip-flop are the same so that power current flows through the bypass path; And a second pumping switch unit which is turned on when the second bypass switch is turned off to perform a pumping operation with a power current (pumping current).

The structures of the first D flip-flop and the second D flip-flop are structures used in a general hogge type phase detector, and the first D flip-flop receives an externally input data and a generation clock, and has an internal clock. A signal is generated to determine whether the phase is slower. The second D flip-flop receives the output of the first D flip-flop and the generated clock inverted to determine whether the phase of the internal clock is faster. Generates a signal to

It is normal that the first D flip-flop always has the same value as the input and output, but when the falling edge of the clock occurs a predetermined time earlier than the transition point of the input data, the first D flip-flop is input. The discrepancy time of the second D flip-flop input / output becomes longer than the discrepancy time of the / output. The inconsistency time of the first D flip-flop input / output causes pumping to increase the charge, and the inconsistency time of the second D flip-flop input / output causes pumping to decrease the charge. Pumping is done to reduce charge by as much as possible.

On the contrary, if a falling edge of the clock occurs a predetermined time later than a transition time of the input data, pumping is performed to increase the charge by the predetermined time.

The first pumping switch unit used in the implementation of FIG. 9 includes a first pumping PMOS transistor P1 having a drain voltage connected to a drain and an output terminal connected to a source to form a pumping path, and a reference voltage applied to a gate. And a second pumped morph transistor (P2).

The first bypass switch illustrated in FIG. 1 includes a first bypass PMOS transistor P11 having a drain voltage connected to a drain and a ground connected to a source to form a bypass path, and a first D flip-flop input connected to a gate. ); A second bypass PMOS transistor (P12) having a supply voltage side connected to the drain and a ground connected to the source to form a bypass path, and an inverted value of the first D flip-flop output connected to the gate; A third bypass PMOS transistor (P21) having a supply voltage side connected to the drain and a ground connected to the source to form a bypass path, and a first D flip-flop output connected to the gate; And a fourth bypass PMOS transistor P22 having a drain voltage connected to the drain and a ground connected to the source to form a bypass path, and an inverted value of the first D flip-flop input connected to the gate.

The illustrated second pumping switch unit has a pumping path connected to an output terminal of the drain and a ground side of the source to form a pumping path, and a first pumping nMOS transistor N1 and a second pumping nMOS transistor to which a reference voltage is applied to a gate. (N2).

The second bypass switch illustrated in FIG. 1 includes a first bypass nMOS transistor N11 having a drain voltage connected to a drain and a ground side connected to a source to form a bypass path, and a second D flip-flop input connected to a gate. ); A second bypass nMOS transistor (N12) having a power supply voltage connected to the drain and a ground connected to the source to form a bypass path, and an inverted value of the second D flip-flop output connected to the gate; A third bypass nMOS transistor (N21) having a power supply voltage connected to the drain and a ground side connected to the source to form a bypass path, and a second D flip-flop output connected to the gate; And a fourth bypass NMOS transistor N22 having a drain voltage connected to the drain and a ground connected to the source to form a bypass path, and an inverted value of the second D flip-flop input connected to the gate.

The drains of the first pumped PMO transistor P1, the first bypass PMO transistor P11, and the second bypass PMO transistor P12 are connected at node a, and the second pumped PMO transistor P P2), the third bypass PMOS transistor P21 and the fourth bypass PMOS transistor P22 may have drains connected at node b, and the first pumping n-MOS transistor N1 and the first bypass N may be connected to each other. The source transistor N11 and the second bypass NMOS transistor N12 are connected to respective sources at node c, and the second pumping nMOS transistor N2 and the third bypass NMOS transistor N21 and the fourth are respectively connected to each other. In the bypass NMOS transistor N22, each source is connected at node d.

The D flip-flop mouths are formed in the gates of the first pumping PMOS transistor P1, the second pumping PMOS transistor P2, the first pumping NMOS transistor N1, and the second pumping NMOS transistor N2. A reference voltage (Vcommon) with an average of logic low and logic high at the output is applied.

A biased PMOS transistor for imparting a bias resistance value between the node a and the power supply voltage terminal and between the node b and the power supply voltage terminal, respectively, between the node c and the ground terminal, and between the node d and the ground terminal. It is preferable that bias bias transistors are respectively provided for imparting a bias resistance value therebetween.

According to the clock / data recovery circuit of this embodiment, the same effects as in the case of the first embodiment can be achieved.

In addition, since the XOR gate is directly implemented in the current path of the charge pump, there is no delay time caused by the XOR gate, and thus, even when the phase difference between the data and the clock is small, the pumping can be performed in proportion to it. Since switching is performed by adjusting the voltage applied to the source or gate terminal of the MOS transistor, the effect of preventing the noise current by the parasitic capacitor of the MOS transistor is additionally obtained.

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

 By implementing the clock / data recovery circuit according to the present invention, a low frequency boosting loop and a fine fixed loop having a wide frequency acquisition range with a single phase detector have an effect of achieving cost reduction.

There is no switching to the drive loop during the clock / data recovery operation, which stabilizes the drive operation.

A wide frequency acquisition range is achieved without using an external reference frequency, thereby preventing the cost increase due to the separate reference frequency generator.

Claims (7)

A phase detector for detecting a phase difference between the input data and the generation clock and outputting a phase difference signal; A charge pump for adjusting the voltage at the output terminal according to the phase difference signal; Compare the preset reference voltage with the charge pump output stage voltage and increase the integrated voltage when the charge pump output stage voltage is greater than the reference voltage, and decrease the integral voltage when the charge pump output stage voltage is less than the reference voltage. An output differential voltage integrator; A voltage mixer for outputting a control voltage by summing the output terminal voltage of the charge pump and the integral voltage of the differential voltage integrator; And A voltage controlled oscillator for oscillating a generation clock having a frequency proportional to the control voltage Clock / data recovery circuit comprising a. The method of claim 1, wherein the differential voltage integrator comprises a transconductance amplifier and an integrated capacitor, And an output terminal of the transconductance amplifier is connected to the integrating capacitor, one input terminal is connected to an output terminal of the charge pump, and the other input terminal is applied with a predetermined reference voltage. According to claim 1, At the output terminal of the charge pump, One end of which is connected to the output terminal and the other end of which is connected to the first capacitor; A first capacitor having one end connected to the resistance element and the other end connected to ground; And A second capacitor having one end connected to the output terminal and the other end connected to ground The clock / data recovery circuit further comprising. The method of claim 1, wherein the phase detector, A first D flip-flop that receives data and a clock; And A second D flip-flop that receives a clock inverted from the output of the first D flip-flop Including; The charge pump, A first bypass switch unit which is turned on when the input and the output of the first D flip-flop are the same so that a pumping current flows through the bypass path; A first pumping switch unit which is turned on when the first bypass switch is turned off to perform a pumping operation with a pumping current; A second bypass switch unit which is turned on when the input and the output of the second D flip-flop are the same so that a pumping current flows through the bypass path; And A second pumping switch unit which is turned on when the second bypass switch is turned off to perform a pumping operation with a pumping current; Clock / data recovery circuit comprising a. The method according to any one of claims 1 to 4, A data recovery unit for outputting restoration data from which a noise signal is removed by synchronizing the input data with the generation clock; The clock / data recovery circuit further comprising. Oscillates a clock of a frequency proportional to the control voltage obtained by adding the first voltage and the second voltage, Fixing the first voltage and gradually increasing the second voltage to increase the frequency of the clock to an approximate target value; When the frequency of the clock reaches the approximate target value, the clock of the increased frequency and the phase of the external input data are compared, and the first voltage is adjusted according to the phase difference to match the phase of the clock and the external input data. step; And Lowering the first voltage and increasing the second voltage to have a final convergence value Clock / data recovery method comprising a. The method of claim 6, Synchronizing the input data with the oscillated clock to output recovered data The clock / data recovery method further comprising.

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