KR100647658B1 - Plasma display panel - Google Patents

Abstract

A plasma display panel is disclosed. The present invention provides a plurality of substrates including a front substrate and a back substrate, a dielectric wall disposed between the substrates and defining discharge cells together with the substrates, and separately disposed along the circumference of the discharge cells and embedded in the dielectric walls. A discharge electrode formed at the outermost portion of the dielectric wall and preventing an overetch of the dielectric wall disposed in the discharge cell during development; and red, green, and blue applied in the discharge cell. Phosphor layer of; includes, the over-etching prevention wall extending from the dielectric wall is provided in the non-display area, the over-etching of the form surrounding the dielectric wall even if the over-etching phenomenon occurs by the developer during the process of manufacturing the dielectric wall Since the barrier wall is preferentially etched, the shape of the dielectric wall in the display area can be maintained.

Description

Plasma display panel {Plasma display panel}

1 is an exploded perspective view illustrating a part of a conventional plasma display panel;

2 is an exploded perspective view of a plasma display panel partially cut out according to an embodiment of the present invention;

3 is a cross-sectional view taken along the line I-I in a state in which the panel of FIG. 2 is coupled;

4 is a plan view showing a state in which the dielectric wall and the over-etching prevention wall of FIG. 2 are disposed;

5 is an exploded perspective view illustrating the discharge electrode of FIG. 2;

<Description of Symbols for Major Parts of Drawings>

200 ... Plasma Display Panel 201 ... Front Board

202 ... back substrate 203 ... first dielectric wall

204 Second dielectric wall 205 Dielectric wall

205c ... first overetch barrier 205d ... second overetch barrier

206 ... X electrode 207 ... Y electrode

208 protective layer 209 address electrode

210 dielectric layer 213 bulkhead

214 phosphor layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel provided with an over-etching prevention wall to prevent breakage of a dielectric wall filling a discharge electrode.

In general, a plasma display panel injects a discharge gas between two substrates on which a plurality of discharge electrodes are formed, and discharges the discharge, and excites the fluorescent material of the phosphor layer by the ultraviolet rays generated thereby to implement desired numbers, letters, or graphics. Refers to a flat display device.

Referring to FIG. 1, the conventional plasma display panel 100 includes a front panel 110 and a rear panel 160 disposed to face the front panel 110.

The front panel 110 includes a front substrate 111, an X and Y electrodes 112 and 113 disposed on an inner surface of the front substrate 111, and the X and Y electrodes 112 and 113. A buried front dielectric layer 114 and a protective film layer 115 formed on the surface of the front dielectric layer 114 are included. The X electrode 112 includes a first transparent electrode line 112a and a first bus electrode line 112b disposed at one edge of the first transparent electrode line 112a. The Y electrode 113 Includes a second transparent electrode line 113a and a second bus electrode line 113b disposed at one edge of the second transparent electrode line 113a.

The rear panel 160 is disposed on the rear substrate 161 and the inner surface of the rear substrate 161 and the address electrode 162 disposed in a direction crossing the X and Y electrodes 112 and 113. And a back dielectric layer 163 filling the address electrode 162.

Meanwhile, a partition wall 164 partitioning a discharge space is disposed between the front panel 110 and the rear panel 160, and a red, green, and blue phosphor layer 165 is applied to the inside of the partition wall 164. It is.

In order to drive the conventional plasma display panel 100 having the above-described structure, electric signals are applied to the Y electrode 113 and the address electrode 162, respectively, and discharge cells are selected at intersections. When surface discharge occurs from the surface of the front panel 110 by applying an electrical signal to the electrodes 112 and 113 alternately, ultraviolet rays are generated from the red, green, and blue phosphor layers 165 coated in the selected discharge cells. Visible light can be emitted to produce still images or moving images.

However, the conventional plasma display panel 100 has the following problems.

First, since not only the X and Y electrodes 112 and 113 but also the front dielectric layer 114 and the passivation layer 115 are sequentially formed on the inner surface of the front substrate 110, the visible light generated in the discharge cell is generated. The transmittance to the light beam is less than 60%. Therefore, it does not function properly as a high efficiency flat panel display.

Second, when the plasma display panel 100 is driven for a long time, the discharge is diffused toward the phosphor layer 165. The charged particles cause ion sputtering on the phosphor layer 165 by the electric field, causing permanent afterimages.

Third, the discharge spreads outward from the discharge gap between the X and Y electrodes 112 and 113. Since the discharge spreads along the plane of the front panel 110, the space utilization of the entire discharge cell is low.

Fourth, when a discharge gas containing a high concentration of Xe gas of 10% by volume or more is injected into the discharge cell, the generation of charged particles and excitation species is increased by ionization and excitation of atoms, thereby increasing luminance and discharge efficiency, but high concentration of Xe There is a disadvantage that the initial discharge firing voltage (initial discharge firing voltage) is increased for the reason of applying the gas.

Recently, in order to prevent such a phenomenon, instead of forming a discharge electrode and a dielectric layer filling the lower surface of the front substrate, the dielectric wall partitions the discharge cell, and the structure of the plasma display panel is embedded in the dielectric wall. I'm researching.

However, even in such a case, the dielectric walls defining the outermost discharge cells among the discharge cells displaying the pixels are exposed to the developer in a process of exposing and developing, which is a manufacturing process of the panel, and thus overetching occurs. Accordingly, there is a problem that a part of the dielectric wall disposed at the outermost part during the discharge is broken.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a plasma display panel provided with an over-etching prevention wall is provided to prevent over-etching of a portion where the dielectric wall embedding the discharge electrode is exposed to the developer in a relatively large amount. The purpose is to provide.

Another object of the present invention is to provide a plasma display panel having an improved structure in which a discharge electrode is disposed along a circumference of a discharge cell to increase transmittance of visible light.

In order to achieve the above object, the plasma display panel according to an aspect of the present invention,

A plurality of substrates having front and rear substrates disposed to face each other;

A dielectric wall disposed between the front and back surfaces and defining discharge cells together with the front and back substrates;

A plurality of discharge electrodes disposed separately along the circumference of the discharge cell and embedded in the dielectric wall;

An over-etching prevention wall formed at the outermost part of the dielectric wall and for preventing over-etching of the dielectric wall disposed in the discharge cell during development; And

And red, green, and blue phosphor layers coated in the discharge cells.

In addition, the substrate may be divided into a display area in which a predetermined voltage is applied to the discharge electrode to implement an image, and a non-display area formed at an edge of the display area and electrically connected to the discharge electrode and an external terminal.

The over-etching preventing wall is integrally extended from the dielectric wall and disposed in the non-display area.

In addition, the over-etching prevention wall is characterized in that it is substantially the same shape as the dielectric wall.

Furthermore, the dielectric wall includes a first partition wall spaced apart from one another along the direction of the substrate and a second partition wall spaced apart from the other side along the other direction of the substrate, wherein the second dielectric wall is adjacent to each other. And integrally extend in an opposite direction from the inside of the pair of first dielectric walls.

In addition, the phosphor layer is excluded from the over-etching barrier.

In addition, the thickness of the over-etching prevention wall is characterized in that formed relatively thicker than the thickness of the dielectric wall.

In addition, the over-etching prevention wall is characterized in that formed on the outer portion of the dielectric wall, the exposure time is relatively high to the developer is injected from the developer disposed in one direction of the substrate during the development process.

Hereinafter, a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a partial cutaway view of the plasma display panel 200 according to an exemplary embodiment of the present invention, and FIG. 3 is a cutaway view of the coupled state along the line II of FIG. 2.

2 and 3, the plasma display panel 200 includes a front substrate 201 and a rear substrate 202 disposed in parallel with the front substrate 201. Frit glass is applied to the edges of the inner surfaces of the front and rear substrates 201 and 202 facing each other, and the inner spaces are sealed from each other by sealing them together.

The front substrate 201 is made of a transparent substrate such as soda lime glass. The back substrate 202 is also made of substantially the same material as the front substrate 201.

A dielectric wall 205 is defined between the front and rear substrates 201 and 202 to define a discharge cell together with them. The dielectric wall 205 is formed by adding various fillers to glass paste.

The dielectric wall 205 includes a first dielectric wall 203 disposed in the X direction of the front and rear substrates 201 and 202, and a second dielectric wall 204 disposed in the Y direction. The second dielectric wall 204 extends integrally in an opposite direction from the inside of the pair of adjacent first dielectric walls 203. The combined first and second dielectric walls 203 and 204 are matrix-like, with the result that the discharge cells are square in shape.

Alternatively, the dielectric wall 205 may be embodied in various shapes such as meander type, delta type, or honeycomb type. In addition, the discharge cells defined by the dielectric wall 205 are not limited to any one of the discharge cell structures as long as the discharge cells defined by the dielectric walls 205 can define discharge cells such as hexagons, ellipses, and circles.

An X electrode 206 corresponding to the first discharge electrode and a Y electrode 207 corresponding to the second discharge electrode are embedded in the dielectric wall 205. The X and Y electrodes 206 and 207 are not disposed inside the discharge cell but are disposed along the circumference of the discharge cell. The X and Y electrodes 206 and 207 are electrically insulated from each other, and voltages of different intensities are applied.

Magnesium oxide (MgO) is formed on the inner surface of the dielectric wall 205 such that ions generated inside the front substrate 201 along the four sidewalls of the discharge cell can emit secondary electrons by interacting with the surface. A protective film layer 208 made of the same material is deposited.

A partition wall 213 may be further formed between the dielectric wall 205 and the back substrate 202. The partition wall 213 is made of a low dielectric material unlike the dielectric wall 205. The partition wall 213 is disposed in substantially the same shape at a portion corresponding to the dielectric wall 205.

The partition wall 213 includes a first partition wall 211 disposed in a direction parallel to the first dielectric wall 203, and a second partition wall 212 disposed in a direction parallel to the second dielectric wall 204. Doing. The first and second partitions 211 and 212 are integrally coupled to each other to form a matrix.

When only the dielectric wall 205 is formed between the front and back substrates 201 and 202, a single wall defines a discharge cell, and the dielectric wall 205 and the partition wall 213 are both front and back. When formed between the substrates 201 and 202, a two-layer wall made of a material having a different dielectric constant defines a discharge cell.

The address electrode 209 is disposed on the top surface of the rear substrate 202 in a direction crossing the X and Y electrodes 206 and 207. The address electrode 209 is located in the discharge cell. The address electrode 209 is buried by the dielectric layer 210.

The plasma display panel 200 may be designed in various structures depending on whether it is a surface discharge type, a counter discharge type, or a hybrid type. In this embodiment, the X and Y electrodes 206 and 207 may perform display sustain discharge. The address electrode 209 is an electrode which is disposed in a direction crossing the pair of discharge sustaining electrode pairs 206 and 207 to cause addressing discharge. In this case, the address electrode 209 may be embedded in the same dielectric wall 205 as the X and Y electrodes 206 and the Y electrode 207 as well as the back substrate 202.

Meanwhile, in the discharge cells defined by the front and rear substrates 201 and 202, the dielectric walls 205, and the partition walls 213, neon (Ne) -xenon (Xe) or helium (He) -xenon ( A discharge gas such as Xe) is injected.

In the discharge cell, red, green, and blue phosphor layers 214 are excited by ultraviolet rays generated from the discharge gas and emit visible light. In this case, the phosphor layer 214 may be coated on any region of the discharge cell, but in the present embodiment, the phosphor layer 214 is coated with a predetermined thickness on the inner wall of the partition 213 and the upper surface of the dielectric layer 210.

The red, green, and blue phosphor layers 214 are coated for each discharge cell. The red phosphor layer consists of (Y, Gd) BO ₃ ; Eu ⁺³ , the green phosphor layer consists of Zn ₂ SiO ₄ : Mn ²⁺ , and the blue phosphor layer is BaMgAl ₁₀ O ₁₇ : Eu ² It is preferable that it consists of ⁺ .

Here, over-etching prevention means is provided at the outermost side of the dielectric wall 205 to prevent the dielectric wall 205 defining the discharge cells from being damaged due to over-etching during development.

More detailed description is as follows.

4 illustrates a state in which the dielectric wall 205 and the over-etching prevention means are disposed on the front substrate 201 of FIG. 2, and FIG. 5 illustrates an enlarged view of the discharge electrodes 206 to 209 of FIG. 2. .

4 and 5, the front substrate 201 is applied by applying a predetermined discharge voltage to the X and Y electrodes 206 and 207 and the address electrode 209 disposed in a direction crossing the same. A display area 201a for implementing an image, and the edge of the display area 201 to the substrate 201, and are formed to have terminals of the X and Y electrodes 206 and 207 and the address electrode 209. Can be partitioned into a nondisplay area 201b (201c) that provides an area that is electrically connected to an external terminal, such as a tape carrier package such as a flexible printes cable. .

The X electrode 206 is disposed along the X direction of the substrate 201. The X electrode 206 is located along the circumference of the discharge cell partitioned by the dielectric wall 205 and is rectangular in shape by the matrix dielectric wall 205.

In addition, the X electrode 206 is continuously disposed along the circumference of the discharge cells formed adjacent to each other along the X direction of the substrate 201. Accordingly, the X electrode 206 has a ladder shape along the X direction of the substrate 201. A plurality of such ladder-shaped X electrodes 206 are disposed at predetermined intervals along the Y direction of the substrate 201.

The Y electrode 207 is disposed below the X electrode 206 and is disposed at the same position as the X electrode 206. Similarly to the X electrode 206, the Y electrode 207 is disposed along the circumference of the discharge cell, and has a ladder shape continuously disposed in the adjacent discharge cell along the X direction of the substrate 201. The X and Y electrodes 206 and 207 maintain substantially the same shape except that they are connected to external terminals in opposite directions of the substrate 201.

The dielectric wall 205 in which the X and Y electrodes 206 and 207 are embedded may include a first dielectric wall 203 disposed in the X direction of the substrate 201 and a first dielectric wall 203 disposed in the Y direction of the substrate 201. And a second dielectric wall 204, wherein the first and second dielectric walls 203 and 204 are bonded to each other to form a matrix. In the discharge cells partitioned by the dielectric wall 205, red, green, and blue phosphor layers 214 are coated for each discharge cell.

At this time, the over-etching means is provided on the outermost side of the dielectric wall 205.

That is, the left and right dielectric walls 205a disposed on the left and right edges of the display area 201a of the dielectric wall 205 and the first and second over-etching prevention walls extending integrally thereto. 205c) and 205d are provided. The first overetch prevention wall 205c is integrally connected from the left dielectric wall 205a, and the second overetch prevention wall 205d is integrally connected from the right dielectric wall 205b. The first and second overetch prevention walls 205c and 205d are disposed in the non-display areas 201b and 201c, respectively.

The portions in which the first and second over-etching barriers 205c and 205d are formed may be formed in a direction in which the developer is injected from a developer disposed in the developing process, which is one of the processes for manufacturing the dielectric wall 205. The non-display areas 201b and 201c are disposed adjacent to each other.

As indicated by the arrows in FIG. 4, if a developer is installed on the right side of the substrate 201 and developer is introduced therefrom, the right dielectric wall 205b disposed adjacent to the developer is more likely than other portions of the dielectric wall 205. There is a lot of time exposed to the developer.

Therefore, since there is a risk of overetching in the right dielectric wall 205b, the first overetch prevention wall 205d corresponding to the dummy dielectric wall is provided outside the right dielectric wall 205b in the non-display area 201c. do. Accordingly, while developing the dielectric wall 205 of the display region 201a, even if the edge of the dielectric wall 205 is exposed to a large amount of developer, the first overetch prevention wall 205d is overetched and the right dielectric wall is etched. There is no fear of damage to 205b.

In addition, the second over-etching prevention wall 205c corresponding to the dummy dielectric wall is integrally formed outside the left dielectric wall 205a, and the over-etching prevention means is provided at the edge of the entire dielectric wall 205 at the same time. In this structure, the over-etching preventing walls 205c and 205d come into contact with the portions exposed to the developer in a large amount. Therefore, the shape of the dielectric wall 205 disposed inwardly of the overetch prevention walls 205c and 205d can be formed without damage.

In this embodiment, a structure in which the first and second overetch prevention walls 205c and 205d are integrally connected to the outer side of the dielectric walls 205a and 205b on the left and right sides of the dielectric wall 205 is described. The over-etching prevention walls 205c and 205d are not limited to any one structure such that the overetch prevention walls 205c and 205d may be formed in a dam-like structure in the vertical, vertical, and horizontal directions of the dielectric wall 205.

Meanwhile, the first and second overetch prevention walls 205c and 205d have substantially the same shape as the dielectric wall 205, and are preferably manufactured at the same time as the dielectric wall 205 is formed. In this case, the thickness of the first and second over-etching prevention walls 205c and 205d may be formed relatively thicker than the thickness of the dielectric wall 205 in consideration of the fact that the first and second over-etching prevention walls 205c and 205d are largely lost depending on the degree of over-etching. I will say. The first and second overetch prevention walls 205c and 205d are disposed one by one outside the dielectric wall 205, but the present invention is not limited thereto.

In addition, since the first and second overetch prevention walls 205c and 205d serve as dummy dielectric walls, red, green, and blue phosphor layers applied in discharge cells partitioned by the dielectric walls 205 ( 214 need not be applied. And there is no reason for providing the address electrode 209 as well.

The operation of the plasma display panel 200 having the above structure will be described in detail with reference to FIGS. 2 to 5.

First, when a predetermined pulse voltage is applied between the Y electrode 207 and the address electrode 209 from an external power source, the discharge cell to emit light is selected. Wall charges accumulate inside the selected discharge cells.

Subsequently, if a voltage of “+” is applied to the X electrode 206 and a voltage higher than this is applied to the Y electrode 207, the wall is caused by the voltage difference applied between the X and Y electrodes 206 and 207. The charge will move.

Next, the plasma is generated while colliding with the discharge gas atoms in the discharge cell by the movement of the wall charges, and the discharge is extended from the X and Y electrodes 206 and 207 where a relatively strong electric field is formed to the entire discharge cell. do.

In this way, after the discharge is formed, if the voltage difference between the X and Y electrodes 206 and 207 becomes lower than the discharge voltage, the discharge no longer occurs, and space charge and wall charge are formed in the discharge cell. At this time, if the polarities of the voltages applied to the X and Y electrodes 206 and 207 are reversed, the discharge is generated again with the help of wall charges. If the polarities of the X and Y electrodes 206 and 207 are immediately changed, the first discharge process is repeated. The discharge is stably generated while repeating this process.

At this time, the ultraviolet rays generated by the discharge excite the fluorescent material of the phosphor layer 214 applied to each discharge cell. Through this process, visible light is obtained. The generated visible light is emitted to the discharge cells to implement a still image or a moving picture.

As described above, in the plasma display panel of the present invention, an over-etching prevention wall extending from the dielectric wall is installed in the non-display area, so that over-etching of the dielectric wall surrounding the dielectric wall occurs even when an over-etching phenomenon occurs by the developer during the process of manufacturing the dielectric wall. Since each barrier is preferentially etched, the shape of the dielectric wall of the display area can be maintained.

In addition, since the over-etching prevention wall serving as the dummy dielectric wall is provided, a phenomenon in which a part of the dielectric wall disposed at the outer side when the dielectric wall is formed in the display area is not properly formed occurs in the over-etching-preventing wall. This widens.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (10)

A plurality of substrates having front and rear substrates disposed to face each other; A dielectric wall disposed between the front and back surfaces and defining discharge cells together with the front and back substrates; A plurality of discharge electrodes disposed separately along the circumference of the discharge cell and embedded in the dielectric wall; An over-etching prevention wall formed at the outermost part of the dielectric wall and for preventing over-etching of the dielectric wall disposed in the discharge cell during development; And And a red, green, and blue phosphor layer coated in the discharge cell. The method of claim 1, The plurality of substrates are divided into a display area for implementing an image by applying a predetermined voltage to the discharge electrode, a non-display area formed at an edge of the display area, and electrically connected to the discharge electrode and an external terminal. And the over-etching prevention wall integrally extends from the dielectric wall and disposed in the non-display area. The method of claim 2, And the overetch prevention wall has the same shape as the dielectric wall. The method of claim 2, The dielectric wall includes a first partition wall spaced apart from each other along a direction of the substrate and a second partition wall spaced apart from each other along the other direction of the substrate, and the second dielectric wall is an adjacent pair. And integrally extending in an opposite direction from the inner side of the first dielectric wall of the plasma display panel. The method of claim 2, And a phosphor layer is excluded from the over-etching wall. The method of claim 2, And the thickness of the over-etching prevention wall is thicker than that of the dielectric wall. The method of claim 2, And the over-etching prevention wall is formed on an outer portion of the dielectric wall having a large exposure time to a developer sprayed from a developer disposed in one direction of the substrate during the developing process. The method of claim 1, And wherein the discharge electrodes have first and second discharge electrodes disposed along one direction of the substrate, and the first and second discharge electrodes are continuously connected along a circumference of an adjacent discharge cell. The method of claim 1, And a partition wall between the dielectric wall and the rear substrate to define a discharge cell together with the dielectric wall, wherein the phosphor layer is coated inside the partition wall. The method of claim 1, It is disposed on the rear substrate in a direction intersecting with the first and second discharge electrodes for causing display sustain discharge, and an address electrode for causing addressing discharge and the second discharge electrode is further provided, and the address electrode is buried by a dielectric layer. Characterized in that the plasma display panel.

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