KR100646978B1 - A bit-line precharge voltage control circuit of semiconductor memory device - Google Patents

Abstract

A bit line precharge voltage control circuit of a semiconductor memory device is provided to improve electrical characteristics of a semiconductor device by applying a bit line precharge voltage to be applied to a mat arranged with a cell array having a defective cell through a transistor of high resistance, and by applying a bit line precharge voltage applied to a mat without a defective cell through a transistor of small resistance. A bank part(500) comprises a number of memory banks including a number of mats each having a bleeder circuit. A row address control part(200) generates a control signal in response to an external address signal. A fuse/test mode signal generation part(300) generates a selection signal for selecting one of memory banks and one of the mats of the bank part according to a fuse/test mode signal. A bleeder circuit control part(400) generates an enable signal of the bleeder circuit, which applies a bit line precharge voltage to be applied to the bank part, in response to the control signal and the selection signal.

Description

A bit-line precharge voltage control circuit of semiconductor memory device

1 is a circuit diagram illustrating a cell region and a bit line sense amplifier of a general memory device.

2 is a block diagram of a device for explaining a bit line precharge voltage control circuit of a semiconductor memory device according to the present invention.

FIG. 3 is a detailed circuit diagram of the fuse / test mode signal generator of FIG. 2.

4 is a detailed circuit diagram of the bleeder circuit controller of FIG. 2.

5 is a circuit diagram illustrating a bleeder circuit among the bit line precharge voltage control circuits according to the present invention.

Description of the main parts of the drawing

10: memory cell area 20: bit line sensing amplifier circuit

100: address signal unit 200: row address control unit

300: fuse / test mode signal generator

400: bleeder circuit control unit 500: bank unit

The present invention relates to a bit line precharge voltage control circuit of a semiconductor memory device, and more particularly, to a bit line precharge voltage control circuit of a semiconductor memory device having improved current reduction and operation speed of a semiconductor memory device.

BACKGROUND OF THE INVENTION [0002] The development of semiconductor memory devices has become the development direction of high capacity and high speed of operation. And in addition to these requirements, it is well known that low-voltage memories are also another development direction for studying reliable operation in low-power voltage environments. In particular, the development trend of the memory to be mounted in a portable system, for example, a portable system such as a mobile phone or notebook computer for the mobile device to consume only a minimum of power.

One such effort is to minimize current consumption in the core area of memory. In the core region consisting of memory cells, bit lines, and word lines, they are designed according to extremely refined design rules. Thus, memory cells are very small in size and use low power.

In particular, bitline precharge is one of the important techniques related to its speed in cell data access. It is well known that bit line precharge is a technique for precharging a bit line to a predetermined voltage level in advance of data access to speed up access of data '1' or '0'.

FIG. 1 is a circuit diagram illustrating a cell region 10 and a bit line sense amplifier 20 of a general memory device.

Referring to FIG. 1, the sense amplification circuit includes bit line equalizer transistors A and D formed between bit lines BL and BL b and bit line isolation transistors B and C for selectively connecting each bit line BL and BL b. Further, a sense amplifier SA operated by the sense amplification control signals RTO and SB is formed between the bit lines BL and BLb. The sense amplification circuit shares two cell blocks in a shared structure. The bit line isolation transistors B and C selectively connect and disconnect the entire bit line according to the BIS signal in consideration of the capacitance load of the bit line.

The bit line equalizer transistors A and D are operated to bring the bit lines BL and BLb to the bit line precharge voltage VBLP level under the precharge command. That is, when the bit line equalizer transistors A and D are turned on in synchronization with the precharge command, the bit lines BL and BLb having the power supply voltage (Vcc) level and the ground voltage (Vss) level are connected to become Vcc / 2 in a short time. The level of the bit lines BL and BLb is adjusted by the supplied bit line precharge VBLP.

However, a defect may occur between the word line and the bit line during the fabrication process of the semiconductor memory device, thereby forming a current path from the VBLP voltage source to the word line. This breaks down the current target irrespective of the repair of the defective cell and divides it into a fail die, resulting in a decrease in yield. A solution to this problem is a bleeder circuit, which is a method of inducing a current reduction through an increase in resistance by connecting a bit line precharge (VBLP) through a transistor instead of directly connecting a sense amplifier circuit. to be. However, this method has a disadvantage in that it is applied to both the defective cell and the normal cell to degrade the operation speed characteristic of the device.

Accordingly, the present invention applies a bit line precharge voltage applied to a mat in which a cell array in which defective cells are present is arranged in a mattress state for a current reduction effect, and improves the operation speed characteristics of the device. In order to provide a bit line precharge voltage control circuit of a semiconductor memory device, a bit line pre-autonomous voltage applied to a mat without a defective cell is applied through a transistor having a low resistance to improve electrical characteristics of the semiconductor device.

A bit line precharge voltage control circuit of a semiconductor memory device according to the present invention includes a bank portion including a plurality of memory banks including a plurality of mats having a bleeder circuit, and a row address generating a control signal in response to an external address signal. A control unit, a fuse / test mode signal generator for generating a selection signal for selecting one memory bank among the plurality of memory banks and one mat among the plurality of mats according to a fuse / test mode signal, and the And a bleeder circuit controller configured to generate an enable signal of a bleeder circuit applying a bit line precharge voltage applied to the bank unit in response to a control signal and the selection signal.

The bleeder circuit may include a first transistor configured to apply the bit line precharge voltage to the bit line in the mat in response to the bleeder circuit enable signal, and an inverter inverting and outputting the bleeder circuit enable signal; And a second transistor configured to apply the bit line precharge voltage to the bit line in the mat in response to the inverted bleeder circuit enable signal, wherein the first transistor is much larger in size than the second transistor. Big, very low resistance

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 is a block diagram of a device for explaining a bit line precharge voltage control circuit of a semiconductor memory device according to the present invention.

Referring to FIG. 2, a bit line precharge voltage control circuit of a semiconductor memory device according to the present invention includes an address signal generator 100 for generating an address signal, and a row address controller for generating a row address signal in response to the address signal. 200, a fuse / test mode signal generator 300 that generates a fuse signal or a test mode signal, and a bleeder enable signal bleed_on in response to the row address signal, the memory bank, and the mat selection signal. The reader circuit controller 400 includes a bank unit 500 including a plurality of memory banks.

The address signal unit 100 outputs a signal for designating a storage location as an address signal when transmitting cell data from the outside.

The row address control unit 200 converts the address signal generated by the address signal unit 100 into a control signal for application according to an internal operation situation and outputs the converted control signal.

The fuse / test mode signal generator 300 may determine a specific mat (eg, a first memory bank Bank0) of a specific memory bank among a plurality of mats mat0 to mat3 constituting the memory bank of the bank unit 500. Outputs a signal that enables mat0). For example, if a fuse set consists of three fuses, the circuit can be configured so that mat3 is selected when all three fuses are cut. In the test mode as well, the combination with an external address allows a specific memory bank and a specific mat (eg mat0) to be selected.

Table 1 below shows the memory bank and the mat selected according to the cut state of the fuse of the fuse / test mode signal generator 300 according to the present invention (in Table 1 '1' represents the cut state of the fuse).

fuse2 fuse1 fuse0 Mat chosen 0 0 0 First bank, mat0 0 0 One 1st bank, mat1 0 One 0 First bank, mat2 0 One One First bank, mat3 One 0 0 Second bank, mat0 One 0 One 2nd Bank, mat1 One One 0 Second bank, mat2 One One One 2nd bank, mat3

 The bleeder circuit controller 400 generates a bleeder enable signal bleed_on by combining the control signal of the row address controller 200 and the memory bank and the mat selection signal in the fuse / test mode signal generator 300.

The bank unit 500 is composed of a plurality of memory banks Bank0, Bank1 (only two memory banks are shown for convenience of description) including a plurality of mats mat0 to 3.

3 is a detailed circuit diagram of the fuse / test mode signal generator 300 of FIG. 2.

Referring to FIG. 3, the fuse / test mode signal generator 300 inverts an output signal according to a fuse (fuse <0>) connecting the external power source Vext and a cut state of the fuse and outputs the inverter IV1. And output signals of the NOR gate NR1 and the NOR gate NR1 which logically combine the output of the inverter IV1 and the test mode signal (test mode) to generate a fuse / test enable signal Fuse_tm_en <0>. It comprises a plurality (n) of the signal generation section including the inverter IV2.

4 is a detailed circuit diagram of the bleeder circuit controller 400 of FIG. 2.

Referring to FIG. 4, an address signal (for example, adress <0>) output from a row address controller and a fuse / test enable signal (for example, Fuse_tm_en <0>) generated from a fuse / test mode signal generation unit may be used. And a plurality of signal generators (n) including an inverter IV11 for inverting the output signals of the NOR gate NR11 and the NOR gate NR11 to be logically combined to output the bleeder enable signal bleed_on <0>. .

5 is a block for applying a bit line precharge voltage Vblp to a bit line sense amplifying circuit in a mat in response to a bleeder enable signal bleed_on output from the bleeder circuit controller 400 of FIG. 2. It is a circuit diagram for demonstrating a reader circuit.

Referring to FIG. 5, the bleeder circuit according to the present invention includes a plurality of NMOS transistors N1 and N2 and an inverter IV1.

The first NMOS transistor N1 has a drain connected to a bit line precharge voltage Vblp output line having a drain connected to a bit line sense amplifier circuit, and a source terminal connected to a bit line precharge voltage generator. In addition, a bleeder enable signal bleed_on is applied to the gate. The second NMOS transistor N2 has a drain connected to the bit line precharge voltage Vblp output line and a source terminal connected to the bit line precharge voltage generator. In addition, the bleeder enable signal bleed_on inverted by the inverter IV1 is applied to the gate. The transistor sizes of the first NMOS transistor N1 and the second NMOS transistor N2 are such that the first NMOS transistor N1 is much larger than the second NMOS transistor N2. This means that the transistor can be regarded as a resistor, and if the size is large, a low resistance value can be secured. Therefore, when a current path is formed through the transistor having a large resistance value, the current flowing through the transistor can be reduced.

An operation of the bit line precharge voltage control circuit of the semiconductor memory device will be described with reference to FIGS. 2 and 5 as follows.

First, the address signal unit 100 outputs a signal for designating a storage location when transmitting cell data from the outside as an address signal. The address signal generated by the address signal unit 100 is converted into a control signal for application according to an internal operation situation by the row address control unit 200 and output.

Also, the fuse / test mode signal generator 300 may include a specific mat (eg, mat0 of a first bank) of a specific memory bank among a plurality of mats mat0 to mat3 constituting the memory bank of the bank unit 500. Signals Fuse_tm_en <0> to Fuse_tm_en <n> capable of enabling are output.

The bleeder circuit controller 400 controls the control signals adress <0> to adress <n> output from the row address controller 200 and the memory bank / mat selection signal output from the fuse / test mode signal generator 300. In response to (Fuse_tm_en <0> to Fuse_tm_en <n>), a bleeder enable signal (bleed_on) for enabling the bleeder circuit is output.

The bleeder enable signal bleed_on is output to the selected mat of the selected memory bank and applied to the bleeder circuit of FIG. 3.

The bleeder enable signal bleed_on is output at a low level to a mat having a defective cell between the word line and the bit line. In response to the low-level bleeder enable signal bleed_on, the first NMOS transistor N1 is turned off and the second NMOS transistor receives the bleeder enable signal bleed_on inverted by the inverter IV1. N2) is turned on. Accordingly, the bit line precharge voltage Vblp output from the bit line precharge voltage generator is applied to the bit line precharge voltage Vblp output line through the second NMOS transistor N2. In this case, as shown in FIG. 1, when a coupling occurs in the memory cell region, a current path is formed between the bit line BL and the word line WL. At this time, since the bit line precharge voltage Vblp is applied to the bit line sense amplifier through the second NMOS transistor N2 having a large resistance value, the current flowing through the second NMOS transistor N2 can be reduced.

In the case of selecting a mat without a defective cell, the bleeder enable signal bleed_on is output at a high level. The second NMOS transistor N2 is turned on in response to the high-level bleeder enable signal bleed_on and receives the bleeder enable signal bleed_on inverted by the inverter IV1. ) Is turned off. Accordingly, the bit line precharge voltage Vblp output from the bit line precharge voltage generator is applied to the bit line precharge voltage Vblp output line through the first NMOS transistor N1. In this case, since the resistance value of the first NMOS transistor N1 is extremely smaller than that of the second NMOS transistor N2, the first NMOS transistor N1 has a fast operation characteristic in applying the bit line precharge voltage Vblp to the bit line. Thus, the operating speed of the device is improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

In the bit line precharge voltage control circuit of a semiconductor memory device according to the present invention, a bit line precharge voltage applied to a mat having a defective cell is applied through a transistor of a small size having a large resistance, and a mat having no defective cell is present. The bit line pre-autonomous voltage applied to is applied through a large transistor having a small resistance, thereby improving the current reduction effect and the operation speed of the semiconductor device.

Claims (6)

A bank portion including a plurality of memory banks including a plurality of mats having a bleeder circuit; A row address controller generating a control signal in response to an external address signal; A fuse / test mode signal generator configured to generate a selection signal for selecting one memory bank among the plurality of memory banks and one mat among the plurality of mats according to a fuse / test mode signal; And And a bleeder circuit controller configured to generate an enable signal of the bleeder circuit to apply a bit line precharge voltage applied to the bank unit in response to the control signal and the selection signal. Voltage control circuit. Following claim 1 The bleeder circuit applies the bit line precharge voltage to a bit line in a mat by using a transistor having a large resistance in the case of a mat having a defective cell among the plurality of mats, The bit line precharge voltage control circuit of a semiconductor memory device which applies the bit line precharge voltage to the bit line in the mat by using a transistor having a low resistance in the case of a mat having no defective cells. The method of claim 1, The fuse / test mode signal generator is a bit line precharge voltage control circuit of a semiconductor memory device that generates a selection signal of a mat having a bad cell and a mat having a bad cell among a plurality of mats of the bank part according to a cut state of a fuse. . The method of claim 1, The bleeder circuit may include a first transistor configured to apply the bit line precharge voltage to the bit line in the mat in response to the bleeder circuit enable signal; An inverter for inverting and outputting the bleeder circuit enable signal; And A second transistor applying the bit line precharge voltage to the bit line in the mat in response to the inverted bleeder circuit enable signal; The first transistor is a bit line precharge voltage control circuit of a semiconductor memory device having a very large size and extremely small resistance compared to the second transistor. The method of claim 1, wherein the fuse / test mode signal generator And a plurality of signal generators generating the selection signal in response to a cut state of the fuse and a test mode signal. The method of claim 1, wherein the bleeder circuit control unit And a plurality of signal generators generating the enable signal of the bleeder circuit in response to the control signal and the selection signal.

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