KR100641090B1 - MIPS BACKPLNAE USING 10/100/1000Mbps ETHERNET SWITCH - Google Patents

Abstract

The present invention relates to a MIPS backplane using a 10/100/1000 Mbps Ethernet switch, wherein the switch Ethernet backplane is disposed on a main switchboard of a main rack, in which a plurality of boards are coupled to a plurality of slots, so that the main switchboard of the main rack and the 100Mbps or 1Gbps between the sub-switch boards of the plurality of auxiliary racks connected to the main rack is configured to allocate a radio bandwidth of 10Mbps or 100Mbps to each board between the sub-switch board of the auxiliary rack and the peripheral board of the auxiliary rack.

The present invention can expand the number of slots as desired while efficiently allocating radio bandwidth so that 100Mbps or 1Gbps can be used between MSB and SSB, and 10Mbps or 100Mbps can be used between SSB and peripheral boards. By using Switch Ethernet as a backplane, unnecessary packet conversions can be eliminated in the middle, a full deplexed backplane can be provided, and a QoS guaranteed backplane can be obtained by adopting 802.1p / Q.

Description

MIPS backplane using 10/100 / 1000Mbps Ethernet switch {MIPS BACKPLNAE USING 10/100 / 1000Mbps ETHERNET SWITCH}

1 is a perspective view showing the structure of a conventional small PCI rack.

2 is a view for explaining a problem caused by the format conversion of the conventional small PCI.

3 to 12 is a diagram of a MIPS backplane using the present invention 10/100 / 1000Mbps Ethernet switch,

Figure 3 is an exploded perspective view showing the configuration of the rack.

4 is a block diagram of a backplane.

5 is a backplane block diagram.

6 and 7 are exemplary views showing different applications of the port selector.

8 is a connector cable structure diagram.

9 and 10 are exemplary views showing a case where different switches are applied to the main rack.

11 and 12 are exemplary views illustrating a case where different switches are applied to a sub switch board.

<Description of reference numerals for main parts of the drawings>

100: main rack 110: secondary rack

200: main switchboard 201: 100Mbps switch chip

202: 1Gbps switch chip 210: sub switch board

211, 212: switch chip 220: peripheral board

230: power board 300: 32-pin connector cable

301: main switch line 302: port selector

303: port

The present invention relates to a switch Ethernet backplane suitable for MIPS (Multimedia Internet Protocol System), and in particular, by using the switch Ethernet as a backplane, the number of slots can be efficiently allocated to each board of the main rack and the auxiliary rack. Is a MIPS backplane using a 10/100 / 1000Mbps Ethernet switch that can be arbitrarily scaled, eliminates unnecessary packet conversions, and provides a full deplexed backplane.

In general, current system backplanes are mostly developed on the extension of TDM base backplane (proportary backplane), main CPU bus, etc.

TDM base backplanes are not easy to expand in bandwidth, and dedicated backplanes do not require standard chipsets or protocols, which are time consuming to develop, and backplanes developed on the extension of the main CPU bus are difficult to develop. It is easy, but it has a number of slots, board size, and a backplane length limit based on the main clock length limit for synchronization.

Among these, the backplane that meets the required radio bandwidth (displacement 2.2Gbps) of MIPS is a small programmatic communication interface (PCI).

Looking at one problem with the prior art, the current small PCI is based on PCI Rev2.1, and according to this specification, the current small PCI has a bandwidth of 1.56 Gbps with a bus speed of 33 MHz and a 32-bit Data Bus. Has In addition, it is expandable to a 64-bit data bus, and has a radio bandwidth of 2.112 Gbps. However, having a 64-bit data bus requires that most of the CPUs and memory connected to it must be upgraded to 64-bit, making most CPU chips and boards available in 32-bit. And yet, there is no defined 66MHz miniature PCI expandable to 4.224Gbps.

These small PCI backplanes are limited to eight slots per rack (including one system slot) as shown in Figure 1 due to electrical characteristics (pan-out) to meet minimum requirements. Motorola's products are also expandable to only 16 slots and require another system board to expand the slot. In addition, the board size is also limited to a maximum of 6U (233.35mm x 160mm), which limits the available ports (typically four ports are used per peripheral board).

In FIG. 1, reference numeral 1 denotes a rack, 10 denotes a system board, and 11 denotes a peripheral board, in which one system board 10 and seven peripheral boards 11 are combined in one rack 1. Is showing.

This limitation of small PCI is appropriate when the main CPU handles the main task, such as a PC, and does not require many peripheral boards, but in communication systems such as MIPS (Multimedia Internet Protocol System), peripheral boards are the main task. It is not suitable because it handles and needs a large number.

FIG. 2 is a diagram illustrating a problem caused by a format conversion of a conventional small PCI. Referring to FIG. 2, another problem of the conventional technology is described. As shown in FIG. 2, a format in which the small PCI is externally connected is Ethernet format to TDM. It is a format that has a PCI backplane, so the process of converting the data into a PCI format that has nothing to do with the actual external connection format, that is, converting the TDM format to the PCI format when transferring data from the peripheral board 21 to the peripheral board 22. After that, the process to be converted to the Ethernet format and transmitted to the peripheral board 22 should be added, thus adding unnecessary latency to the package.

Looking at other problems in the prior art, it is important that in multimedia data transmission environments such as MIPS, transmission priority can be applied to things like full duplex and voice packets, but small PCI backplanes are bus arbiters. Arbitrators are asked by each chip to give them a fair chance per chip or to give priority to a particular chip. For example, in a PC-like environment, video adapters are given priority over bus usage over SCSI host bus adapters that require relatively low throughput and slow bus access. This is not suitable for environments such as MIPS where priority per package is more important.

The problems of the prior art are summarized as follows.

First, in the case of a small PCI, there is a problem in that a latency that needs to be converted into a PCI format is added.

Second, in terms of scalability and efficient bandwidth distribution, MIPS must be able to scale from a small number of ports to a large number of slots to meet the needs of small offices and large offices. There must be multiple racks to cover a large office, but there is no backplane that can freely expand the number of slots (expand the number of ports) while properly distributing the desired radio bandwidth.

Third, in MIPS, the priority between chips is significant because all the chips are in the same position where the physical media must carry different voices and related control signals and status information together. In MIPS, what you need is an environment that gives priority to the voice package, but it is not appropriate.

Accordingly, the present invention was devised to solve the above-mentioned defects and problems, and it is easy to expand the size of a printed circuit board and a slot while efficiently allocating a bandwidth to a board. Unlike the existing backplanes that form the backplane of the MIPS (Multimedia Internet Protocol) and cannot give priority per packet, the multimedia environment needs (QoS, Full) It is an object of the present invention to provide a MIPS backplane using a 10/100 / 1000Mbps Ethernet switch that can implement a backplane capable of satisfying a duplex.

MIPS backplane using a 10/100 / 1000Mbps Ethernet switch according to the present invention in order to achieve the object as described above by arranging the switch Ethernet backplane on the main switchboard of the main rack to which a plurality of boards are coupled to a plurality of slots Each board has a bandwidth of 100 Mbps or 1 Gbps between the main switch board of the rack and the sub switch boards of the plurality of sub racks connected to the main rack, and a bandwidth of 10 Mbps or 100 Mbps between the sub switch board of the sub rack and the peripheral board of the sub rack. Is assigned to.

In addition, a 1Gbps Ethernet switch or 100Mbps Ethernet switch is arranged on the main switchboard, the main switchboard and the sub-switchboard are connected at 100Mbps or 1Gbps, and the subswitchboard and the peripheral board are configured at 10Mbps or 100Mbps. do.

In addition, a 1-port 100 Mbps, 8-port 10 Mbps switch chipset or 1 Gbps, 8-port 100 Mbps switch chipset is placed on the sub-switch board of the sub-rack, and 1 Gbps switch chip connected from the main switch board through the backplane in the sub-rack. It is configured by receiving 100Mbps or 10Mbps through the uplink.

Then, the switch Ethernet is configured to employ a full deplex of the switch Ethernet to which the 802.1p / Q chipset is applied.

The present invention can eliminate the conversion (conversion) process by employing a switch ethernet backplane (switch ethernet backplane).

In addition, the same backplane can have a structure that can be expanded to multiple racks while efficiently controlling the radio bandwidth of the MSB (main switch board) chip set to 100Mbps or 1Gbps.

In addition, a full duplex of switched ethernet can be applied while having a structure that can give priority per package by adopting the 802.1p / Q chipset.

Hereinafter, with reference to the accompanying drawings, the present invention as described above in more detail as follows.

3 shows a rack configuration, which is composed of a main rack 100 and a plurality of auxiliary racks 110. For example, the main rack 100 includes a main switch board 200 and a peripheral board 220. ), And the power supply board 230, the auxiliary rack 110 is composed of a sub-switch board 210 and a plurality of peripheral boards 220.

The main switchboard 200 is applied to the case of using a 1Gbps Ethernet switch and the case of using a 100Mbps Ethernet switch.

When the sub-switch board 210 uses a 1 Gbps Ethernet switch in the main switch board 200, the connection with the main switch board 200 is 100 Mbps, the connection of the peripheral board 220 is 10 Mbps, and the main switch When a 100 Mbps Ethernet switch is used for the board 200, the connection with the main switch board 200 is 1 Gbps, and the connection with the peripheral board 220 is 100 Mbps.

The configuration of such a rack is one example, and the number of slots of the rack may be selected from 5 to 10 slots or other numbers as necessary.

4 shows the configuration of the backplane, as shown in the main rack 100 and the auxiliary rack 110 or the auxiliary rack 110 is connected to the 32-pin connector cable 300. In addition, the main switch board 200 and the sub switch board 210 are connected to the 48-pin connector cable and the backplane, the sub switch board 210 and the peripheral board 220 is connected to the backplane.

FIG. 5 is a block diagram illustrating a backplane, and FIGS. 6 and 7 show different application examples of port selectors. As shown in FIG. 5, the connection between the sub switch board 210 and the peripheral board 220 is a unique circuit. The main switch lines 301 connected through a path and transferred through the 32-pin connector cable 300 as shown in FIGS. 6 and 7 are selected as the desired port 303 by the port selector 302. In this case, any port that is not used in another rack may be used. In FIG. 5, reference numeral 310 denotes a sub-switchboard connector, and 320 denotes a board connector.

As shown in FIG. 6 and FIG. 7, the two cases are divided because the same backplane is selected, but as shown in FIG. 6, 100 Mbps uses only 4 lines per port, and as shown in FIG. 7, 1 Gbps uses 8 lines.

8 shows a 32-pin connector cable. Referring to the 32-pin connector cable 300, each pair of lines is twisted to remove noise signals from the comparator of the receiver and to prevent interference from other pairs of electromagnetic waves.

FIG. 9 illustrates an 8-port 100 Mbps switch and FIG. 10 shows a 4-port 1 Gbps switch, in which pins connected to the 32-pin connector cable 300 are connected through the backplane of the main rack 100. As shown in FIG. 10, when the 8-port 100Mbps switch chip 201 is applied to the main switch board 200, only 4 lines are connected to the connector as shown in FIG. 10, and the 4-port 1Gbps switch chip 202 is applied as shown in FIG. 10. In this case, connect all 8 lines to the connector as "A".

11 and 12 are diagrams illustrating a case where different switches are applied to a sub switch board, and FIG. 11 is a 1 port 100 Mbps, 8 port 10 Mbps switch chip set 211 to the sub switch board 210, and FIG. 12 is a 1 port. 1 Gbps, 8 port 100 Mbps switch chip set 212 is applied, 1 Gbps or 100 Mbps connected from the main switchboard 200 via the backplane in the secondary rack 110 switch chip 211, (212) It shows the part connected to 100Mbps or 10Mbps by receiving through uplink of.

Full deplexing is naturally solved by adopting switch Ethernet as the backplane, and the QoS part can use a switch chip set that supports 802.1p / Q.

The rack shown in the above description is just one example, and more slots may be added and slots may be further reduced. In this case, a switch chip set suitable for the number of slots may be selected and used.

As described above, the present invention can expand the number of slots as desired while efficiently allocating radio bandwidth so that 100Mbps or 1Gbps can be used between MSB and SSB, and 10Mbps or 100Mbps can be used between SSB and peripheral boards.

By using Switch Ethernet as a backplane, unnecessary packet conversions can be eliminated in the middle, a full deplexed backplane can be provided, and a QoS guaranteed backplane can be obtained by adopting 802.1p / Q.

In the above has been shown and described a preferred embodiment of the present invention, any one of ordinary skill in the art without departing from the gist of the present invention claimed in the claims can be variously modified Therefore, the protection scope of the present invention is not limited by the above embodiment.

Claims (7)

100 Mbps or 1 Gbps between the main switch board of the main rack and the sub switch boards of the plural auxiliary racks connected to the main rack by arranging a switch Ethernet backplane on the main switch board of the main rack where the plural boards are coupled to the plural slots. MIPS backplane using a 10/100 / 1000Mbps Ethernet switch, characterized in that configured to allocate a radio bandwidth of 10Mbps or 100Mbps to each board between the sub-switch board of the auxiliary rack and the peripheral board of the auxiliary rack. The apparatus of claim 1, wherein a 1 Gbps Ethernet switch or a 100 Mbps Ethernet switch is disposed on the main switch board, the main switch board and the sub switch board are connected at 100 Mbps or 1 Gbps, and the sub switch board and the peripheral board are 10 Mbps or 100 Mbps. MIPS backplane using a 10/100 / 1000Mbps Ethernet switch, characterized in that configured to connect to. 2. The apparatus of claim 1, wherein a 1-port 100 Mbps, 8-port 10 Mbps switch chipset or 1 Gbps, 8-port 100 Mbps switch chipset is placed on the sub-switchboard of the sub-rack, and connected from the main switchboard through a backplane in the sub-rack. MIPS backplane using a 10/100 / 1000Mbps Ethernet switch, characterized in that 1Gbps received via the uplink of the switch chip and connected to 100Mbps or 10Mbps. According to claim 1, wherein the main rack, the auxiliary rack, and the auxiliary rack is connected to the connector cable, the main switchboard and the sub switchboard is connected to the connector cable and the backplane, the sub switchboard and the peripheral board is configured to be connected to the backplane MIPS backplane using a 10/100 / 1000Mbps Ethernet switch. According to claim 1, wherein the sub-switch board and the peripheral board of the plurality of auxiliary racks are connected by a unique line, the main switch lines transferred through the connector cable from the main switch board of the main rack is configured by selecting the desired port by the port selector MIPS backplane using a 10/100 / 1000Mbps Ethernet switch. The MIPS according to claim 1, wherein the rack has 5 to 10 slots, and the main rack, the sub rack, and each sub rack are connected to each other by a 32-pin connector cable. Backplane. The MIPS backplane of claim 1, wherein each pair of the 32-pin connector cable is twisted.

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