KR100640967B1 - Method for Surface Treatment in Cu Wafer - Google Patents

Method for Surface Treatment in Cu Wafer Download PDF

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KR100640967B1
KR100640967B1 KR1020040117593A KR20040117593A KR100640967B1 KR 100640967 B1 KR100640967 B1 KR 100640967B1 KR 1020040117593 A KR1020040117593 A KR 1020040117593A KR 20040117593 A KR20040117593 A KR 20040117593A KR 100640967 B1 KR100640967 B1 KR 100640967B1
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wafer
surface treatment
present
treatment method
copper
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KR20060079412A (en
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홍지호
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

본 발명은 표면 산화된 웨이퍼를 전해액을 이용하여 회복(recovery)하는 웨이퍼 표면 처리 방법에 관한 것으로, 표면 산화된 웨이퍼를 산성 전해액이 담긴 식각액에 넣어 상기 웨이퍼의 표면 산화막을 제거하는 것을 특징으로 한다. 여기서, 산성 전해액에 웨이퍼를 넣을 때, 상기 산성 전해액에 전류를 흘러주어 표면 산화막의 제거를 높인다.The present invention relates to a wafer surface treatment method for recovering a surface oxidized wafer using an electrolyte solution, wherein the surface oxidized wafer is removed by inserting the surface oxidized wafer into an etchant containing an acidic electrolyte solution. Here, when the wafer is placed in the acidic electrolyte, a current is flowed into the acidic electrolyte to increase the removal of the surface oxide film.

표면 처리, 표면 산화, ECP(Electro Chemical Plating) 담금(immersion)Surface Treatment, Surface Oxidation, Electro Chemical Plating (ECP) Immersion

Description

웨이퍼의 표면 처리 방법{Method for Surface Treatment in Cu Wafer}Method for Surface Treatment in Cu Wafer

도 1a 내지 도 1c는 본 발명의 웨이퍼의 표면 처리 방법을 나타낸 공정 순서도1A to 1C are process flowcharts showing a surface treatment method of a wafer of the present invention.

도 2는 본 발명의 웨이퍼의 표면 처리 방법을 적용 전 사진Figure 2 is a photograph before applying the surface treatment method of the wafer of the present invention

도 3은 본 발명의 웨이퍼의 표면 처리 방법을 적용 후 사진Figure 3 is a photograph after applying the surface treatment method of the wafer of the present invention

도 4는 본 발명의 웨이퍼 표면 처리 방법에 적용되는 전해액 내에서의 습식각률 데이터에 관한 표4 is a table relating to the wet etch rate data in the electrolyte applied to the wafer surface treatment method of the present invention.

*도면의 주요 부분에 대한 부호 설명* Explanation of symbols on the main parts of the drawings

10 : 표면 산화된 웨이퍼 10a : 표면 처리된 웨이퍼10: surface oxidized wafer 10a: surface treated wafer

20 : 식각조20: etching bath

본 발명은 반도체 소자에 관한 것으로 특히, 표면 산화된 웨이퍼를 전해액을 이용하여 회복(recovery)하는 웨이퍼 표면 처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a wafer surface treatment method for recovering a surface oxidized wafer using an electrolyte solution.

전기 화학적 플레이팅(ECP : Electro Chemical Plating) 방법을 이용한 구리 배선 증착 공정은, 구리 다마신(Damascene) 공정으로 구현되는 Cu BEOL(Back End OF Line) 배선의 형성에 있어서 반드시 필요한 공정이다. 이는 다마신(Damascene) 패턴으로 구현된 작은 크기(size)의 비아 홀(hole) 및 트렌치(trench)영역에 대한 구리 배선을 채우는 공정으로 수행되게 된다.The copper wiring deposition process using the electrochemical plating (ECP) method is an essential process for forming a Cu BEOL (Back End OF Line) wiring implemented by a copper damascene process. This is performed by a process of filling a copper wiring for a small sized via hole and trench region implemented by a damascene pattern.

이러한 구리의 전기 화학적 플레이팅(Cu ECP) 공정에서는 구리 도금이 완료된 후에 시간 지연(time delay)을 최소화하여 웨이퍼의 표면을 제 때 린싱(rinsing)해 주지 않으면, 구리 도금에 사용되는 산성 전해액(electrolyte)이 표면에 남은 채로 건조(dry)되어 웨이퍼 표면의 심한 산화(oxidation)현상을 유발시키게 된다. In the copper electrochemical plating (Cu ECP) process, an acidic electrolyte used for copper plating is used unless copper rinsing the surface of the wafer in time to minimize time delay after copper plating is completed. ) Is left on the surface, causing severe oxidation of the wafer surface.

일단 산화 현상이 발생한 웨이퍼의 표면은 단순한 DIW(Deionized Water)를 이용한 린싱(rinsing)법으로는 제거하기가 불가능한데, 이는 웨이퍼 표면에 형성되게 되는 Cu의 산화물 때문이다.The surface of the wafer, once oxidized, cannot be removed by a simple rinsing method using DIW (Deionized Water) because of the oxide of Cu formed on the surface of the wafer.

구리의 전기화학적 플레이팅(Cu ECP) 공정 상에서 종종 나타나는 이러한 산화현상은, 린싱 등을 수행하는 공정장비가 제대로 기능을 발휘하지 못하여 후속 린싱(rinsing) 처리가 제대로 이루어지지 못할 때 종종 발생한다.This oxidation phenomenon, which often occurs in the copper electrochemical plating (Cu ECP) process, often occurs when the process equipment performing the rinsing or the like does not function properly and the subsequent rinsing treatment is not performed properly.

상기와 같은 종래의 웨이퍼는 다음과 같은 문제점이 있다.The conventional wafer as described above has the following problems.

전기 화학적 플레이팅 공정을 통해 구리 배선을 증착한 후에, 린싱 처리가 이루어져야 하는데, 이러한 린싱 처리시에 지연이 발생하거나, 제대로 처리가 되지 않게 되면 웨이퍼 표면은 공기 중에서 산화되어 표면 산화막이 형성된다.After depositing the copper wiring through the electrochemical plating process, a rinsing process should be performed. If a lag occurs or the process is not properly processed, the wafer surface is oxidized in air to form a surface oxide film.

종래에는 이러한 웨이퍼 표면에 린싱 전에 형성되는 산화막에 대해 처리하는 방법이 별다르게 없었고, 단순히 소정의 용액에 담그는 방법(immersion)만이 제시되었다. 그러나, 이와 같은 담금법으로는 완전히 웨이퍼 표면의 산화막이 제거되기 힘들게 된다.Conventionally, there has been no method of treating an oxide film formed on the wafer surface before rinsing, and only a method of immersion in a predetermined solution has been proposed. However, such an immersion method makes it difficult to completely remove the oxide film on the wafer surface.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 표면 산화된 웨이퍼를 전해액을 이용하여 회복(recovery)하는 웨이퍼 표면 처리 방법을 제공하는 데, 그 목적이 있다.An object of the present invention is to provide a wafer surface treatment method for recovering a surface oxidized wafer using an electrolyte solution, which has been devised to solve the above problems.

상기와 같은 목적을 달성하기 위한 본 발명의 웨이퍼 표면 처리 방법은 표면 산화된 웨이퍼를 산성 전해액이 담긴 식각액에 넣어 상기 웨이퍼의 표면 산화막을 제거하는 것에 그 특징이 있다.Wafer surface treatment method of the present invention for achieving the above object is characterized by removing the surface oxide film of the wafer by putting the surface oxidized wafer in an etching solution containing an acidic electrolyte solution.

상기 산성 전해액에 웨이퍼를 넣을 때, 상기 산성 전해액에 전류를 흘러줌을 특징으로 한다.When the wafer is placed in the acidic electrolyte, it is characterized by flowing a current through the acidic electrolyte.

이하, 첨부된 도면을 참조하여 본 발명의 웨이퍼 표면 처리 방법을 상세히 설명하면 다음과 같다.Hereinafter, a wafer surface treatment method of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 웨이퍼의 표면 처리 방법을 나타낸 공정 순서도이다.1A to 1C are process flowcharts showing the surface treatment method of the wafer of the present invention.

도 1a와 같이, 구리 다마신 방법에 있어서, BEOL(Back End Of Line)의 구리 도금을 완료한 후, 린싱 처리하지 못하고 소정의 시간이 지연되면, 도 1a와 같이, 웨이퍼(10) 표면에 산화가 일어나 부신된 것처럼 붉게 관찰된다.As shown in FIG. 1A, in the copper damascene method, after completion of copper plating of the BEOL (Back End Of Line), if the rinsing treatment is not performed and a predetermined time is delayed, the surface of the wafer 10 is oxidized as shown in FIG. It is observed to appear red as it is adrenal.

도 1b와 같이, 본 발명의 웨이퍼 표면 처리 방법에 있어서는, 상기 표면이 산화된 웨이퍼(10)를 소정의 산성 전해액이 들어있는 식각조(20)에 넣어 상기 웨이퍼(10) 표면으로부터 소정 두께 제거한다.As shown in FIG. 1B, in the wafer surface treatment method of the present invention, the wafer 10 whose surface is oxidized is placed in an etching bath 20 containing a predetermined acidic electrolyte solution and a predetermined thickness is removed from the surface of the wafer 10. .

이어, 도 1c와 같이, 상기 표면 산화막이 제거된 웨이퍼(10a)를 린싱(rinsing) 및 건조한다.Subsequently, as illustrated in FIG. 1C, the wafer 10a from which the surface oxide film is removed is rinsed and dried.

이와 같은 웨이퍼의 표면 처리를 진행하기 전과 진행한 후는 다음의 사진에서 그 변화를 잘 관찰할 수 있다.Before and after the surface treatment of such a wafer, the change can be observed well in the following photograph.

도 2는 본 발명의 웨이퍼의 표면 처리 방법을 적용 전 사진이며, 도 3은 본 발명의 웨이퍼의 표면 처리 방법을 적용 후 사진이다.2 is a photograph before applying the surface treatment method of the wafer of the present invention, Figure 3 is a photograph after applying the surface treatment method of the wafer of the present invention.

웨이퍼의 표면 처리 전에는 도 2와 같이, 상기 웨이퍼(10) 내 소정의 원 형상으로 산화막이 형성된다. 이 크기는 전기 화학적 플레이팅 방법으로 구리 배선을 증착 후에 린싱까지의 지연시간의 정도에 따라 달라질 수 있을 것이다.Before the surface treatment of the wafer, an oxide film is formed in a predetermined circular shape in the wafer 10 as shown in FIG. 2. This size may vary depending on the degree of delay from deposition of copper wiring to rinsing by electrochemical plating.

그리고, 웨이퍼의 표면 처리를 진행하게 되면, 도 3과 같이, 그 표면의 산화막이 완전히 제거되어 오염되지 않은 웨이퍼를 관찰할 수 있다.When the surface treatment of the wafer is performed, as shown in FIG. 3, the oxide film on the surface of the wafer is completely removed to observe the uncontaminated wafer.

이 경우, 웨이퍼의 표면 처리는 산성 전해액을 이용하며, 예를 들어, H2 SO4 성분을 이용한다. 상기 산성 전해액이 들어있는 식각조(20)에 웨이퍼를 넣었을 때는, 웨이퍼 표면에 구리 산화막(Cu Oxide)이 제거된다.In this case, the surface treatment of the wafer uses an acidic electrolyte solution, for example, using a H 2 SO 4 component. When the wafer is placed in the etching bath 20 containing the acidic electrolyte solution, copper oxide (Cu Oxide) is removed from the wafer surface.

이하에서는 본 발명의 웨이퍼 표면 처리 방법을 3개의 웨이퍼에 대해 진행한 것으로, 전기적 접촉을 하는 포인트 측정 전과 후에 식각된 두께의 최대-최소 균일도를 측정하였다. 이 경우, 포인트 측정 전후의 차이가 없다.In the following, the wafer surface treatment method of the present invention was carried out on three wafers, and the maximum-minimum uniformity of the etched thickness was measured before and after measuring the point of electrical contact. In this case, there is no difference before and after the point measurement.

도 4는 본 발명의 웨이퍼 표면 처리 방법에 적용되는 전해액 내에서의 습식각률 데이터에 관한 표이다.4 is a table relating to the wet etch rate data in the electrolyte applied to the wafer surface treatment method of the present invention.

도 4와 같이, 본 발명의 웨이퍼 표면 처리를 진행할 때, 식각되는 두께는 182Å, 218Å, 108Å 정도로, 각각의 습식각률은 728Å/min, 872Å/min, 432Å/min로, 평균 습식각률은 약 677Å/min에 해당하였다.As shown in Fig. 4, when the wafer surface treatment of the present invention is performed, the etched thickness is about 182 kPa, 218 kPa and 108 kPa, and the respective wet etch rates are 728 kPa / min, 872 kPa / min and 432 kPa / min, and the average wet etching rate is about 677 kPa. It corresponded to / min.

이와 같이, 본 발명의 웨이퍼 표면 처리 방법에 있어서는, 어떤 웨이퍼는 일정 두께 이상, 웨이퍼 표면으로부터 수 십 nm 두께의 산화막이 최대-최소 균일도(불균일도: non-uniformity)의 증가없이 제거된다. 즉, 거의 균일하게 웨이퍼 상부의 산화막이 제거되는 것이다.Thus, in the wafer surface treatment method of the present invention, some wafers are removed from the wafer surface by a thickness of several tens of nm or more without increasing the maximum-minimum uniformity (non-uniformity). In other words, the oxide film on the wafer is almost uniformly removed.

상기와 같은 본 발명의 웨이퍼 표면 처리 방법은 다음과 같은 효과가 있다.The wafer surface treatment method of the present invention as described above has the following effects.

전기 화학적 플레이팅 방법으로 형성된 구리 배선 형성 후, 종종 발생하는 표면이 산화된 웨이퍼에 있어서, 전해액을 통해 표면 산화막을 제거하여 줌으로써, 반도체 제조 시에 스크랩(scrap)되는 웨이퍼를 줄여 생산성을 극대화 할 수 있으며 따라서, 반도체 제조 경비의 절감을 기대할 수 있다. After formation of copper wiring formed by electrochemical plating method, in a wafer whose surface is often oxidized, by removing the surface oxide film through the electrolyte, it is possible to maximize productivity by reducing wafers scraped during semiconductor manufacturing. Therefore, it is expected to reduce the semiconductor manufacturing cost.

특히, 특별한 회복(recovery) 장치(예를 들어, 식각 장비 혹은 스크러버(scrubber))에 대한 추가 요구가 필요없이, 구리의 전기 화학적 플레이팅(Cu ECP) 공정을 진행하는 장비 자체를 이용하여 회복할 수 있다는 장점이 있다.In particular, there is no need for additional recovery equipment (eg etching equipment or scrubbers), and the equipment itself can be recovered using the copper electrochemical plating (Cu ECP) process. There is an advantage that it can.

Claims (2)

구리가 전기 화학적으로 플레이팅된 후 표면 산화된 웨이퍼를 전류가 흐르는 산성 전해액이 담긴 식각액에 넣어 상기 웨이퍼의 표면 산화막을 제거하는 것을 특징으로 하는 웨이퍼 표면 처리 방법.And after the copper is electrochemically plated, the surface oxidized wafer is placed in an etchant containing an acidic electrolyte flowing through the current to remove the surface oxide film of the wafer. 삭제delete
KR1020040117593A 2004-12-31 2004-12-31 Method for Surface Treatment in Cu Wafer KR100640967B1 (en)

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