KR100639985B1 - Apparatus for generating a on-chip network topology and method therefor - Google Patents

Abstract

An on-chip network topology generating apparatus and method are disclosed. By performing the reference code implemented by the design specification of the algorithm step, it analyzes the communication requirements between the IP modules, and generates a binary tree with the IP modules as the lowest child node based on the communication requirements between the IP modules. Then, among all cases where merging between the lower nodes connected to the predetermined intermediate node and the predetermined intermediate node of the binary tree is possible, the process of selecting a merge that minimizes the value of the cost function defined based on the area and the communication delay time is performed. Reorganize the tree by running up to the root node. This allows the creation of an on-chip network topology with minimal area and communication latency.

On-Chip Network Topology, IP Modules, Communication Requirements, Binary Trees

Description

Apparatus for generating a on-chip network topology and method therefor}

1A-1C illustrate various topologies of an on-chip network;

FIG. 2 illustrates a crossbar switch used in a star network topology. FIG.

3A to 3C show an example of data communication requirements between components in an actual design circuit;

4A to 4C are graphs comparing chip areas when a single crossbar switch structure and a tree structure are used;

5A is a diagram illustrating a configuration of an embodiment of an on-chip network topology generating device according to the present invention;

6A, 6B, and 7A to 7E illustrate an embodiment of a binary tree generation process;

8A to 8D illustrate an embodiment of a tree optimization method;

9A-9D illustrate each step of generating an on-chip network topology, and

10A and 10B illustrate an example of critical path search and path addition.

The present invention relates to an on-chip network topology generating apparatus and method thereof.

SoC (System-on-Chip) design method is focused on the platform-oriented design to develop SoC for a variety of systems in a short time, the data communication structure together with the processor is the core of the design. As the number of devices integrated in an SoC increases, the amount of data that must be transmitted and received between each component module is rapidly increasing, and the design of a communication structure for this is becoming more difficult.

On-chip buses such as Multi-layer AMBA and Silicon Backplane, which are widely used in embedded systems, are becoming a big performance constraint for multimedia applications requiring large data communication due to data bandwidth limitations.

The existing on-chip bus structure is not suitable for applications requiring real-time data transmission and reception by sharing the limited communication media with multiple communication entities in a time based multiplexed manner.

In addition, the limitations of on-chip buses where multiple core components share a bus include performance degradation, poor reuse rate due to various interface requirements, and limitations in data bandwidth scalability. As the number of connected core components increases, There is a disadvantage in that a lot of power is consumed because the loading capacity is increased. In addition, in order to obtain the same data bandwidth as the on-chip network, the clock frequency driving the bus is increased, resulting in increased power consumption at the same performance.

Therefore, for SoC design that can integrate various processor cores, memory, and IP (Intellectual Properties) on a single chip, on-chip network technology having scalability and reusability is required. In addition, enabling high-performance SoC designs using on-chip networks requires design automation methods based on on-chip network architecture design and verification techniques.

Unlike general-purpose computer networks in the real world, the on-chip network is implemented in one semiconductor chip. Since this is almost constant, the implementation of a network structure specialized for each design can greatly reduce the chip area which has an absolute influence on the manufacturing cost of the semiconductor chip, and improve the performance as well as the power consumption.

1A-1C illustrate various topologies of an on-chip network.

FIG. 1A illustrates a topology of a star on-chip network, FIG. 1B illustrates a topology of a mesh-type on-chip network, and FIG. 1C illustrates a topology of a torus-type on-chip network. One drawing.

Star topology is advantageous in terms of performance and chip area when the number of components with mutual communication requirements is not relatively high, and mesh and torus topology is very advantageous in scalability when the number of components is large. Globally, star topologies are expected to be the most advantageous for SoC designs within the next five years, and star topologies are being applied to several designs. The mesh and torus topologies are very general structures and can be applied in the future when the number of components will be very large.

FIG. 2 illustrates a crossbar switch used in a star network topology.

3A to 3C are diagrams showing examples of data communication requirements between components in actual design circuits.

4A to 4C are graphs comparing chip areas when a single crossbar switch structure and a tree structure are used.

Referring to FIG. 2, by simply connecting components to ports of a crossbar switch, a design of a communication structure is not required. Therefore, a design time is shortened and a plurality of components can communicate at the same time. The performance is excellent, compared to.

However, in general, the communication requirements between the IPs are not equal as in the example of FIG. 3, so when designing with one crossbar switch, not only wastes data bandwidth but also wastes chip area when there are unused ports.

In addition, as the number of connected IP increases, the area of the crossbar switch is proportional to the square of the number of ports as shown in FIG. 4, thereby reducing the clock speed of the switch, thereby reducing the performance of the entire network. If the switch library is not designed for the desired number of ports, unused ports are generated, which wastes valuable chip resources. Therefore, there is a need for an application design specialized on-chip network optimized for the characteristics of each design itself.

However, it is very difficult and time-consuming to analyze the communication requirements between the components of each design and find the most suitable communication structure according to each design. Therefore, when designing by the designer's hand, a single switch or the experience of the designer is generally required. It is very inefficient to design with a dependent structure.

A design automation tool that automatically synthesizes the on-chip network-based communication structure optimized for each design is called an on-chip network compiler. Although much research has not been done so far, Xpipes On-Chip-Network (OCN) compiler from Stanford University There is. The Xpipes compiler supports on-chip networks of various topologies and outputs SystemC code as a result of synthesis. However, Xpipes supports a variety of network topologies but does not create the most customized network for each design because of the way they map to a given topology.

It is an object of the present invention to provide an apparatus and method for automatically generating an on-chip network topology optimized to minimize chip area and communication delay time.

Another technical problem to be solved by the present invention is to provide a computer-readable recording medium having recorded thereon a program for executing on a computer a method for automatically generating an on-chip network topology optimized to minimize chip area and communication latency. There is.

In accordance with one aspect of the present invention, there is provided an apparatus for generating an on-chip network topology according to an embodiment of the present invention, comprising: a traffic analysis unit configured to analyze a communication requirement between IP modules by performing a reference code in which a design specification of an algorithm step is implemented; A tree generation unit generating a binary tree having the IP modules as the lowest child nodes based on the communication demands between the IP modules; And selecting merging in which all of the lower nodes connected to the predetermined intermediate node of the binary tree and the predetermined intermediate node are merged with the minimum value of the cost function defined based on the area and the communication delay time. It includes; tree optimizer for performing up to the root node of the binary tree.

In order to achieve the above technical problem, an embodiment of the method for generating an on-chip network topology according to the present invention includes: analyzing communication requirements between IP modules by performing a reference code in which a design specification of an algorithm step is implemented; Generating a binary tree having the IP modules as the lowest child nodes based on the communication demands between the IP modules; And selecting merging in which all of the lower nodes connected to the predetermined intermediate node of the binary tree and the predetermined intermediate node are merged with the minimum value of the cost function defined based on the area and the communication delay time. And reconstructing the tree by performing up to the root node of the binary tree.

This allows the creation of an on-chip network topology with minimal area and communication latency.

Hereinafter, an on-chip network topology generating apparatus and method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

5A is a diagram illustrating a configuration of an embodiment of an on-chip network topology generating apparatus according to the present invention.

Referring to FIG. 5A, the on-chip network topology generating apparatus includes a traffic analyzer 500, a tree generator 510, a tree optimizer 520, a critical path searcher 530, and a topology generator 540. .

The traffic analysis unit 500 performs a reference code in which a design specification of an algorithm step is implemented and calculates a communication request between respective IP modules in an actual execution environment. In other words, the traffic analysis unit 500 executes a program that executes a reference code in which a design specification of an algorithm step written in C code or SystemC code is implemented to generate a communication request in an actual execution environment. In step), communication requirements between the respective IP modules are analyzed.

That is, the traffic analysis unit 500 accumulates the amount of data movement between the functions on the reference C code corresponding to the respective IP modules for each function and finally outputs the accumulated data movement amount. The present invention optimizes the on-chip network topology based on the traffic amount calculated by the traffic analysis unit 500.

The tree generation unit 510 is arranged by the traffic analysis unit 500 after the analysis of the communication requirements between the respective IP modules is completed, placed close to the IP modules having a large communication demands and assigned to one crossbar switch as possible. By clustering the IP modules to minimize the communication delay time and the traffic between the communication lines. The tree generating unit 510 uses a binary tree splitting method of forming a tree by combining two IP modules in a bottom-up manner for clustering.

Specifically, the tree generating unit 510 first introduces a parent node having two communication modules having high communication demands among each other among all the IP modules and having them as child nodes, and then applies all communication requests of the child nodes. Assign to the parent node. Then, the tree generating unit 510 introduces the next higher level of nanny node having two parent nodes and grouping them two by one in order of high communication demand as in the previous method. The tree generator 510 performs this process until all IP blocks are included in the tree to generate a binary tree. One embodiment of binary tree generation is shown in FIGS. 6A, 6B and 7A-7E.

6A to 7E, an embodiment of generating a binary tree will be described first. Referring to FIG. 6A, there are six IP modules of p1 600, p2 602, ip1 604, ip2 606, m1 608, and m2 610, and communication analyzer 500. The communication requirements between the respective IP modules analyzed by are presented. FIG. 6B is a binary tree generation result of FIG. 6A generated by the tree generator 510. The production process from FIG. 6A to FIG. 6B is illustrated in FIGS. 7A to 7E.

Referring to FIG. 7A, first, IP modules having a high communication demand are bundled together based on a communication demand between IP modules, and parent nodes 700 and 702 are introduced and connected. Then, as shown in FIG. 7B, the two nodes are bundled based on the communication requirements of the remaining IP modules 604 and 606 that are not tied to the parent nodes, and the parent node 704 is introduced and connected again (FIGS. 7B, 7C, and 7D). This method is repeated to finally complete the binary tree as shown in FIG. 7E.

When the intermediate nodes of the binary tree are implemented as 2x1 crossbar switches by the tree generating unit 510, fast communication is possible between IP modules allocated to one crossbar switch, but in some cases, communication is performed through several crossbar switches. If there are too many crossbar switches in the middle of the communication channel, the chip area may increase.

Therefore, a tree optimization process that minimizes the area occupied by the switch and communication delay time through the tree optimization process is required.

The tree optimizer 520 merges intermediate nodes on the tree as needed by using a dynamic programming technique to minimize the area and delay time. To measure the scale of optimization task, first, the cost function is defined as in Equation 1 below.

Here, the constants a and b are calculated experimentally.

Looking at the tree optimization method by the tree optimizer 520 in detail, first the binary tree to the root node starting from the lowest child node of the binary tree (Depth First Search), each intermediate node of the tree Use the solution of all possible node merges computed in the subtree to find the merge solution that minimizes the value of the cost function at the intermediate node level. This node merging process is continued for the intermediate nodes to find a tree with the minimum value of the cost function of the entire tree.

An example of the tree optimization method is shown in FIGS. 8A-8D. Referring to FIGS. 8A to 8D, one example of a tree optimization method is divided into four methods for merging intermediate nodes of a binary tree. First, as shown in FIG. 8A, when the two child nodes 802 and 804 that are the root nodes of the lower subtree and the parent node 800 that are the root nodes of the one-level higher subtree including them are not merged, the right child as shown in FIG. 8B. When merging with the node 804, when merging with the left child node 802 as shown in FIG. 8C, and when the parent node 800 and both child nodes 802 and 804 are merged as shown in FIG. 8D.

The tree optimizer 520 obtains a solution of the cost function for each of the merges shown in FIGS. 8A to 8D, selects a solution of the least cost among them, and determines the solution of the current subtree. When the solution of the minimum cost function of all subtrees is determined, the four merge processes of FIGS. 8A to 8D are performed again by using the solution of the cost function of each sub-node and the root node in a higher level subtree. The solution of the cost is performed until the entire binary tree is included.

9A to 9D illustrate an example of each step of generating an on-chip network topology optimized by the traffic analyzer 500, the tree generator 510, and the tree optimizer 520 described with reference to FIG. 5. to be. FIG. 9A shows a result of analyzing the amount of communication between the respective IP modules by the traffic analyzer 500 (see FIG. 6A), and FIG. 9B shows the amount of communication between the respective IP modules by the tree generator 510. Fig. 6B and 7E show the binary tree generated based on Fig. 9C, and Fig. 9C shows a tree optimized by the tree optimizer 520, and Fig. 9D shows the optimized tree of Fig. 9D. On-chip network topology is implemented by replacing intermediate nodes with crossbar switches.

The critical path search unit 530 does not have a large amount of communication depending on the communication characteristics between the IP modules, but in the case of a critical path that may cause an abnormal operation when the communication delay time increases by more than a predetermined threshold, the critical path delay time ( Insert paths between these IP modules to reduce Critical Path Delay. In this case, since the communication channel is connected to the crossbar switch to which each IP module belongs, the number of ports of each of the two crossbar switches increases by 1, which reduces the overall communication delay time but increases the area.

Accordingly, the critical path search unit 530 selects a newly inserted communication channel when the total communication delay time is reduced and the sum of the areas does not exceed a predetermined limit when the communication channel is connected between the crossbar switches for a predetermined critical path. Otherwise, remove the added path. This greedy optimization is performed until there are no more critical paths to choose from, or there is no further improvement in communication latency.

10A and 10B illustrate an example of threshold path search and path addition by the threshold path search unit 530. 10A and 10B, the threshold path search unit 530 searches for a critical path between the left lowest child node 1000 and the node 1010 having a communication delay time greater than or equal to a predetermined threshold. The critical path search unit 530 adds a path between intermediate nodes 1010 and 1012 connected to the critical path. This adds a communication channel between crossbar switches when intermediate nodes are implemented as crossbar switches.

The topology generating unit 540 optimizes the tree by the tree optimizer 520 and optionally adds the number of ports corresponding to the number of nodes connected to the intermediate nodes in the tree where the additional path is inserted by the critical path search unit 530. It changes to a crossbar switch having the same, and generates and outputs an on-chip network topology by connecting the IP modules to the crossbar switch in the same manner as the connection structure of the tree.

5B is a flowchart illustrating a flow of an embodiment of an on-chip network topology generation method according to the present invention.

Referring to FIG. 5B, first, a profiling that generates a communication request in an actual execution environment is performed by performing a reference code in which a design specification of an algorithm step written in C code or SystmeC code is implemented (S550). The profiling step analyzes the communication requirements between the respective IP modules (S555), and generates a binary tree including the IP modules as the lowest nodes based on the analyzed communication requirements (S560).

The binary tree is optimized by applying a dynamic programming technique to optimize the binary tree to minimize the area and communication delay time (S565), and search for critical paths between IP modules having a communication delay time greater than or equal to a predetermined threshold to directly connect the IP modules. Add (S570). And finally, generates an On Chip Network (OCN) SystemC code for the tree (S575), and simulates the performance (S580).

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

According to the present invention, an algorithm-based design specification executes a reference code and analyzes a communication pattern, thereby automatically generating an optimal on-chip network. Therefore, it is possible to output the communication structure optimized by the network topology that minimizes the chip area and maximizes the performance to SystemC and VHDL, and to synthesize it with simulation and hardware.

Claims (12)

A traffic volume analyzer configured to analyze a communication requirement between IP modules by performing a reference code in which a design specification of an algorithm step is implemented; A tree generation unit generating a binary tree having the IP modules as the lowest child nodes based on the communication demands between the IP modules; And Among all possible mergers of the lower nodes connected to a predetermined intermediate node of the binary tree and the predetermined intermediate node, a process of selecting a merge of which a value of a cost function defined based on area and communication delay time is minimized is selected. On-chip network topology generating device comprising a; tree optimization unit for performing up to the root node of the tree. The method of claim 1, On-chip network topology generation device further comprising; a critical path search unit for inserting a path between the IP modules having a communication delay time of more than a predetermined threshold after the node merging process of the binary tree is completed. The method according to claim 1 or 2, The intermediate nodes of the tree generated through the node merging process of the binary tree are replaced with crossbar switches having as many ports as the nodes connected to the intermediate nodes, and the IP modules are connected to the crossbar switches in the same manner as the connection structure of the tree. On-chip network topology generating device further comprising; a topology generating unit for connecting. The method of claim 1, wherein the traffic analysis unit, And accumulating the amount of data movement between the functions of the reference code for each function and analyzing the communication requirements between the IP modules. The method of claim 1, wherein the tree generation unit, Group the two IP modules based on the order of the high communication demands between the IP modules, introduce the parent nodes having the respective IP modules as the child nodes, and allocate the communication requirements of the child nodes to the parent nodes. And generating a binary tree by repeating the step of introducing two higher parent nodes in order of increasing communication requirements between the parent nodes. The method of claim 1, wherein the tree optimizer, When merging with the right subnode connected with the predetermined intermediate node, when merging with the left subnode connected with the predetermined intermediate node, when merging with both the right and left subnodes connected with the predetermined intermediate node, The on-chip network topology generating device, wherein the merging of the minimum value of the cost function is selected from among the intermediate nodes and no subnodes. Analyzing a communication requirement between IP modules by performing a reference code in which a design specification of an algorithm step is implemented; Generating a binary tree having the IP modules as the lowest child nodes based on the communication demands between the IP modules; And Among all possible mergers of the lower nodes connected to a predetermined intermediate node of the binary tree and the predetermined intermediate node, a process of selecting a merge of which a value of a cost function defined based on area and communication delay time is minimized is selected. And reconstructing the tree by performing up to the root node of the tree. The method of claim 7, wherein And inserting a path between the IP modules having a communication delay time equal to or greater than a predetermined threshold. The method according to claim 7 or 8, Changing the intermediate nodes of the reconstructed tree into crossbar switches having as many ports as the nodes connected to the intermediate nodes, and connecting the IP modules to the crossbar switches in the same manner as the connection structure of the reconstructed tree to generate a topology The on-chip network topology generation method further comprising. The method of claim 7, wherein the traffic analysis step, And accumulating the amount of data movement between the functions of the reference code for each function and analyzing the communication demands between the IP modules. The method of claim 7, wherein the tree generation step, Group the two IP modules based on the order of the high communication demands between the IP modules, introduce the parent nodes having the respective IP modules as the child nodes, and allocate the communication requirements of the child nodes to the parent nodes. And generating a binary tree by repeating the step of introducing two higher parent nodes by binding the two nodes in order of increasing communication demands between the parent nodes. 2. The method of claim 7, wherein the tree reconstruction step, When merging with the right subnode connected with the predetermined intermediate node, when merging with the left subnode connected with the predetermined intermediate node, when merging with both the right and left subnodes connected with the predetermined intermediate node, Selecting a merging in which the value of the cost function is the minimum among cases in which the intermediate node and no subnodes are not merged.

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