KR100636218B1 - Delay compensation circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay compensation circuit. In particular, a delay compensation circuit for generating a reverse control clock signal by delaying a delay control clock signal by 180 degrees out of phase by using a delay element line having no constraint on duty. To provide. The compensation circuit for this purpose includes a phase detector which detects a phase of an input reference clock signal, a delay controller that determines whether to lock the phase signal output from the phase detector, and adjusts a delay value of the phase detector, and the delay controller. A delay processor for delaying an input signal by receiving a delay value, the delay processor including a delay processor to generate a reverse control clock signal by delaying the delay control clock signal by 180 degrees with a plurality of delay elements. Thus, according to the present invention, the delay control line signal is further provided to generate the inversion control clock signal, so that the duty of the existing delay device line does not need to be ± 5%. Therefore, when designing the delay element line, the burden on the duty can be reduced, and the delay element line can be effectively designed.

Description

Delay compensation circuit

1 is a block circuit diagram schematically showing a conventional delay compensation circuit.

FIG. 2 is a detailed circuit diagram of the phase detector of FIG. 1.

3 is a detailed circuit diagram of the delay device of FIG. 2.

4 is a detailed circuit diagram of the delay element line of FIG. 2.

5 is a detailed circuit diagram of the read processing unit of FIG. 1.

6 is a waveform diagram illustrating a delay control clock signal and an inversion control clock signal.

7 is a detailed circuit diagram of a lead processing unit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1 ... delay compensation circuit 2 ... reference clock signal

10 Phase detection section 20 Delay control section

30 ... Lead processing part 40 ... Light processing part

100 second delay element line 104 delay control clock signal

Inverting control clock signal 110, 111, 11n ...

120, 121, 12n ... delay control signal 310 ... lead control signal input

320 ... first delay element line 330 ... data lead part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay compensation circuit. In particular, a delay compensation circuit for generating a reverse control clock signal by delaying a delay control clock signal by 180 degrees out of phase using a delay element line having no duty constraint It is about.

Due to the asynchronous nature of dynamic random access memory (DRAM), the timing for data transfer between application specific integrated circuits (ASICs) and DRAM has become an important factor. In addition, as the system, for example, a printer or a multifunction device, becomes faster, the frequency of the system increases, and a phenomenon in which a valid data window decreases sharply occurs.

Accordingly, a logic circuit for accurately reading and writing data on a narrow valid data window is required, and a delay compensation circuit (DCC) plays this role.

In the case of using a delay compensation circuit (DCC), the ASIC can capture read data at a desired position, so it is not a problem even in a narrow valid data window. In addition, even when the ASIC writes data toward the DRAM, a write control signal can be transmitted so that the DRAM can correctly capture the data.

However, in the case of the conventional delay compensation circuit, when the delay control clock signal clk_dqs for capturing data is generated, the duty of the delay element line is very high. Plays an important role. That is, there is a constraint that the duty of the delay control clock signal (clk_dqs) passing through the delay element line must be within a range of 45% to 55%.

1 is a block circuit diagram schematically showing a conventional delay compensation circuit. FIG. 2 is a detailed circuit diagram of the phase detector of FIG. 1. 3 is a detailed circuit diagram of the delay device of FIG. 2. 4 is a detailed circuit diagram of the delay element line of FIG. 2.

As shown in FIG. 1, the delay compensation circuit DCC controls a phase detection unit Dll_phase_detect 10 for detecting a phase of the input reference clock signal 2 and a delay of the phase detection unit 10. The delay control unit (dll_delay_control) 20 and the read / write processing unit (dll_rd_dqs_slice / dll_wr_dqs_slice) 30 and 40 which delay the read signal / write signals by a predetermined delay value from the phase detection unit 10.

As shown in FIG. 2, the phase detector 10 includes a delay element (dll_delay_element) 16 having a delay minimum unit configuration and a delay element line (dll_delay_line) 18 including a delay element (delay element). And two flip-flops 11 and 13 generating a first phase signal 12 and a second phase signal 14 to detect the phase.

As shown in FIG. 3, the delay element dll_delay_element 16 passes through an in port signal 162 through a buffer 163. 164 and an output port 169 for selectively outputting in and ret signals. The delay of the delay element 16 is the sum of the delay of the buffer 163 and the delay of the mux 166.

The phase detector 10 receives a reference clock signal 2 and uses a delay element 16, a delay element line 18, and two flip-flops 11 and 13 as minimum delay units. It serves to detect the period of the signal 2. In addition, the phase detector 10 detects the phase of the reference clock signal 2 passing through the delay element line 18, and detects how many delay elements or delay cells the reference clock signal is composed of. Do this.

The delay controller 20 determines whether or not phase lock is performed using the phase signals 12 and 14, which are outputs of the phase detector 10, according to the control input 4. If it is not locked, the delay control signal (sel_num_delay_elements) 22 outputted to the phase detector 10 is adjusted to increase or decrease the delay value of the delay element line 18 of the phase detector 10. In this case, the adjustment unit is a delay element 180-18n having a delay value of the minimum delay unit. That is, the delay control unit 20 adjusts the delay control signal 22 so that the output of the first phase signal 12 is "low", and the output of the second phase signal 14 is output. Find a lock that is "high". When locked, the delay control signal 22 at this time is encoded and output as an encoder signal 24.

The delay of the delay element 16, which is the minimum unit of delay, may be as small as possible in order to increase the resolution. Typically, when using a reference clock (100MHz ~ 200MHz) has a delay time of 100psec ~ 150psec.

When the delay element line dll_delay_line 18 as shown in FIG. 4 is configured with a delay element having a small delay value as described above, the delay element 180 is composed of many delay elements 180-18n. Should. When configuring one delay element line 18 at a 100 MHz reference clock, approximately 100 delay elements 180-18n should be used.

5 is a detailed circuit diagram of the lead processor 30 of FIG. 1. 6 is a waveform diagram showing a delay control clock signal (clk_dqs) 304 and an inversion control clock signal (clk_dqs_n) 306. FIG.

As shown in FIG. 5, the read processing unit 30 includes a read control signal input unit 310, a first delay element line 320, an inversion control clock signal generation unit 300, and a data lead unit 330. do.

The read control signal input unit 310 inputs a read control signal read_dqs 34 according to an input control signal 312 and outputs a clean read control signal clean_dqs_mod 314. According to the control clock selection signal sel_clk_dqs 344 output from the delay control slice dll_delay_control_slice 340 inputting the encoder signal 24, the first delay element line 320 may be a clean read control signal ( The delayed control clock signal delayed_dps 322 is generated and outputted by delaying 314.

The inversion control clock signal generation unit 300 inputs the delayed control clock signal delayed_dps 322 to output the delayed control clock signal clk_dqs 304 and the inverted control clock signal clk_dps_n 306. The data lead unit 330 reads data (read_data) 32 received using the delay control clock signal (clk_dqs) 304 and the inversion control clock signal (clk_dps_n) 306.

As described above, the phase detector 10 detects the phase of the reference clock signal 2 that has passed through the delay element line 18, and detects how many delay elements the reference clock signal 2 is composed of. Perform. Thus, for example, when the reference clock signal 2 is detected by the phase detection unit 10 to have a phase difference of 360 degrees when passing through 80 delay elements, the read processing unit 30 has a phase difference of 90 degrees. A delay control clock signal (clk_dqs) 304 passing two delay elements and an inversion control clock signal (clk_dqs_n) 306 having a phase difference of 180 degrees with the delay control clock signal (clk_dqs) are generated and read data (read data). ) Can capture data even in a narrow valid data window. Even in the case of data write, the delay compensation circuit converts the write clock signal clk_wr 42 to easily capture data from a DRAM corresponding to a receiving end, for example, DDR-SDRAM (Double Data Rate Synchronous DRAM). Create from (DCC). At this time, the light clock signal clk_wr 42 also passes through 20 delay cells to have a phase difference of 90 degrees with the reference clock signal 2 to generate the light clock signal clk_wr 42. Therefore, the newly generated delay control clock signal (clk_dqs) 304, inversion control clock signal (clk_dqs_n) 306, write clock signal (clk_wr) 42, and control clock output signal (clk_dqs_out) 44 are used. This enables accurate capture of data in narrow valid data windows.

6, read data read_data 32, read control signal read_dqs 34, delayed control clock signal delayed_dqs 322, delayed control clock signal clk_dqs 304, and inversion control. The waveforms of the clock signal (clk_dqs_n) 306 are shown.

As described above, in order to find out whether the delayed clock signal has a phase difference of 360 degrees from the reference clock signal 2, a delay line must be composed of a large number of delay elements. This is to satisfy both the operating frequency of the system in which the DDR-SDRAM is embedded and the operating condition of the chip.

Therefore, when the delay value of one delay element is 80 psec and the system operates at 80 MHz, the number of delay elements is about 140. In this case, the duty of the delayed clock output through the 140 delay elements is not easy to satisfy 45% to 55%. In other words, it is not easy to satisfy the specification of ± 5% up to the duty while designing with a focus on the delay value of the delay element.

In this case, the same delay line should be reused in the read processing unit 30 and the write processing unit 40, but may not be reused in the read processing unit 30. This is because the read control signal read_dqs 34 input from the outside passes through 20 delay elements, so that when the 80 delay elements pass, the delayed clock and the phase difference between the reference clock 360 degrees) when the delayed control clock signal (clk_dqs) 304 is generated and then the delayed control clock signal (clk_dqs) 304 is inverted to generate the inverted control clock signal (clk_dqs_n) 306. The rising edge of the inversion control clock signal clk_dqs_n 306 may not be in a desired position.

Therefore, in order to prevent such a problem from occurring, there is a limitation that the duty of the signal passing through the delay element line must be designed to be ± 5%.

However, there is a problem in that it is not easy to design and layout the delay element line while satisfying both the duty rate and the accuracy of delay of the delay element.

The technical problem to be solved by the present invention, to solve the above disadvantages, by using a delay element line having no constraint on the duty (duty) delay delay control clock signal by 180 degrees out of phase control clock It is to provide a delay compensation circuit for generating a signal.

The present invention, phase detection unit for detecting the phase of the input reference clock signal in order to achieve the above technical problem;

A delay control unit for determining whether to lock from a phase signal output from the phase detection unit and adjusting a delay value of the phase detection unit; And

A delay processing unit for delaying an input signal by receiving a delay value from the delay control unit, comprising a delay processing unit for generating a reverse control clock signal by delaying the delay control clock signal by 180 degrees using a plurality of delay elements. A delay compensation circuit is provided.

Preferably, the delay processing section includes a read processing section for delaying a read control signal to read received data, wherein the read processing section delays the read control signal in accordance with a delay value from the control processing section. A first delay element line having a plurality of delay elements for generating a control clock signal; And a second delay element line including a plurality of delay elements for delaying the delay control clock signal output from the first delay element line by a phase difference of 180 degrees to generate an inversion control clock signal.

Preferably, the number of delay elements used in the second delay element line is one half of the delay elements used in the first delay element line.

Preferably, the read processing unit further includes a data read unit for reading data received using the inversion control clock signal and the delay control clock signal output from the second delay element line.

Preferably, the delay compensation circuit is embedded in an application specific semiconductor (ASIC) or a system on a chip (SOC), and the application specific semiconductor or a system on chip is a dynamic random access memory (DRAM). In the case of being connected to and transmitting data, the delay compensation circuit is used to delay the control signal of the DRAM.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that detailed descriptions of related well-known technologies or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

In the prior art, the duty of the signal passing through the delay element line is a very important factor due to the nature of the delay line. However, according to the present invention, the inversion control clock signal clk_dqs_n is generated using the delay element line, so that the duty characteristic of the delay element line does not have to be ± 5%. Therefore, it is possible to design the delay element line by focusing on the delay value of the delay cell without considering the duty when designing the delay element line, thereby facilitating the design of the delay element line and providing a narrow effective data window. Even with your system, you can capture lead data accurately.

The delay compensation circuit according to the present invention is the same as the delay compensation circuit 1 described above with reference to FIGS.

Referring to FIG. 1, the delay compensation circuit 1 according to the present invention includes a phase detector 10, a delay controller 20, and delay processors 30 and 40. The phase detector 10 detects a phase of the input reference clock signal. The delay controller 20 determines whether to lock from the phase signal output from the phase detector 10 and adjusts the delay value of the phase detector 10.

The phase detector 10 shown in FIG. 2, the delay element 16 shown in FIG. 3, and the delay element line 18 shown in FIG. 4 may be configured in the delay compensation circuit 1 of the present invention. have. Therefore, detailed description is omitted.

The delay processor 30 and 40 according to the present invention includes a read processor 30 and a write processor 40, and receives an encoder signal 24 of a delay control signal from the delay controller 20. The signal is delayed, and the delayed control clock signal is delayed to have a phase difference of 180 degrees using a plurality of delay elements to generate an inverted control clock signal.

7 is a detailed circuit diagram of the read processing unit 30 of the delay compensation circuit 1 according to the present invention.

The delay processing units 30 and 40 include a read processing unit 30 for delaying the read control signal 34 to read received data. The read processing unit 30 includes a first delay element line 320 and a second delay element line 100.

The first delay element line 320 includes a plurality of delay elements, and delays the read control signal read_dqs 34 according to the encoder signal of the delay control signal from the delay control unit 20. delayed_dqs) 322 is generated. The delayed control clock signal delayed_dqs 322 may be used as the delayed control clock signal clk_dqs 304.

The second delay element line 100 includes a plurality of delay elements 110-11n, so that a phase difference of 180 degrees is increased from the delay control clock signal (clk_dqs) 304 output from the first delay element line 320. Delay to generate the inverted control clock signal (clk_dqs_n) 306.

The number of delay elements used in the second delay element line 100 is one half of the number of delay elements used in the first delay element line 320.

The read processing unit 30 also reads data received using the inversion control clock signal 306 and the delay control clock signal 304 output from the second delay element line 100. It includes.

That is, in the related art, only the first delay element line 320 is provided, but the second delay element line 100 is further provided to reduce the burden on the duty of the first delay element line 320. At this time, the number of delay elements constituting the second delay element line 100 for generating the inversion control clock signal (clk_dqs_n) 106 may be 1/2 of the number of delay elements constituting the general delay element line. This is because the second delay element line 100 delays the phase of the delay control clock signal (clk_dqs) 104 only up to 180 degrees.

The present invention is similar to the operation of the prior art. Conventionally, a delayed control clock signal (delayed_dqs) 322 is passed through a buffer 302 (FIG. 5) to generate a delayed control clock signal (clk_dqs) 304, and inverted in the inverter 308 (FIG. 5). (inverting) to generate an inverted control clock signal (clk_dqs_n) 306. However, in order to eliminate the specification burden on the duty rate of the first delay element line 320, the delayed control clock signal delayed_dqs 322 is delayed control clock signal clk_dqs 104. The delayed control clock signal 322 passes through the second delay element line 100 again to be 180 degrees out of phase and has a phase difference of exactly 180 degrees from the delayed control clock signal (clk_dqs) 104. An inversion control clock signal (clk_dqs_n) 106 is generated.

The delay compensation circuit 1 may be embedded in an application specific semiconductor (ASIC) or a system on a chip (SOC), and the application specific semiconductor or the system on chip may be a dynamic random access memory (DRAM). When the data is transmitted and received, the delay control circuit may be used to delay the control signal of the DRAM.

The on-demand semiconductor or system on chip incorporating the delay compensation circuit as described above may be provided in a printer or a multifunction device and used to perform smooth data transmission and reception with a DRAM.

Although the preferred embodiments of the present invention have been described in detail above, those of ordinary skill in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the present invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, by using the present invention, the delay control line signal is further provided to generate the inversion control clock signal, so that the duty of the existing delay device line does not need to be ± 5%. Therefore, when designing the delay element line, the burden on the duty can be reduced, and the delay element line can be effectively designed.

In addition, even when the valid data window is narrow, the delay compensation circuit according to the present invention can be used to accurately capture data by adjusting delay values of control signals related to data transmission.

Therefore, the delay compensation circuit according to the present invention can be designed by focusing on the delay value of the delay element without considering the duty when designing the delay element line.

Claims (5)

A phase detector for outputting a first phase signal representing the phase of the input reference clock signal and a second phase signal representing the phase of the signal delaying the input reference clock signal according to the delay control signal; A delay control unit for adjusting and supplying the delay control signal to the phase detection unit so that phase locking of the first and second phase signals output from the phase detection unit is achieved; And And a delay processing unit for generating a delay control clock signal by delaying an input signal according to the delay control signal from the delay control unit, and generating the inversion control clock signal by delaying the delay control clock signal by 180 degrees. Delay compensation circuit. The apparatus of claim 1, wherein the delay processor comprises a read processor configured to delay a read control signal as the input signal to read received data. The lead processing unit A first delay element line including a plurality of delay elements for delaying a read control signal according to a delay value from the delay control unit to generate a delay control clock signal; And And a second delay element line including a plurality of delay elements for generating an inversion control clock signal by delaying the delay control clock signal output from the first delay element line by 180 degrees. . The method of claim 2, And the number of delay elements used in the second delay element line is one half of the delay elements used in the first delay element line. The method of claim 2, wherein the lead processing unit And a data lead unit configured to read data received using the delay control clock signal and the inversion control clock signal. The method of claim 1, The delay compensation circuit is embedded in an application specific semiconductor (ASIC) or a system on a chip (SOC), and the application specific semiconductor or the system on chip is connected to a dynamic random access memory (DRAM) to provide data. And transmitting and receiving a delay, delaying the control signal of the DRAM using the delay compensation circuit.

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