KR100634951B1 - Display apparatus - Google Patents

Abstract

The present invention provides a display unit having a plurality of display elements arranged in a matrix, a drive voltage generation circuit for generating a drive voltage for driving the display element, and a signal voltage for controlling the amount of current of the drive voltage according to the display data. Pixel lighting for controlling the lighting time of the display element according to the data line driving circuit to be generated, the scan line driving circuit for selecting the display element to be driven, and the distance along the current path from the driving voltage generating circuit to the display element. It includes a control circuit.

Lighting, pixel, driving, light emission

Description

Display device {DISPLAY APPARATUS}

1 is a configuration diagram of a display device of a first embodiment of the present invention.

2 is a block diagram of a display unit 25 of the first embodiment of the present invention.

3 is an operation diagram of each scan line of the scan line drive signal 17 and the pixel lighting control signal 24 of the first embodiment of the present invention;

4A and 4B are conceptual views for explaining current control in the first embodiment of the present invention.

5A to 5D are conceptual views for explaining the current control in the first embodiment of the present invention.

6 is a conceptual diagram for explaining the current control in the first embodiment of the present invention.

7 is an internal configuration diagram of a data line driver circuit 14 of the first embodiment of the present invention.

8 is an operation timing diagram of the lighting start timing shift circuit 123, the lighting end reference timing generation circuit 129, and the lighting end timing shift circuit 131 of the first embodiment of the present invention.

9 is an operation timing diagram of the scanning line lighting termination timing adjustment circuit 137 of the first embodiment of the present invention.

10 shows a first scan line lighting control circuit 143, a second scan line lighting control circuit 145, a third scan line lighting control circuit 147, and a 479 scan line lighting control circuit 149 of the first embodiment of the present invention. Operation timing diagram of the 480th scan line lighting control circuit 151.

11 is a configuration diagram of a display device of a second embodiment of the present invention.

Fig. 12 is a diagram showing the operation of the scan line multiple drive signal 204 and the data line drive signal 15 in each scan line in the second embodiment of the present invention.

Fig. 13 is an internal configuration diagram of a scan line second drive circuit 203 in a second embodiment of the present invention.

Fig. 14 is an operation timing diagram of a scan drive signal, a scan second drive signal, and a scan line multiple drive signal in the second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: vertical sync signal

2: horizontal sync signal

3: data enable signal

4: display data

5: synchronous clock

6: display control unit

7: data line control signal

8: scanning line control signal

9: Save / Read command signal

10: Save / Read Address

11: save data

12: screen storage circuit

13: screen readout data

14: data line driving circuit

15: data line driving signal

16: scan line driving circuit

17: scan line drive signal

18: driving voltage generation circuit

19: driving reference voltage

20: current detection circuit

21: current detection information

22: drive voltage

23: pixel lighting control circuit

24: pixel lighting control signal

25: self-luminous element display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using a self-luminous element represented by a light emitting diode (LED), an organic EL (Electro Luminescence) or the like as a display element.

JP-A-10-223373 draws a display that uniformly distributes the luminance on the screen by drawing the odd-row cathode electrode pattern to one side of the substrate and the even-row cathode electrode pattern to the other side opposite thereto. It is starting.

JP-A-2000-194428 prepares a plurality of constant current sources (for example, five) for driving one organic EL element, selects and controls them, and changes the energized current flowing through the organic EL element, thereby providing each constant current source. Disclosed is a driving apparatus of an organic EL element capable of eliminating a luminance nonuniformity caused by a variation in the variation of the forward voltage of each organic EL element.

JP-A-2000-194428 discloses adjusting the luminance by adjusting the lighting time.

JP-A-2000-187467 detects the current flowing through the organic EL element by the current detection circuit, and controls the next lighting time according to the detected current value, thereby resulting in luminance even if there is a variation or deterioration in the element. Disclosed is that the change can be detected and corrected, and good gradation control can be performed.

US Patent No. 6291942 (JP-A-2001-13903) generates deterioration information on a deterioration state from a current value or time or luminance flowing through a self-luminous display element, and based on the deterioration information, The adjustment of the time width for applying a constant voltage or the time width for not applying is disclosed.

In the invention described in JP-A-10-223373, a row with high brightness and a row with low brightness alternately occur at the end of the screen, and thus, it is considered that the luminance unevenness occurs at the end of the screen. In addition, in the self-luminous element, a current corresponding to luminance flows through a pixel that is lit, so that the amount of power current varies by the number of pixels that are lit. In other words, the degree of deterioration in luminance also varies with the content of the display data.

On the other hand, in the invention described in JP-A-10-223373, the difference in voltage drop between the light emitting dot close to the light emitting dot and the distant light emitting dot occurs in the extraction portion of the electrode pattern is considered. The degree is not considered to the other.

The invention described in JP-A-2000-194428 eliminates luminance unevenness caused by variations in each constant current source and fluctuations in the forward voltage of each organic EL element, and is caused by the voltage drop of the wiring from the current source to the display element. There is no consideration in reducing the luminance nonuniformity by the fall and the change.

JP-A-2000-194428 or JP-A-2000-187467, US Patent No. The invention described in 6291942 (JP-A-2001-13903) corrects a change in luminance due to a change in display element or a deterioration state (change in time), and the voltage drop of the wiring from the current source to the display element is reduced. There is no consideration in reducing the luminance unevenness due to the decrease in luminance and the change caused by the luminance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that reduces a change in luminance due to the arrangement position of display elements.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that reduces a change in luminance caused by a voltage drop in a wiring from a current source to a display element.

In the present invention, the lighting time (drive time) of the display element is controlled in accordance with the distance from the drive voltage generation circuit for generating the drive voltage for driving the display element to the display element.

Since the display elements are arranged in a matrix, the distance from the driving voltage generation circuit to the display elements depends on the arrangement position of the display elements. Therefore, this invention changes the lighting time according to the arrangement position of a display element.

According to the present invention, a change in luminance due to the arrangement position of the display element can be reduced.

According to the present invention, it is possible to reduce the change in luminance due to the voltage drop of the wiring from the current source to the display element.

<Example>

Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

1 is a configuration diagram of a display device of a first embodiment of the present invention. The vertical synchronization signal 1 is a signal of one display period (one frame period), the horizontal synchronization signal 2 is a signal of one horizontal period, and the data enable signal 3 is valid or invalid for the display data 4. It is a signal indicating a period (display valid period). All these signals are input from the outside (for example, a personal computer, etc.) in synchronization with the synchronous clock 5. In the first embodiment, it is assumed that these display data are sequentially transmitted in the raster scan form from one pixel on the upper left side, and one pixel of information consists of four bits of grayscale data. 6 denotes a display control unit, 7 denotes a data line control signal, 8 denotes a scan line control signal, 9 denotes a storage / read command signal, 10 denotes a storage / read address, 11 denotes stored data, Reference numeral 12 denotes a screen storage circuit, and reference numeral 13 denotes screen read data. The display control section 6 is a screen storage circuit (frame memory) 12 capable of storing at least one screen of display data 4 of the display section 25 (described later). 9), the storage / reading address 10 and the storage data 11 are generated. In addition, the display control section 6 generates a storage / read command signal 9 and a storage / read address 10 to read display data for one screen in accordance with the display timing of the display section 25. The screen storage circuit 12 stores the storage data 11 or reads the screen read data 13 in accordance with the storage / read command signal 9 and the storage / read address. The display control unit 6 generates a data line control signal 7 and a scanning line control signal 8 from the screen read data 13. Reference numeral 14 denotes a data line driving circuit, reference numeral 15 denotes a data line driving signal, reference numeral 16 denotes a scan line driving circuit, reference numeral 17 denotes a scan line driving signal, reference numeral 18 denotes a driving voltage generation circuit, and reference numeral 19 denotes a driving reference voltage. , Reference numeral 20 denotes a current detection circuit, reference numeral 21 denotes current detection information, reference numeral 22 denotes a driving voltage, reference numeral 23 denotes a pixel lighting control circuit, reference numeral 24 denotes a pixel lighting control signal, and reference numeral 25 denotes a self-luminous element display. to be. The display unit 25 has a self-light emitting element using a light emitting diode, an organic EL, or the like as a display element. In the display unit 25, a plurality of self-luminous elements (pixels) are arranged in a matrix. Each pixel is applied to the pixel selected by the scan line drive signal 17 output from the scan line driver circuit 16, and the application of the signal voltage according to the data line drive signal 15 output from the data line drive circuit 14, and the pixel. It operates by lighting control of the pixel according to the pixel lighting control signal 24 output from the lighting control circuit 23. Here, the current detection circuit 20 detects the amount of current of the drive voltage 22 and outputs information of the amount of current as the current detection information 21. The pixel lighting control circuit 23 outputs the pixel lighting control signal 24 to control the lighting time of the pixel in accordance with the scanning line control signal 8 and the current detection information 21. The voltage for driving the self-luminous element is supplied as the driving voltage 22. In addition, the scanning line driver circuit 16 and the pixel lighting control circuit 23 may be realized by one LSI chip. In the first embodiment, the display unit 25 has a resolution of 640 x 480 dots. The display unit 25 may adjust the luminance displayed by the self-light emitting device according to the amount of current flowing through the self-light emitting device or the lighting time of the self-light emitting device. As the amount of current flowing through the self-light emitting element increases, the brightness of the self-light emitting element increases. As the lighting time of the self-light emitting element becomes longer, the brightness of the self-light emitting element increases. The data line driving circuit 14 generates a signal voltage in accordance with the display data, and controls the amount of current of the driving voltage supplied to the self-luminous element by the signal voltage.

2 is an internal configuration of the display unit 25 of the first embodiment of the present invention. An example in the case of using an organic EL element as a self-luminous element is shown. In Fig. 2, reference numeral 26 denotes a first data line, reference numeral 27 denotes a second data line, reference numeral 28 denotes a first scanning line, reference numeral 29 denotes a 480th scanning line, reference numeral 30 denotes a first lighting control line, and reference numeral 31 is a 480th lighting control line, 32 is an organic EL driving voltage supply line, 33 is a first thermal organic EL driving voltage supply line, 34 is a second thermal organic EL driving voltage supply line, and 35 is a first A row first column pixel, reference numeral 36 is a first row second column pixel, reference numeral 37 is a 480th row first column pixel, reference numeral 38 is a 480th row second column pixel. The signal voltage is supplied to the pixels in the row selected by the scan line selection voltage flowing through each scan line through the respective data lines, and the pixels to be turned on by the respective lighting control lines are determined, and each column is determined according to the signal voltage. The pixel is turned on by controlling the organic EL driving voltage supplied from the organic EL driving voltage supply line. Although the internal structure of the pixel is shown here only in the first row first column pixel 35, the first row second column pixel 36, the 480th row first column pixel 37, and the 480th row second column pixel. The same configuration also applies to (38). Reference numeral 39 is a pixel driver, 40 is a switching transistor, 41 is a write capacitor, 42 is a drive transistor, 43 is a lighting control switch, and 44 is an organic EL. The pixel driver 39 is for controlling the current flowing through the organic EL 44 in response to the signal voltage. The pixel driver 39 includes a switching transistor 40, a write capacitor 41, and a drive transistor 42. The switching transistor 40 is turned on by the first scanning line 28, accumulates the signal voltage supplied from the first data line 26 in the write capacitor, and flows the driving transistor 42 by the accumulated voltage. Control the amount of current. The current controlled by the driving transistor 42 flows into the organic EL 44 within the lighting time controlled by the lighting control switch 43, so that the organic EL 44 emits light within the lighting time with the luminance corresponding to the amount of current. . In addition, the lighting control switch 43 operates in accordance with whether the control signal is "High" or "Low". Here, when the switch is "High", when the switch is "ON", that is, the current is in a conductive state, and is "Low", It is assumed that the switch is "OFF", that is, the current is stopped. However, it may be reversed.

Since the number of pixels of the display unit 25 is 640 x 480 pixels, 480 scan lines are arranged in the horizontal direction from the first scan line 28 to the 480th scan line 29 in the vertical direction, and the data lines are in the vertical direction. It is assumed that 640 pieces are arranged from the first data line 26 and the second data line 27 to the 640th data line in this horizontal direction. In addition, the organic EL driving voltage supply line 32 is disposed below the display portion 25. In the organic EL driving voltage supply line 32, a line (for example, the first column organic EL driving voltage supply line 33 or the second column organic EL driving voltage supply line 34) in the vertical direction (column direction) is horizontal in the horizontal direction ( It will be described below, 640 being connected in the row direction). Therefore, the driving voltage is higher from the lower side of the display unit 25 via the first column organic EL driving voltage supply line 33 and the second column organic EL driving voltage supply line 34 from the organic EL driving voltage supply line 32. Towards, the pixels are supplied to the pixels in column units (one column unit or multiple column units) of the pixels arranged in a matrix. When the lighting time of the some organic EL 44 is made the same, the display luminance of the pixel located below the column direction (side near the supply point of a driving voltage) becomes relatively high, and the upper side of a column direction (the driving voltage of The display luminance of the pixel located on the side far from the supply point becomes relatively low. Therefore, it is necessary to control the lighting time of the organic EL 44. In addition, the organic EL driving voltage supply line 32 may be disposed above the display unit 25. In this case, the driving voltage is displayed on the display unit 25 from the organic EL driving voltage supply line 32 disposed above via the first column organic EL driving voltage supply line 33 and the second column organic EL driving voltage supply line 34. ) From the upper side to the lower side, the pixels are supplied to the pixels in a column unit (one column unit or a plurality of column units) of the pixels arranged in a matrix. Therefore, in the case where the lighting time of the organic EL 44 is the same and the same luminance is to be displayed on the plurality of pixels, the display luminance of the pixels located above the column direction (side near the supply point of the driving voltage) is It becomes relatively high and the display brightness of the pixel located below the column direction (side far from the supply point of a drive voltage) becomes relatively low. In addition, the organic EL driving voltage supply line 32 is disposed above and below the display unit 25 to supply the driving voltage to the pixels from above the display unit 25 and from below the display unit 25. The case where the driving voltage is supplied to the pixels may be alternately formed in units of columns. The organic EL driving voltage supply line 32 may be disposed on the right side of the display unit 25. In this case, 480 lines in the horizontal direction (for example, the first row organic EL drive voltage supply line or the second row organic EL drive voltage supply line) are connected to the organic EL drive voltage supply line 32 in the vertical direction. In this case, the driving voltage passes from the right side to the left side of the display portion 25 via the first row organic EL driving voltage supply line or the second row organic EL driving voltage supply line from the organic EL driving voltage supply line 32 disposed on the right side. On the other hand, the pixels are supplied in units of rows of pixels arranged in a matrix form (one row unit may be used, or a plurality of rows (for example, two rows or three rows)). Therefore, when the lighting time of the organic EL 44 is the same and the same luminance is to be displayed on the plurality of pixels, the display luminance of the pixels located on the right side of the row direction (side near the supply point of the driving voltage) is It becomes relatively high and the display luminance of the pixel located in the left side (side far from the supply point of a drive voltage) of a column direction becomes relatively low. In addition, the organic EL driving voltage supply line 32 may be disposed on the left side of the display unit 25. In this case, the driving voltage passes from the left side to the right side of the display unit 25 via the first row organic EL driving voltage supply line or the second row organic EL driving voltage supply line from the organic EL driving voltage supply line 32 disposed on the left side. On the other hand, the pixels are supplied in units of rows of pixels arranged in a matrix form (one row unit may be used, or a plurality of rows (for example, two rows or three rows)). Therefore, when the lighting time of the organic EL 44 is the same and the same luminance is to be displayed on the plurality of pixels, the display luminance of the pixels located on the left side (the side close to the supply point of the driving voltage) in the row direction is It becomes relatively high and the display brightness of the pixel located in the right side of the column direction (side far from the supply point of a drive voltage) becomes relatively low. Further, the organic EL driving voltage supply lines 32 are disposed on the left and right sides of the display unit 25 to supply the driving voltage to the pixels from the left side of the display unit 25 and from the right side of the display unit 25. The case where the driving voltage is supplied to the pixels may be alternately formed in units of columns.

3 is a diagram showing an operation of each scan line of the scan line drive signal and the pixel lighting control signal according to the embodiment of the present invention. In Fig. 3, reference numeral 45 denotes a first scan signal, reference numeral 46 denotes a first scan line driving period, reference numeral 47 denotes a second scan signal, reference numeral 48 denotes a second scan line driving cycle, and reference numeral 49 denotes a third scan signal. , Reference numeral 50 denotes a third scan line driving period, reference numeral 51 denotes a first scan line lighting control signal, reference numeral 52 denotes a first scanning line lighting period, reference numeral 53 denotes a second scanning line lighting control signal, and reference numeral 54 denotes a second scanning line. The lighting period, reference numeral 55 denotes the third scan line lighting control signal, and reference numeral 56 denotes the third scan line lighting period. Each scan signal is a signal that is sequentially shifted after the second scan signal 47 ends the first scan signal 45 and the third scan signal 49 ends after the second scan signal 47. . Therefore, the first scanning line driving period 46, the second scanning line driving period 48, and the third scanning line driving period 50 are periods in which signal voltages are written, which is time for writing 480 lines. All of these times are preferably the same time. Each scan line lighting control signal is " High " after rising of the scan signal corresponding to each scan line, and " Low " after an arbitrary period before the next write. The pixel only lights up a period of "High". However, it may be reversed. This period can be set for each scan line. Therefore, the first scanning line lighting period 52, the second scanning line lighting period 54, and the third scanning line lighting period 56 are all different periods. In addition, the scanning signal may be sequentially shifted in units of one scan line, or may be sequentially shifted in units of plural (for example, 2 or 3) scan lines. In addition, one or more scanning lines may be shifted at intervals.

Fig. 4A is a configuration diagram of the driving transistor and the organic EL only in the first embodiment of the present invention, and Fig. 4B is a diagram showing a relationship between signal voltage and current. Reference numeral 57 denotes an organic EL driving voltage, reference numeral 58 denotes a write voltage, reference numeral 59 denotes a source-gate voltage, reference numeral 60 denotes a source-drain voltage, and reference numeral 61 denotes an organic EL current. The driving transistor 42 controls the organic EL current 61 from the relationship between the source-gate voltage 59 and the source-drain voltage 60 determined from the organic EL voltage 57 and the write voltage 58. Thus, the organic EL 44 is emitted. Reference numeral 62 denotes a driving transistor voltage-current characteristic, reference numeral 63 denotes an organic EL voltage-current characteristic, reference numeral 64 denotes an organic EL operating point, and the driving transistor voltage-current characteristic 62 is a source of the driving transistor 42 on the horizontal axis. By taking the value of the inter-drain voltage 60 and the current flowing in the drive transistor 42 for the voltage on the vertical axis, the characteristic for any constant source-gate voltage 59, i. It is shown. The organic EL voltage-current characteristic 63 is an organic EL that flows at that voltage with respect to the organic EL voltage derived from the source-drain voltage 60 on the horizontal axis when a certain organic EL driving voltage 57 is provided. The value of the current 61 is taken along the vertical axis. Therefore, the organic EL operating point 64 serving as the intersection of these two lines represents the value of the organic EL current 61 flowing when a certain signal voltage 58 is provided under the condition of the organic EL driving voltage 57. have. In FIG. 4B, in the graph of the source-drain voltage characteristic of the driving transistor 42 with respect to a signal voltage 58, it is represented by the difference between the organic EL driving voltage 57 and the source-drain voltage 60 of the driving transistor. The graphs of the organic EL voltage-current characteristics, which are the characteristics of the organic EL current 61, with respect to the voltage with respect to the organic EL to be superimposed. From the intersection of these two characteristics, the value of the organic EL current 61 with respect to the conditions of the organic EL driving voltage 57 and the signal voltage 58 becomes Ia.

Reference numeral 70 denotes a driving transistor voltage-current characteristic at low organic EL driving voltage, reference numeral 71 is an organic EL voltage-current characteristic at low organic EL driving voltage, and reference numeral 72 is an organic EL operating point at low organic EL driving voltage. When the organic EL driving voltage 57 is lowered, the source-gate voltage 60 is lowered, so that the driving transistor voltage-current characteristic 62 is the same as the driving transistor voltage-current characteristic 70 at the low organic EL driving voltage. Change. Similarly, when the organic EL driving voltage 57 is lowered, the organic EL voltage for the source-drain voltage of the same value is lowered, so that the organic EL voltage-current characteristic 62 is the organic EL voltage- at the low organic EL driving voltage. It changes like the current characteristic 71. From the organic EL operating point 72 at the intersection of the low organic EL driving voltage, the organic EL current 61 is shown to decrease from Ia to Ib. Therefore, here, it is shown that the drop of the organic EL driving voltage causes the reduction of the organic EL current, that is, the decrease of the luminance.

Fig. 5A is a block diagram of a supply line of an organic EL driving voltage and a pixel in the case of the back display of the first embodiment of the present invention. Fig. 5B shows the relationship between the pixel position (distance from the feeding point to the pixel) and the driving voltage in the case of the white display of the first embodiment of the present invention. Fig. 5C is a block diagram of the supply line and the pixel of the organic EL driving voltage in the case of halftone display (gradation between white and black) of the first embodiment of the present invention. Fig. 5D shows the relationship between the pixel position and the driving voltage in the case of halftone (gradation between white and black) display of the first embodiment of the present invention. The distance from the power feeding point to the pixel is, for example, of the organic EL driving voltage supply line 32 and the first column organic EL driving voltage supply line 33 from the driving voltage generation circuit 18 to the first row first column pixels. Length. Reference numeral 65 denotes the second row first column pixel, reference numeral 66 denotes the first row organic EL driving voltage, reference numeral 67 denotes the second row driving voltage, reference numeral 68 denotes the 480th row driving voltage, and the organic EL driving voltage is The first row of organic EL driving voltages are provided to the first row of pixels 35 through the first column organic EL driving voltage supply line 33 from the 480th row first column pixel 36 to the pixels on the first column. 66 is supplied, the second row organic EL driving voltage 67 is supplied to the second row first column pixel 65, and the 480th row organic EL driving voltage 68 is supplied to the second row first column pixel 65. Each is supplied. Reference numeral 69 denotes a pixel position-driving voltage characteristic, which takes the pixel position represented by the distance from the feed point (the supply point of the driving voltage) on the horizontal axis, and the value of the organic EL driving voltage supplied to the pixel at that position on the vertical axis. Will be taken. Since the organic EL driving voltage supply line 33 has wiring resistance and the distance from the feeding point becomes longer, the resistance becomes larger, indicating that the organic EL driving voltage is falling. That is, since the pixels arranged in the vertical direction are connected to one organic EL driving voltage supply line 33, voltage drop occurs due to wiring resistance in the lowermost pixel and the uppermost pixel, and the driving voltage supplied to each pixel is The pixel position-driving voltage characteristic 69 is the same.

Reference numeral 73 denotes a feed drain current when displaying white, reference numeral 74 denotes a row 480 pixel current when displaying white, reference numeral 75 denotes a second row pixel current when displaying white, reference numeral 76 denotes a first row pixel current when displaying white, Reference numeral 77 denotes a pixel position-drive voltage characteristic when displaying white. Since the organic EL current flows through the pixel during the white display, the power supply drain current 73 becomes the maximum during the white display. Since the first thermal organic EL driving voltage feed line 33 has wiring resistance, the larger the current flowing, the larger the voltage drop. Accordingly, the pixel position-drive voltage characteristic 77 at the time of the back display becomes a characteristic having a large inclination as shown in FIG. 5B, and the first row pixel current far from the 480 row pixel current 74 close to the feeding point. This indicates that 76 is small, that is, the display luminance is lowered. Reference numeral 78 denotes a feed drain current when halftone is displayed, reference numeral 79 denotes the 480th row pixel current when halftone is displayed, reference numeral 80 denotes the second row pixel current when halftone is displayed, and reference numeral 81 is the first when halftone is displayed. Row pixel current, reference numeral 82, is a pixel position-drive voltage characteristic in halftone display. Since the current flowing through the organic EL element is small during halftone display, the feed drain current 78 in halftone display is smaller than the feed drain current 73 in white display. Since the first thermal organic EL drive voltage feed line 33 has wiring resistance, the voltage drop decreases when the current flowing therein decreases. Accordingly, the pixel position-driving voltage characteristic 82 at halftone display becomes a characteristic having a small slope as shown in FIG. 5D, so that the halfway half of the pixel current 78 at the halftone display near the feed point The first row pixel current 81 shows no difference, i.e., the display brightness does not change much. 5B and 5D, since the display brightness of the white display is higher than that of the black display, the voltage drop rate of the white display side is larger than that of the black display, and the voltage drop rate also increases.

FIG. 6 is a diagram showing the concept of making the display luminance almost constant (uniform) by the light emission time corresponding to the pixel position in the first embodiment of the present invention. FIGS. It is a figure in the case where voltage drop is large like a display. 6 (d) to (f) are diagrams in the case where the voltage drop is small, such as all pixel halftone display and black display. In FIG. 6A, when the pixel is the top of the screen far from the organic EL driving voltage feeding point, when FIG. 6B is near the center of the screen closer than FIG. 6A, C is the closest bottom of the screen. The case is shown. Reference numeral 83 denotes a pixel position-organic EL current characteristic when displaying white. Since the current is proportional to the voltage, the current is the same as the pixel position-driving voltage characteristic shown in FIG. 84 is the top organic EL current when displaying white, 85 is the top lighting period when displaying white, 86 is the top lighting effective brightness when displaying white, and 87 is the central organic EL current when displaying white, and 88 Is the center lighting period in the white display, reference numeral 89 is the center lighting effective luminance in the white display, reference numeral 90 is the lowest organic EL current in the white display, reference numeral 91 is the lowest lighting period in the white display, and reference numeral 92 is the white display. The lowest lit effective luminance. As shown in Fig. 6A, since the top organic EL current 84 is small at the top of the screen at the time of white display, the top lighting period 85 is lengthened at the time of white display, and the back display as shown in Fig. 6C. Since the lowermost organic EL current 90 is large, the lowermost lighting period 91 during white display is shortened. Thus, the area where the top organic EL current 84 at the time of white display is multiplied by the top lighting period 85 at the time of white display, the top lit effective luminance 86 at the time of white display, the bottom organic EL current 90 at the time of white display, and The area of the bottom display period multiplied by the lowest lighting period 91 at the time of white display is made equal to the lowest lighting effective luminance 92 at the time of white display. In addition, as the display from black to white (as the gradation value of the display data increases), that is, as the display brightness increases, the ratio of the voltage drop (tilt) and the voltage drop increase, so that the lighting time is increased. It is desirable to increase the size. In addition, the display luminance can be estimated from the current amount of the organic EL driving voltage.

FIG. 6 (d) shows the case where the pixel is near the top of the screen far from the organic EL driving voltage feeding point, and FIG. 6 (f) shows the case where FIG. 6 (e) is near the center of the screen closer than FIG. 6 (d). The bottom of the nearest screen is shown. Reference numeral 93 is a pixel position-organic EL current characteristic in halftone display. Since the current is proportional to the voltage, the current is the same as the pixel position-driving voltage characteristic shown in FIG. 94 is the top organic EL current when halftone is displayed, 95 is the top lighting period when halftone is displayed, 96 is the top lighting effective brightness when halftone is displayed, and 97 is the center organic EL when halftone is displayed. Current, 98 is the center lighting period when halftone is displayed, 99 is the middle light when halftone is displayed Effective luminance, 100 is the lowest organic EL current when halftone is displayed, 101 is the lowest light when halftone is displayed Period 102 is the lowest lit effective luminance at halftone display. Since the difference between the top organic EL current 94 in halftone display and the bottom organic EL current 100 in halftone display is small, accordingly, the top lighting period 95 in halftone display and the bottom lighting period in halftone display ( 101, the difference between the top organic EL current 94 at halftone display and the top lighting period 95 multiplied at halftone display, the top lit effective luminance 96 at halftone display, and halftone display at halftone display. The lowermost lit effective luminance 102 is equal when the halftone display is the area obtained by multiplying the lowest organic EL current 100 by the lowest lit period 101 during halftone display.

The display controller 6 includes a storage controller and a display control signal generator. The storage control unit generates a storage / read command signal 9 and a storage / read address 10 to output display data in accordance with the display timing of the display unit 25, and the screen reading data (from the screen storage circuit 12) 13, the storage / read command signal 9, the storage / read address 10, and the storage data 11 are generated in order to store the display data 4. The display control signal generation unit generates a data read instruction signal in accordance with the timing of generating the display timing of the display unit 25, matches the read display display data, and provides data for the data line driver circuit 14 to operate. A data line driving signal 7 is output as a timing signal, and a scanning line driving signal 8 including a timing signal for operating the scanning line driving circuit 16 is generated. The display control signal generator 104 includes a basic clock generation circuit, a horizontal counter, a vertical counter, a stored data read timing control circuit, a data timing adjustment circuit, a data line drive control circuit, a scan line drive control circuit, A scan start signal and a scan shift clock control circuit. In order to display the display unit 25, the base clock generation circuit generates a base clock that is the basis of a control signal to be generated later. The horizontal counter continues counting up within one horizontal period in accordance with the basic clock and outputs it as a horizontal count value. When the horizontal counter ends, the horizontal counter resets the horizontal count value and outputs vertical count timing. The vertical counter continues counting up within one frame period in accordance with the vertical count timing and outputs it as a vertical count value. When the one frame period ends, the vertical counter resets the vertical count value. The timing control circuit generates a data read instruction signal to read the display data stored in the storage circuit 12 in accordance with the values of the horizontal count value and the vertical count value. The data line driving control circuit latches the data line driving data from the horizontal count value and the vertical count value to the data line driving circuit 14 to generate a data line driving timing signal for outputting. The data timing adjustment circuit adjusts the timing of the display display data from the horizontal count value and the vertical count value to match the timing of the data line driving timing signal and outputs the data as the data line driving data. The data line driving signal 7 is constituted by the basic clock, the data line driving data, and the data line driving timing signal. The scan line drive control circuit generates a scan start signal indicating the head in one frame from the horizontal count value. The scan shift clock control circuit generates a scan shift clock for the scan line driver circuit 16 to shift the scan start signal to a different scan line every one horizontal from the vertical count timing. The scan line control signal 8 is constituted by the scan start signal and the scan shift clock.

7 is an internal configuration diagram of the pixel lighting control circuit 23 of the first embodiment of the present invention. Reference numeral 123 denotes a lighting start timing shift circuit, reference numeral 124 denotes a first scanning line lighting starting timing signal, reference numeral 125 denotes a second scanning line lighting starting timing signal, reference numeral 126 denotes a third scanning line lighting starting timing signal, and reference numeral 127 A 479th scanning line lighting start timing signal and the code | symbol 128 are the 480th scanning line lighting starting timing signal. The lighting start timing shift circuit 123 shifts the scan start signal 120 in accordance with the scan shift clock, and indicates the shift start timing of each scan line, and the 480th scan line from the first scan line light start timing signal 124. 480 outputs of the lighting start timing signal 128 are assumed. In addition, in the first embodiment, the lighting start timing is made simultaneous with the timing of the scan start. However, after the scan start timing, there may be a lighting start timing. Reference numeral 129 denotes a lighting termination reference timing generation circuit, and reference numeral 130 is a lighting termination reference timing signal. The lighting termination reference timing generation circuit 129 generates the lighting termination reference timing signal 130 which becomes the reference timing of the lighting termination from the scanning start signal 120. Here, the scan start signal 120 is latched by an arbitrary number with the scan shift clock 122, which will be described below. Reference numeral 131 denotes a lighting termination timing shift circuit, reference numeral 132 denotes a first scanning line lighting termination reference timing signal, reference numeral 133 denotes a second scanning line lighting termination reference timing signal, reference numeral 134 denotes a third scanning line lighting termination reference timing signal, and reference. Reference numeral 135 denotes a 479 scanning line lighting termination reference timing signal, and reference numeral 136 denotes a 480 scanning line lighting termination reference timing signal. The lighting termination timing shift circuit 131 shifts the lighting termination reference timing signal 130 in accordance with the scan shift clock 122 to indicate the reference of the termination timing of the lighting of each scanning line, and the first scanning line lighting termination reference timing. From the signal 132, 480 outputs of the 480th scanning line lighting termination reference timing signal 136 are set. Reference numeral 137 denotes a scanning end lighting timing adjustment circuit, reference numeral 138 denotes a first scanning line lighting ending timing signal, reference numeral 139 denotes a second scanning line lighting ending timing signal, reference numeral 140 denotes a third scanning line lighting ending timing signal, reference numeral Reference numeral 141 denotes a 479 scan line turn-on timing signal, and reference numeral 142 denotes a 480 scan line turn-on timing signal. The scanning end lighting timing adjustment circuit 137 arbitrarily adjusts the lighting end reference timing signals 132 to 136 of each scanning line for each scanning line, and terminates the 480th scanning line lighting from the first scanning line lighting end timing signal 138. The signal is output as the timing signal 142. The adjustment amount of timing can be set independently for each scanning line, and each adjustment amount is made variable according to the current detection information 21. Reference numeral 143 denotes a first scanning line lighting control circuit, reference numeral 144 denotes a first scanning line lighting control signal, reference numeral 145 denotes a second scanning line lighting control circuit, reference numeral 146 denotes a second scanning line lighting control signal, reference numeral 147 denotes a third Scanning line lighting control circuit, reference numeral 148 is a third scanning line lighting control signal, reference numeral 149 is a 479 scanning line lighting control circuit, reference numeral 150 is a 479 scanning line lighting control signal, reference numeral 151 is a 480th scanning line lighting control circuit, reference Reference numeral 152 denotes a 480th scan line lighting control signal. Each scanning line lighting control circuit generates each scanning line lighting control signal indicating a lighting period from the lighting starting timing signal and the lighting ending timing signal inputted to each. Here, it is assumed that the lighting control signal is a signal which becomes "High" for the period from the lighting start timing to the lighting termination timing, and will be described below. Therefore, the pixel lighting control circuit 23 controls the "ON" time of the lighting control switch 43. However, the pixel lighting control circuit 23 may control the "OFF" time of the lighting control switch 43. In this case, the lighting control signal becomes "High" for a period from the lighting termination timing to the lighting starting timing.

8 is a diagram showing the operation timings of the lighting start timing shift circuit 123, the lighting end reference timing generation circuit 129, and the lighting end timing shift circuit 131 of the first embodiment of the present invention. Each scan line lighting start timing signal indicates that the scan start signal 120 is shifted once in accordance with the scan shift clock 122. In addition, the lighting termination reference timing signal 130 is a signal obtained by shifting the scan start signal 120 by the number of clocks of an arbitrary scan shift clock 122, and once shifted according to the scan shift clock 122. The signal is made from the first scanning line lighting termination reference timing signal 132 to the 480th scanning line lighting termination reference timing signal 136.

Fig. 9 is a diagram showing the operation timing of the scanning line lighting termination timing adjustment circuit 137 of the first embodiment of the present invention. Reference numeral 153 denotes the first scanning line lighting termination timing adjustment amount, reference numeral 154 denotes the second scanning line lighting termination timing adjustment amount, reference numeral 155 denotes the third scanning line lighting termination timing adjustment amount, and reference numeral 156 denotes the 479 scanning line lighting termination timing adjustment. Amount. The scanning line lighting end timing signals 138 to 142 indicate that the scanning line lighting end timing signals 132 to 136 are generated by delaying the respective timing adjustment amounts 153 to 156 respectively.

10 shows a first scan line lighting control circuit 143, a second scan line lighting control circuit 145, a third scan line lighting control circuit 147, a 479 scan line lighting control circuit 149 of a first embodiment of the present invention. The operation timing of the 480th scan line lighting control circuit 151 is shown. Each scan line lighting control signal indicates that the signal becomes "High" from the rise of each scan line lighting start timing signal to the rise of each scanning line lighting end timing signal.

Equations 1 to 3 are the first scan line lighting end timing adjustment amount 153, the second scan line lighting end timing adjustment amount 154, the third scan line lighting end timing adjustment amount 155, and 479 described in FIG. 9. It is an equation for calculating the scan line lighting end timing adjustment amount 156.

However, V _EL is the organic EL driving voltage drop from the bottom to the top, R is the wiring resistance from the bottom to the top, and I _EL is the organic EL driving current.

However, V _D is an organic EL driving voltage and C _EL is an organic EL driving voltage drop rate.

Where T _w n is the nth scan line lighting termination timing adjustment amount, N is the scanning line number, Tf is the scanning line driving period, and Tb is the lighting termination reference timing delay amount.

In the equations (1) to (3), the organic EL driving voltage V _EL and the wiring resistance R are set in advance, and the organic EL driving current I _EL is obtained from the voltage detection information 21, whereby each scan line lighting termination timing adjustment amount T _w Determination of n is shown.

As described above, in the first embodiment of the present invention, the change in luminance due to the voltage drop caused by the wiring resistance can be suppressed by detecting the amount of current of the organic EL driving voltage and reflecting the information in the pixel lighting control.

Hereinafter, the pixel lighting control in the first embodiment will be described using FIGS. 1 to 10 and Equations 1 to 3. FIG.

First, the flow of display data will be described with reference to FIG. 1. In FIG. 1, the display control unit 6 temporarily stores the display data 4 as the storage data 11 in the screen storage circuit 12 for one screen. Then, in accordance with the display timing of the display section 25, the display data is read from the screen storage circuit 12 as the screen read data 13 to generate a data line drive signal 7 and a scan line control signal 8. . Detailed description will be described later. The screen storage circuit 12 is used when the display data 4 normally input and the display resolution and timing of the display unit 25 are different, and thus may be omitted when the timings are exactly the same. The data line driving circuit 14 latches the data line driving signal 7 including four bits of gray scale information for one line (may be a plurality of lines), and a signal voltage for displaying pixels of the display unit 25. Is converted to and output as the data line driving signal 15. Detailed description will be described later. The scan line driver circuit 16 outputs the scan line drive signal 17 to sequentially select the scan line of the display unit 25. Detailed description will be described later. The driving voltage generation circuit 18 generates the driving reference voltage 19 as a reference for generating the driving voltage for turning on the organic EL, and the current detection circuit 20 generates the organic EL driving voltage 22. In addition, the current flowing when the organic EL driving voltage 22 is supplied is detected, and the current detection information 21 representing the current amount as digital data is output. In the first embodiment, the current detection circuit 20 is formed after the driving voltage generation circuit 18 and before the display unit 25 (between the driving voltage generation circuit 18 and the display unit 25). Although the organic EL voltage driving line (for example, the first column organic EL voltage driving line 33 or the second column organic EL voltage driving line 34) of each column in the display unit 25 may be formed, The opposite electrode side of each pixel, that is, the side from which the current flows out of the pixel (the exit from the display portion 25 may be used), and the organic EL voltage driving line (for example, the first column organic EL in each column in the display portion 25). The voltage driving line 33 or the second thermal organic EL voltage driving line 34 may be formed), and the installation position is not limited as long as it is on a supply line of the organic EL driving voltage. In the case where the organic EL voltage driving lines are formed in units of rows, the current detection circuit 20 may include organic EL voltage driving lines (for example, the first row of organic EL voltage driving lines) in each column of the display unit 25. Second row organic EL voltage driving lines). The pixel lighting control circuit 23 generates a pixel lighting control signal 24 for controlling the switches formed in the pixels of the display unit 25 for each scanning line. Detailed description will be described later. The display unit 25 lights the pixels on the scan line selected by the scan line drive signal 17 in accordance with the signal voltage of the data line drive signal 15 and the pixel lighting control signal 24. Detailed description will be described later.

The detail of the lighting operation of the display part 25 of FIG. 1 is demonstrated using FIG. In FIG. 2, when the scan line selection voltage is supplied through the first scan line 28, the switch transistor 40 is turned on to write the signal voltage of the data through the first data line 26. Accumulates in the drive transistor 42 and operates as a transistor for controlling the current flowing through the organic EL 44. The current according to the voltage-current characteristic of the driving transistor 42 is induced through the lighting control switch 43 which performs "on" and "off" operations according to the lighting control signal supplied through the first lighting control line 30. By flowing to the EL 44, the organic EL 44 emits light. Here, the lighting control switch 43 is expressed in the form of a switch, but is generally composed of a MOS transistor. However, as long as it functions as a switch, the realization circuit is irrelevant.

3, the lighting control operation in the order of the scanning lines will be described. In Fig. 3, when each scan signal is "High", each scan line is selected, and the signal voltage is sequentially written from the first scan line. After the pixel writes the signal voltage, the pixel turns on during the period in which each pixel lighting control signal is "High".

Next, the operation | movement of the pixel lighting control circuit 23 is demonstrated using FIG. 7 thru | or 10. FIG. In FIG. 7, the lighting start timing shift circuit 123 shifts the scan start signal 120 by one clock in accordance with the scan shift clock 122, as shown in FIG. ) Is outputted as the 480th scanning line lighting start timing signal 128. Here, in FIG. 8, the first scan line lighting start timing signal 124 is set to the same timing as the scan start signal 120, but it is not necessary to have the same timing, and the 480th scanning line is obtained from the first scan line lighting start timing signal 124. As long as the phase to the lighting start timing signal 128 is shifted by one clock of the scan shift clock 122 as shown in FIG. Therefore, if only this phase relationship is maintained, the structure of the lighting start timing shift circuit 123 is not limited, either. As shown in FIG. 8, the lighting termination reference timing generation circuit 129 generates the lighting termination reference timing signal 130, which is a signal obtained by delaying the "High" portion of the scanning start signal 120 by an arbitrary period. Arbitrary periods will be described later. As shown in FIG. 8, the lighting termination timing shift circuit 131 shifts the lighting termination reference timing signal 130 by one clock in accordance with the scan shift clock 122 to thereby turn on the first scanning line lighting termination reference timing signal 132. 480 are output as the 480th scanning line lighting termination reference timing signal 136 from FIG. Here, in FIG. 8, the first scan line lighting termination reference timing signal 132 is set to the same timing as the lighting termination reference timing signal 130. However, the first scanning line lighting termination reference timing signal 132 is not necessarily the same timing. The phase from the 480th scan line lighting termination reference timing signal 136 may be shifted by one clock of the scan shift clock 122 as shown in FIG. 8. Therefore, if only this phase relationship is maintained, the structure of the lighting termination timing shift circuit 131 is not limited, either. As shown in FIG. 9, each of the scanning line lighting termination timing adjusting circuits 137 delays each of the scanning line lighting termination reference timing signals 132 to 136 by a different timing adjustment amount for each scanning line, so that the first scanning line lighting ending timing signal ( 138 is output as the 480th scan line lighting end timing signal 142. The timing adjustment amount is determined according to the current detection information 21, but the detailed description will be described later. Finally, the first scan line lighting control circuit 143, the second scan line lighting control circuit 145, the third scan line lighting control circuit 147, the 479 scan line lighting control circuit 149, and the 480th scan line lighting control circuit ( As shown in FIG. 10, the first scan line lighting up from the rising of each scan line lighting start timing signal 124 to 128 to "High" from the rising of each scanning line lighting ending timing signal 138 to 142 is turned on. The control signal 144, the second scanning line lighting control signal 146, the third scanning line lighting control signal 148, the 479th scanning line lighting control signal 150, and the 480th scanning line lighting control signal 152 are generated. The above configuration is an example for generating each scan line lighting control signal, and the circuit configuration is not limited as long as it is each scanning line lighting control signal that becomes "High" for a different period for each scanning line shown in FIG. In this case, 480 scanning line circuits are formed, but by changing the number according to the resolution, it is possible to cope with displays of all resolutions.

Finally, an example is shown regarding the timing adjustment amount. In the equations (1) to (3), the wiring resistance R, the organic EL driving voltage V _D , and the scanning line driving period Tf are found in the design stage. Then, by recognizing the value of the organic EL current I _EL from the current detection information 21, the nth scan line lighting termination timing adjustment amount T _w n is derived. Therefore, in Fig. 12, the lighting termination reference timing signal 130 is conditional not to exceed the scan line driving period Tf even if a delay of T _w n is applied when n = 1 where T _w n becomes the maximum. The position n of the scanning line coincides or is proportional to the distance between the feeding point and the pixel. Therefore, the lighting termination timing adjustment amount is proportional to the distance between the organic EL current I _EL and the feeding point and the pixel. Since the lighting start timing is proportional to the scan line driving period Tf, the lighting time of the organic EL is proportional to the distance between the organic EL current I _EL and the feeding point and the pixel. In addition, since the lighting time of the organic EL may be controlled, the lighting state of one pixel in one frame period may be divided into plural. In this case, there are a plurality of lighting start timings and lighting end timings of one pixel in one frame period.

In addition, instead of detecting the current amount of the driving voltage, the display brightness of the pixel may be measured, and the timing adjustment amount may be set according to the display brightness. By providing a luminance measuring circuit for measuring display luminance, the display luminance for each pixel on the screen is measured. Alternatively, the luminance measuring circuit may calculate display luminance for each pixel, every column of pixels, or every row of pixels from the grayscale data of the display data.

In addition, although the case where the feeding of the organic EL driving voltage from the lower side of the screen has been described here, in the case where the feeding points of the driving voltages are different or there are a plurality, the timing adjustment amount may be set accordingly. That is, the longer the distance between the pixel and the feeding point of the driving voltage (the farther the pixel is from the feeding point), the longer the lighting time of the organic EL 44 of the pixel is. In the first embodiment, since the feed point of the driving voltage is located below the display portion 25, the lighting time of the organic EL 44 is lengthened as the display portion 25 goes from the lower side to the upper side. In the first embodiment, when the power supply point of the driving voltage is located above the display unit 25, the lighting time of the organic EL 44 is lengthened as it goes from the upper side to the lower side of the display unit 25. In the first embodiment, when the power supply point of the driving voltage is located on the right side of the display portion 25, the lighting time of the organic EL 44 is lengthened as it goes from the right side of the display portion 25 to the left side. In the first embodiment, when the power supply point of the driving voltage is located on the left side of the display portion 25, the lighting time of the organic EL 44 is lengthened as it goes from the left side to the right side of the display portion 25. However, in the organic EL 44 of adjacent pixels, the difference in voltage drop is small, and therefore, the lighting time may be controlled in units of plural (for example, 2 or 3) pixels. That is, the lighting time is the same between the plurality of pixels. For example, when the driving voltage is supplied in units of columns, the lighting time is controlled in units of pixels belonging to adjacent rows. In addition, when the driving voltage is supplied in units of rows, the lighting time is controlled in units of pixels belonging to adjacent columns. As a result, the control of the lighting time of the organic EL 44 is simplified. According to the first embodiment of the present invention, the pixel lighting time can be controlled in response to the voltage drop according to the pixel position and the driving power supply voltage current amount, and the luminance of the same brightness or the same display data on the screen can be controlled. Demonstrate the effect of reducing.

Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.

11 is a configuration diagram of a display device of a second embodiment of the present invention. The same reference numerals as in the first embodiment of the present invention have the same functions and functions as the first embodiment of the present invention. Reference numeral 201 denotes a multiple display control unit, and reference numeral 202 denotes a scan line second control signal. As in the first embodiment, the display control unit 202 has a data line control signal 7, a scan line control signal 8, a storage / read command signal 9, a storage / read address 10, and storage data 11 Is generated, and at the timing corresponding to the current detection information 21, the scan line second control signal 202 for writing the black display after the normal display data writing is generated. Reference numeral 203 denotes a scan line second control circuit, reference numeral 204 denotes a scan line multiple driving signal, and reference numeral 205 denotes a display unit. The scan line second control circuit 203 matches the scan line drive signal corresponding to the scan line second control signal 202 with the scan line drive signal 17 and outputs it as the scan line multiple drive signal 204. The first multiple scan line 206 and the second multiple scan line 207 perform two scans within one display period.

Fig. 12 is a diagram showing the operation of each scan line of the scan line multiple drive signal 204 and the data line drive signal 15 of the second embodiment of the present invention. Reference numeral 208 denotes a first multi-scanning signal, reference numeral 209 denotes a first scanning line display period, reference numeral 210 denotes a first scanning line black display period, reference numeral 211 denotes a second multiple scanning signal, reference numeral 212 denotes a second scanning line display period. 213 is a second scanning line black display period, 214 is a third multiple scanning signal, 215 is a third scanning line display period, 216 is a third scanning line black display period, and 217 is a 480 multiple The scanning signal, 218 is the 480th scan line display period, and 219 is the 480th scan line black display period. Each multi-scan signal is a signal which, after normal display data writing, is appended with a pulse for black data writing to generate a plurality of times (for example, two times) of pulses within one display period. This black data write is referred to as scanning second drive here. Reference numeral 220 denotes first scan line write data, reference numeral 221 denotes second scan line write data, reference numeral 222 denotes third scan line write data, reference numeral 223 denotes 480 scan line write data, and reference numeral 224 denotes black write data. After each scan line write, by using the data line drive signal as the black write data 224, black data write is performed in accordance with the second pulse and the scan second drive timing of each multiple scan signal. By adjusting the timing of this second pulse for each scan line, the same effect as adjusting the pixel lighting period in the first embodiment can be obtained. In other words, the period in which the black data is written has substantially the same function as the unlit period of the organic EL in the first embodiment. In addition, before writing normal display data, black data may be written or a plurality of black data may be written within one frame period.

An internal configuration of the multiple display control unit 201 includes a storage control unit and a multiple display control signal generation unit. In addition to generating the data line control signal 7 and the scan line control signal 8 as in the first embodiment, the multiple display control signal generator generates a scan line agent for generating the scan line driving timing for black data writing in FIG. The two control signals 202 are generated with reference to the current detection information 21. The multi display control signal generator 225 includes a basic clock generation circuit, a horizontal counter, a vertical counter, a data timing adjustment circuit, a data line driving control circuit, a scan line driving control circuit, a scan shift clock control circuit, a scan line second driving control circuit, And a scanning second shift clock control circuit. The scan line second drive control circuit generates a scan second start signal indicating the timing of the scan second drive from the horizontal count value 110. The scan second shift clock control circuit determines the scan-line shift amount of the scan second start signal from the current detection information 21, and generates a scan second shift clock having the shift amount as one cycle. The scan second start signal and the scan second shift clock constitute a scan line second control signal.

12 is an internal configuration of a scan line second drive circuit 203 in the embodiment of the present invention. Reference numeral 230 denotes a scan second start signal shift circuit, reference numeral 231 denotes a first scan line second driving timing signal, reference numeral 232 denotes a second scan line second driving timing signal, and reference numeral 233 denotes a third scan line second driving timing signal. Reference numeral 234 denotes a 479th scan line second driving timing signal, and reference numeral 235 denotes a 480th scan line second driving timing signal. The scan line second start signal shift circuit 230 shifts the scan second start signal 227 in accordance with the scan second shift clock 229, and indicates the second driving timing of each scan line by shifting the scan result. 480 pieces are output from the second drive timing signal 231 as the 480th scan line second drive timing signal 235. Reference numeral 236 denotes a first scan line driving signal, reference numeral 237 denotes a second scan line driving signal, reference numeral 238 denotes a third scan line driving signal, reference numeral 239 denotes a 479 scan line driving signal, and reference numeral 240 denotes a 480 scan line driving signal. This is a signal of each scan line of the scan line drive signal 17. Reference numeral 241 denotes a first scan line overlapping circuit, reference numeral 242 denotes a first scan line multiple driving signal, reference numeral 243 denotes a second scan line overlapping circuit, reference numeral 244 denotes a second scan line multiple driving signal, and reference numeral 245 denotes a third scan line overlapping. Circuit, reference numeral 246 denotes a third scanning line multiple driving signal, reference numeral 247 denotes a 479 scanning line overlapping circuit, reference numeral 248 denotes a 479 scanning line multiple driving signal, reference numeral 249 denotes a 480th scanning line overlapping circuit, reference numeral 250 denotes a 480th Scan line multiple drive signal. Each scan line overlapping circuit superimposes each scan line drive signal and the scan line second drive signal and outputs each signal as each scan line multiple drive signal.

12 is a diagram illustrating operation timings of a scan drive signal, a scan second drive signal, and a scan line multiple drive signal. Similarly to the first embodiment, in order to lengthen the display period by the scanning line on the upper part of the screen, the frequency of the scanning second shift clock 229 is made earlier than the scanning shift clock 122, so that the scanning second drive signal output to each scanning line is output. The shift amount of becomes small, and the display period of a 1st scanning line becomes longest.

Hereinafter, multiple scanning control in the second embodiment will be described with reference to FIGS. 11 to 14.

In FIG. 11, the multi-display control unit 201 performs the screen save operation, the data line control signal generation operation, and the scan line control signal generation operation in the same manner as in the first embodiment. After the control, a scan second control signal 202 for adding the second scan control is generated, and the display data of the data line control signal 7 is black data in accordance with the second scan timing. The scan second control circuit 203 generates the second scan drive signal and overlaps with the normal scan drive signal 17 to generate the multiple scan drive signal 204 that performs two scans in one frame. do. The conventional display unit 205 is different from the first embodiment, and the pixels on the line selected by the scan line multiple drive signal 204 light up in accordance with the signal voltage supplied to the data line drive signal 15. In the second embodiment, as shown in FIG. 12, after writing the normal signal voltage, black data is always written at different timings for each scan line, thereby controlling the pixel lighting time for each scan line, thereby reducing the drop described in the first embodiment. Get The other part is the same operation as in the first embodiment.

Details of the operation of the multi-scan display control unit 201 will be described. The multi-display control signal generator generates a data line control signal 7, a scan line control signal 8, and a data read instruction signal 105, and references the current detection information 21 to the scan second control signal ( 202). As shown in FIG. 12, the scan line second drive control circuit generates a scan second start signal 227 serving as a reference for the scan second drive after normal writing. The scan second shift clock control circuit generates a scan second shift clock for shifting the scan second start signal.

In FIG. 12, the scan second start signal shift circuit 230 shifts the scan second start signal 227 in accordance with the scan second shift clock 229, thereby scanning second scan lines of each scan line as shown in FIG. 12. Generate a drive signal. Finally, each scan line overlapping circuit overlaps the scan drive signal and the scan second drive signal, thereby generating a multiple scan drive signal that performs two scans in one frame, as shown in FIG. At this time, as shown in FIG. 12, the display period of each scanning line can be changed by changing the frequency of the scanning 2nd shift clock 229 from the scanning shift clock 122. As shown in FIG. Therefore, by adjusting this frequency in accordance with the current detection information 21, it is possible to adjust the display period for supplementing the voltage drop as in the first embodiment.

Instead of inserting black data, display data having a lower luminance than display data may be inserted.

According to the second embodiment of the present invention, the lighting control switch 43 or the lighting control line (for example, the first lighting control line 30 or the 480th lighting control line) provided for each pixel with respect to the first embodiment. 31)), it is possible to control the lighting / lighting off of the organic EL 44 substantially, so that the constitution of the pixel is simplified in addition to the effect of the first embodiment. In addition, in order to use the lighting control switch 43 for applications other than the lighting control of the organic EL 44, you may provide in the pixel.

Moreover, you may apply this invention to a liquid crystal display or a plasma display as well as a self-luminous element display.

 According to the present invention, a change in luminance due to the arrangement position of the display element can be reduced.

In addition, according to the present invention, it is possible to reduce the change in luminance due to the voltage drop of the wiring from the current source to the display element.

Claims (20)

In a display device, A plurality of display elements arranged in a matrix, A driving voltage generation circuit for generating a driving voltage for driving the display element; A data line driving circuit which generates a signal voltage for controlling the amount of current of the driving voltage according to display data; A scan line driver circuit for selecting the display element to be driven; Control circuit for controlling the lighting time of the display element according to the distance along the current path from the drive voltage generation circuit to the display element Including, The control circuit lengthens the lighting time as the distance from the driving voltage generation circuit to the display element increases. The control circuit may be configured such that the distance from the drive voltage generation circuit is small as the amount of current of the drive voltage increases, or as the gradation of the display data increases, or as the light emission luminance of the display element increases. The display device which enlarges the ratio which lengthens the said lighting time of the said display element with the distance from the said drive voltage generation circuit large with respect to the lighting time of an element. The method of claim 1, And a plurality of display elements having the same light emission luminance when the values of the display data are the same. The method of claim 1, A blocking circuit for interrupting the supply of the driving voltage to the display element in accordance with a control signal from the control circuit; Display device further comprising. delete The method of claim 1, And a detection circuit for detecting an amount of current of the driving voltage. delete The method of claim 1, And a detection circuit for detecting light emission luminances of the plurality of display elements. The method of claim 1, And the control circuit controls the lighting time by inserting black display data into the display data and controlling timing and / or time of inserting the black display data. The method of claim 1, And the control circuit controls the lighting time by inserting display data having a lower luminance than the display data into the display data and controlling timing and / or time of inserting the display data having the lower luminance. In a display device, A plurality of display elements arranged in a matrix, A driving voltage generation circuit for generating a driving voltage for driving the display element; A data line driving circuit for generating a signal voltage for controlling the amount of current of the driving voltage according to display data; Scan line driver circuit for selecting the display element to be driven Including, The display element is different from each other in the lighting time of the display element according to the arrangement position of the display element relative to the arrangement position of the driving voltage generation circuit. As the distance from the driving voltage generation circuit to the display element increases, the display element has a longer lighting time. As the amount of current of the drive voltage increases, or as the gray scale of the display data increases, or as the light emission luminance of the display element increases, the lighting time of the display element with a small distance from the drive voltage generation circuit is small. The ratio of lengthening the lighting time of the display element having a large distance from the driving voltage generating circuit increases with respect to. The method of claim 10, A control circuit for controlling the lighting time according to the arrangement position Display device comprising a. The method of claim 10, And wherein the plurality of display elements have different lighting times depending on the arrangement position when the light emitting luminances of the display elements are the same. The method of claim 10, When the drive voltage generation circuit is arranged above the column direction with respect to the arrangement position of the plurality of display elements, The display device located above the column direction among the plurality of display elements has a shorter lighting time than the display device located below the column direction among the plurality of display elements. The method of claim 10, When the driving voltage generation circuit is disposed below the column direction with respect to the arrangement position of the plurality of display elements, The display device located below the column direction among the plurality of display elements has a shorter lighting time than the display element located above the column direction among the plurality of display elements. The method of claim 10, When the driving voltage generation circuit is disposed at the left side in the row direction with respect to the arrangement positions of the plurality of display elements, The display element located in the row direction left of the plurality of display elements has a shorter lighting time than the display element located in the row direction right of the plurality of display elements. The method of claim 10, When the drive voltage generation circuit is disposed on the right side in the row direction with respect to the arrangement positions of the plurality of display elements, The display element located on the right side of the row direction among the plurality of display elements has a shorter lighting time than the display element located on the left side of the row direction among the plurality of display elements. The method of claim 1, A plurality of drive voltage supply lines connecting the plurality of display elements and the drive voltage generation circuit; A plurality of data lines connecting the plurality of display elements and the data line driver circuit; A plurality of scanning lines connecting the plurality of display elements and the scanning line driver circuit, The plurality of driving voltage supply lines are wired in the column direction of the plurality of display elements, The plurality of data lines are wired in the column direction of the plurality of display elements, The plurality of scanning lines are wired in the row direction of the plurality of display elements. The method of claim 17, The control circuit controls the lighting time of the display element by adjusting the lighting end timing according to the distance along the current path from the driving voltage generation circuit to the display element, The adjustment amount T _W n of the lighting termination timing from the lighting termination reference timing of the display element connected to the nth scan line is V the voltage drop from the _EL driving voltage generating circuit according to a current route to the display element, A wiring resistance along a current path from the driving voltage generation circuit to the display element, I _EL is the driving current of the display element, V _D is the driving voltage of the display element, C _EL is the voltage drop rate of the display element, N is the number of scan lines, Scan cycle of the scan line, When Tb is set as the delay amount of the lighting termination reference timing,

Display device determined by. The method of claim 10, A plurality of drive voltage supply lines connecting the plurality of display elements and the drive voltage generation circuit; A plurality of data lines connecting the plurality of display elements and the data line driver circuit; A plurality of scanning lines connecting the plurality of display elements and the scanning line driver circuit, The plurality of driving voltage supply lines are wired in the column direction of the plurality of display elements, The plurality of data lines are wired in the column direction of the plurality of display elements, The plurality of scanning lines are wired in the row direction of the plurality of display elements. The method of claim 19, The lighting time of the display element is controlled by adjusting the lighting end timing according to the arrangement position of the display element relative to the arrangement position of the drive voltage generation circuit, The adjustment amount T _W n of the lighting termination timing from the lighting termination reference timing of the display element connected to the nth scan line is Voltage drop along the V _EL on the arrangement position of the display element to a placement position of the drive voltage generating circuit, Wiring resistance according to an arrangement position of the display element relative to an arrangement position of the driving voltage generation circuit, I _EL is the driving current of the display element, V _D is the driving voltage of the display element, C _EL is the voltage drop rate of the display element, N is the number of scan lines, Scan cycle of the scan line, When Tb is set as the delay amount of the lighting termination reference timing,

Display device determined by.

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