KR100633331B1 - Method for forming overlay vernier - Google Patents

Abstract

The method for forming a multi-overlay vernier according to the present invention comprises the steps of: forming a first parent vernier having a pair of bars formed in parallel at a predetermined interval in an intaglio on a first layer, and the intaglio of the first parent vernier being Forming a second mother vernier on the second layer on the first layer by embossing a second mother vernier in a direction orthogonal to the first mother vernier so as to be exposed, in parallel with a predetermined interval; By forming the magnetic vernier consisting of the third layer on the second layer, it is possible to shorten the time required to manufacture the semiconductor to improve the productivity, resulting in the effect of reducing the semiconductor production cost have.

Semiconductor element, vernier, embossed, engraved

Description

How to form a multi-overlay vernier {METHOD FOR FORMING OVERLAY VERNIER}             

1 is an exemplary view showing a degree of overlap measurement mark of a general box in box type,

2 is a view showing a planar shape of the first parent overlay vernier according to the present invention,

3 is a view showing a planar shape of a second parent overlay vernier according to the present invention;

4 is a view showing a planar shape of the ruler overlay vernier according to the present invention,

5 is a view showing a shape in which each overlay vernier of FIGS.

Explanation of symbols on the main parts of the drawings

10: Mod Overlay Vernier 20: Purple Overlay Vernier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an overlay vernier employed in a semiconductor device manufacturing process to evaluate the degree of overlap. More specifically, the present invention relates to a multi-overlay capable of simultaneously evaluating the degree of overlap with two layers. A method of forming a vernier.

In general, in forming the circuit patterns in the manufacturing process of the semiconductor device, it is necessary to accurately overlap the circuit pattern formed first and the circuit pattern formed later.

As such, in order to measure the degree of overlap indicating the degree of overlap between the lower pattern and the upper pattern, as shown in FIG. 1, a mother overlay vernier (mothert overlay) is formed in forming a previously formed lower layer in the scribe lane of the wafer. A vernier 10 is formed and a son overlay vernier 20 is formed when forming the currently formed layer to evaluate whether the upper and lower patterns overlap correctly by the overlapping degree of both verniers. . In this case, the overlay vernier illustrated in FIG. 1 is an exemplary diagram illustrating a overlapping measurement mark of a general box in box type.

However, such overlap evaluation is performed every layer for accurate pattern formation in forming a semiconductor device having a multi-layer structure, so that the time required for the entire semiconductor device is large, resulting in a large cost increase. have.

Therefore, in order to shorten the process time and improve productivity, it is necessary to shorten the time required for the degree of overlap evaluation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a multi-overlay vernier that can contribute to productivity improvement by shortening the time required for the evaluation of the degree of overlap during the semiconductor process.

The multi-overlay vernier forming method according to an embodiment of the present invention for achieving the above object is a multi-overlay vernier forming method used to measure the overlapping degree of the upper layer and the lower layer in the semiconductor manufacturing process, a predetermined interval Forming a first parent vernier having a pair of bars formed in parallel on the first layer in an intaglio manner in a first layer, and in a direction orthogonal to the first parent vernier so that the intaglio of the first parent vernier is exposed, Embossing a second mother vernier having a pair of bars formed parallel to each other at a predetermined interval on the second layer on the first layer, and forming a box-shaped ruler vernier on the second layer. It is formed to include.

The method for forming a multi-overlay vernier according to another embodiment of the present invention is characterized in that the first mother vernier and the second mother vernier of the embodiment form a box in a bar in bar state.

In addition, according to another embodiment of the present invention, in the method of forming a multi-overlay vernier, the box shape of the first parent vernier and the second parent vernier is used as the outer box, and the ruler vernier is the inner box. It is characterized by forming a box in box (box in box) shape.

On the other hand, the method for forming a multi-overlay vernier according to another embodiment of the present invention, the first mother vernier is a gate vernier, the second vernier is characterized in that the bit line vernier.

Hereinafter, the present invention will be described in more detail with reference to preferred embodiments 2 to 5.

First, referring to FIG. 2, the first parent vernier 100 forms a pair of bars 100a and 100b parallel to each other in one direction (eg, the longitudinal direction), and is formed in an intaglio. At this time, the first mother vernier 100 is, for example, a gate mother vernier formed on the scribe line of the wafer simultaneously with the gate of the semiconductor device.

Again, referring to FIG. 3, the second parent vernier 110 is in a direction orthogonal to the direction formed by the pair of bars 100a and 100b constituting the first parent vernier 100 (eg, in a transverse direction). A pair of bars (110a, 110b) in parallel to each other is formed, but is formed in relief. In the present invention, since the overlapping degree should be simultaneously measured with a single vernier with respect to the longitudinal vernier and the lateral vernier formed on the two layers, the second parent vernier ( Even if 110 is formed, the first parent vernier 100 should not be shielded by the second parent vernier 110. Therefore, in the present invention, by forming the second parent vernier 110 in relief, as shown in FIG. 5, when the degree of overlap with the subsequent child vernier 120 is evaluated, the first parent vernier 100 is the second parent vernier. When forming (100) it is not shielded but appears clearly. At this time, the second mother vernier 110 is, for example, a bit line mother vernier formed on the scribe line of the wafer at the same time as the bit line of the semiconductor device.

Next, referring to FIG. 4, the ruler vernier 120 has a box shape having a smaller size than a box (used as an outer box) including the first parent vernier 100 and the second parent vernier 110. Used as an inner box) to form an overlapping mark of a box in box type together with the outer box.

When the planar vernier shown in Figs. 2 to 4 overlap with each other by the above-described process, they appear as shown in Fig. 5. As shown in FIG. 5, it can be seen that the second parent vernier 110 is clearly displayed without being shielded by the first parent vernier 100.

On the other hand, as described above, the method of forming a multi-overlay vernier of the present invention, the second parent vernier is embossed, so as not to shield the first parent vernier, the process of the previous vernier is shielded by the vernier of the subsequent layer For example, even when the gate parent vernier is applied to a process that is shielded by the hard mask tungsten of the subsequent process and cannot be read, the degree of overlap can be accurately confirmed in each of the longitudinal direction and the lateral direction in units of two layers.

 According to the present invention described above, by performing the overlapping degree checking process, which is performed in units of layers, in units of two layers, it is possible to shorten the time required for semiconductor manufacturing by that amount and improve productivity. As a result, the semiconductor production cost can be reduced.

Claims (4)

In the method of forming a multi-overlay vernier used to measure the overlapping degree of the top layer and the bottom layer in the semiconductor manufacturing process, Negatively forming a first parent vernier on the first layer, the first parent vernier comprising a pair of bars formed in parallel at a predetermined interval, Embossing a second parent vernier comprising a pair of bars formed in parallel with a predetermined interval in a direction orthogonal to the first parent vernier so that the intaglio of the first parent vernier is exposed to the second layer on the first layer Forming with, A method for forming a multi-overlay vernier, comprising: forming a box-shaped ruler vernier in a third layer on a second layer. The method of claim 1, The first mother vernier and the second mother vernier forming a box shape bar in bar (bar in bar) characterized in that the multi-overlay vernier forming method. The method of claim 2, And forming a box in box shape using a box shape consisting of the first mother vernier and the second mother vernier as an outer box, and the child vernier as an inner box. The method according to any one of claims 1 to 3, And wherein the first parent vernier is a gate vernier, and the second vernier is a bit line vernier.

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