KR100633234B1 - Interfacing apparatus between driver ICs in LCD - Google Patents

Abstract

An interface device between driver integrated circuits of a liquid crystal display device is disclosed. The interface device according to the present invention has a state value indicating whether data can be transferred from a controller connected through a system bus to a gate driver integrated circuit through a source driver integrated circuit and a parallel type applied from the controller to control the gate driver integrated circuit. A first register for storing control data, a second register for capturing and buffering the state value and parallel control data stored in the first register, and parallel control data stored in the second register as control data in serial form. After the conversion, the data converter transmits the gate driver integrated circuit through the data transmission line and the state value stored in the second register to determine whether data can be transferred to the gate driver integrated circuit. Possible If it is determined to include a state machine for controlling the data conversion unit to perform a data conversion operation.

LCD, Source Driver, Gate Driver, Interface

Description

Interfacing apparatus between driver ICs in LCDs

1 is a view schematically showing a liquid crystal display according to a preferred embodiment of the present invention;

FIG. 2 is a schematic block diagram of the interface device shown in FIG. 1;

3 shows a state diagram of a state machine according to the invention,

4 is a circuit diagram schematically showing the configuration of the data converter shown in FIG. 2, and

5 is a timing diagram for explaining a data transfer operation to a gate driver IC in the interface device according to the present invention.

Explanation of symbols on the main parts of the drawings

110: liquid crystal panel 120: source driver IC

130: gate driver IC 140: control unit

200: interface device 210: first register

212: status register 214: data register

220: second register 222: status capture register

224: data capture register 230: state machine

240: data conversion unit

The present invention relates to an interface device, and more particularly to a case in which a source driver and a gate driver for driving a liquid crystal panel of a liquid crystal display are configured as separate chips. And an apparatus for providing a communication interface between a source driver integrated circuit (IC) and a gate driver IC.

Liquid crystal display devices are currently being used as a display for personal computers or TV screens because of their low power consumption, light weight, and thinness, compared to CRTs.

The liquid crystal display may be largely divided into a liquid crystal panel and a driver. The liquid crystal panel may include a lower glass substrate on which pixel electrodes and thin film transistors are arranged in a matrix, an upper glass substrate on which a common electrode and a color filter layer are formed, and an upper and lower sides. It consists of a liquid crystal layer filled between glass substrates.

In addition, the driving unit processes a video signal input from the outside and outputs a composite synchronization signal, and receives a composite synchronization signal output from the image signal processing unit and outputs a horizontal synchronization signal and a vertical synchronization signal separately. A control unit controlling timing according to a selection signal (eg, NTSC, PAL, SECAM), a data driver supplying a signal voltage to a data line of the liquid crystal panel unit according to the control signal of the control unit, and a liquid crystal according to the control signal of the control unit And a gate driver for sequentially applying a driving voltage to the gate line of the panel portion.

The source driver and the gate driver may be configured as one chip, or may be configured as separate chips, respectively, according to the resolution, area, etc. of the liquid crystal panel unit. In general, a source driver and a gate driver for driving a low-resolution liquid crystal panel may be configured as a single chip because the internal circuit is relatively simple. However, in the case of a source driver and a gate driver for driving a high resolution liquid crystal panel, the configuration of the internal circuit is complicated, and the size of the circuit is so large that it cannot be composed of one chip.

When the source driver and the gate driver are configured in one chip, it is possible to design by simply determining the interface method between the two. However, when the source driver and the gate driver are configured as separate chips, a protocol for regularly connecting the two chips is required. Although an interface for communication between two separately configured chips can be implemented in various ways, an interface method that can be simply implemented without increasing the size of a circuit suitable for a thin film transistor liquid crystal display device is required.

An object of the present invention is to provide an interface device that supports a protocol for serial communication between two chips when the source driver and the gate driver are configured as separate chips.

In order to solve the above technical problem, the interface device for serial communication between the source driver integrated circuit and the gate driver integrated circuit according to the present invention, the gate driver integrated circuit through a source driver integrated circuit from a control unit connected via a system bus A first register configured to store a state value indicating whether the data can be transmitted to a second memory device and a control data of parallel type applied from the controller to control the gate driver integrated circuit; A second register for capturing and buffering the state value stored in the first register and the control data in parallel; A data conversion unit converting the parallel control data stored in the second register into serial control data and transmitting the data to the gate driver integrated circuit through a data transmission line; And determining whether data can be transferred to the gate driver integrated circuit by checking the state value stored in the second register, and performing the data conversion operation when it is determined that data can be transmitted to the gate driver integrated circuit. And a state machine for controlling the data conversion unit.

The state machine generates and transmits a chip select signal and a clock signal to the gate driver integrated circuit to transmit the serial control data converted by the data converter to the gate driver integrated circuit.

Advantageously, said first register comprises: a status register for storing said status value; And a data register for storing the parallel control data applied from the controller.

The second register may further include: a state capture register configured to capture and buffer the state value stored in the state register; And a data capture register for capturing and buffering the parallel data stored in the data register.

The control unit checks the state value set in the state register and transmits the parallel control data to the gate driver integrated circuit when it is determined that the data can be transmitted to the gate driver integrated circuit through the source driver integrated circuit. Is transmitted to the data register via the system bus.

Preferably, when the state machine determines that data transfer from the data converter to the gate driver integrated circuit is completed, the state machine sets the status register to inform the gate driver integrated circuit that the next data transfer is possible. Reset the status value.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. However, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a view schematically showing a liquid crystal display according to a preferred embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to the present invention includes a liquid crystal panel 110 having a plurality of pixels at intersections of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLn, and the liquid crystal. A source driver integrated circuit (IC) 120 that provides an image signal to each pixel through the data line of the panel 110, and a gate driver integrated circuit that selects a gate line to 'on' a plurality of pixels. (IC) 130, and a control unit 140 for controlling the source driver IC 120 and the gate driver IC 130.

As shown in FIG. 1, the controller 140 and the source driver IC 120 according to the present invention are connected through a system bus, and perform mutual data communication through the system bus. The controller 140 directly controls the source driver IC 120 through a system bus, and controls the gate driver IC 130 through an interface device 200 provided in the source driver IC 120. That is, the controller 140 directly transmits data and instructions to the source driver IC 120 through the system bus, and transmits data and instructions to the gate driver IC 130 to the source driver IC 120. Transfer through the provided interface device 200.

The source driver IC 120 and the gate driver IC 130 according to the present invention perform serial communication. To this end, the source driver IC 120 is provided with an interface device 200 that supports a serial data transfer protocol with the gate driver IC 130. The interface device 200 converts parallel control data (eg, 16 bits) applied from the controller 140 into serial control data and transmits the converted control data to the gate driver IC 130.

FIG. 2 is a schematic block diagram of the interface device 200 shown in FIG. 1.

Referring to FIG. 2, the interface device 200 includes a first register 210, a second register 220, a state machine 230, and a data converter 240.

The first register 210 is connected to the control unit 140 via a system bus and includes a status register 212 and a data register 214.

The status register 212 is a value indicating whether the control unit 140 is in a state where data can be transferred to the gate driver IC 130 through the source driver IC 120, that is, the source driver IC 120 has the gate driver IC 130. Stores a state value (TE) that indicates whether the state is accessible. For example, when the source driver IC 120 sets the state value TE to '0' when the source driver IC 120 is accessible to the gate driver IC 130, the source driver IC 120 transmits the gate driver IC 130 to the gate driver IC 130. In case of busy state (busy), set the state value (TE) to '1'.

The data register 214 stores parallel control data transmitted from the controller 140 via the system bus. The control unit 140 must check whether the source driver IC 120 is accessible to the gate driver IC 130 before transmitting control data to the gate driver IC 130 to the data register 214. . The controller 140 transmits data to the data register 214 only when it is determined that the data transfer to the gate driver IC 130 is possible. In addition, the controller 140 transmits the status value TE change information to the status register 212 to change the status value TE of the status register 212 to '1'. Accordingly, the state value TE of the state register 212 is changed from '0' to '1'. In this case, the controller 140 may not transmit data to the data register 214 until the state value TE of the status register 212 is reset to '0'.

The second register 220 captures and buffers a state value TE stored in the state register 212 and a data capture register that captures and buffers data stored in the data register 214. 224.

The state machine 230 controls the data converter 240 to be described later in order to transmit the parallel control data buffered in the data capture register 224 to the gate driver IC 130, and the data converter 240. ) Generates a chip select signal GCS and a clock signal GCL to transfer the data converted by the < RTI ID = 0.0 > The state machine 230 according to the present invention is operated based on the state diagram shown in FIG.

3 shows a state diagram of a state machine 230 in accordance with the present invention.

As shown in FIG. 3, the state machine 230 has six states: STA_IDLE, STA_TRS, STA_TRF, STA_TRE, STA_RETTE, and STA_RETTEE.

Here, the "STA_IDLE" state is an initialization state, and the control unit 140 can transmit data to the gate driver IC 130 through the source driver IC 120, and the "STA_TRS" state is a state register 212. Initial state to start data transmission with 'TE' as '1'. The "STA_TRF" state is a state in which data is transmitted to the gate driver IC 130, and the "STA_TRE" state is a state in which data transfer to the gate driver IC 130 is terminated. Lastly, the "STA_RETTE" and "STA_RETTEE" states are states in which data transfer to the gate driver IC 130 is completed and returned to the "STA_IDLE" state.

As described above, the state machine 230 starts operation when the state value TE is '0', returns to the "STA_IDLE" state after the transfer ends, and returns the state value TE of the state register 212. Reset As described above, when the state value TE of the status register 212 is reset after the data transfer to the gate driver IC 130 is completed, data may be transmitted several times.

In addition, the state machine 230 generates a chip select signal GCS and a clock signal GCL for data transmission to the gate driver IC 130. Here, the chip select signal GCS is a signal indicating the start and end of data transmission.

Referring back to FIG. 2, the data converter 240 converts parallel control data received from the state machine 230 into serial control data under the control of the state machine 230, and then converts the data transmission line. Transmit to gate driver IC 130 through.

4 is a circuit diagram schematically showing the configuration of the data converter 240 shown in FIG.

As shown in FIG. 4, the data converter 240 includes a plurality of multiplexers (mux) and a plurality of flip-flops, and the output of the previous flip-flop is fed back to the input of the current multiplexer (mux). It consists of. Each multiplexer mux selects one of control data input from the state machine 230 and data fed back from a previous flip-flop according to a load signal, and outputs it to each flip-flop connected to an output terminal. Data stored in each flip-flop is shifted and output according to a clock signal input to a clock terminal. Accordingly, parallel control data input from the state machine 230 is converted into serial control data by the data converter 240 and output.

As illustrated in FIG. 5, the data signal GDA output from the data converter 240 is a gate driver IC based on the chip select signal GCS and the clock signal GCL signal generated by the state machine 230. Is sent to 130. The data signal GDA output from the data converter 240 sequentially switches the gate driver IC in synchronization with the clock signal GCL when the chip select signal GCS is switched from high to low. 130). Then, the transfer ends when the chip select signal GCS transitions from low to high.

On the other hand, the present invention has been described in detail through a representative embodiment, but those skilled in the art to which the present invention pertains various modifications within the scope of the present invention without departing from the scope of the present invention. I will understand what is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

As described above, according to the present invention, by providing an interface device for serial communication between a source driver integrated circuit and a gate driver integrated circuit, the control unit may control the source driver and the gate driver even when the source driver and the gate driver are configured as separate chips. It can provide a basis for easy control of the gate driver.

Claims (6)

Storing a state value indicating whether data can be transferred from a controller connected through a system bus to a gate driver integrated circuit through a source driver integrated circuit and parallel control data applied from the controller to control the gate driver integrated circuit. A first register; A second register for capturing and buffering the state value stored in the first register and the control data in parallel; A data conversion unit converting the parallel control data stored in the second register into serial control data and transmitting the data to the gate driver integrated circuit through a data transmission line; And It is determined whether data can be transferred to the gate driver integrated circuit by checking the state value stored in the second register, and the data is performed to perform the data conversion operation when it is determined that data can be transmitted to the gate driver integrated circuit. A state machine for controlling the converter; Interface device for serial communication between the source driver integrated circuit and the gate driver integrated circuit. The method of claim 1, The state machine generates a chip select signal and a clock signal to transmit the serial control data converted by the data converter to the gate driver integrated circuit and transmits the generated signal to the gate driver integrated circuit. An interface device for serial communication between a driver integrated circuit and a gate driver integrated circuit. The method of claim 1, The first register is, A status register for storing the status value; And And a data register for storing the parallel type control data applied from the controller. The method of claim 3, wherein The second register, A status capture register for capturing and buffering the status value stored in the status register; And And a data capture register for capturing and buffering the data in the parallel form stored in the data register. The method of claim 3, wherein The control unit checks the state value set in the state register and transmits the parallel control data to the gate driver integrated circuit when it is determined that the data can be transmitted to the gate driver integrated circuit through the source driver integrated circuit. And serial communication between the source driver integrated circuit and the gate driver integrated circuit via the system bus to the data register. The method of claim 3, wherein When the state machine determines that the data transfer from the data converter to the gate driver integrated circuit is completed, the state machine resets the state value set in the status register to indicate that the next data transfer is possible to the gate driver integrated circuit. and an interface device for serial communication between the source driver integrated circuit and the gate driver integrated circuit.

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