KR100631833B1 - Linear Selection Filter Using Weighted BCD Code - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a linear selection filter using a weighted BCD nose that uses a GM current cell suitable for an integrated circuit and implements GM control with a simple and low power consumption.

The present invention relates to a linear selection filter including a resistance (R) and a capacitance (C) suitable for implementation in an integrated circuit, comprising: a gate terminal connected to a signal input terminal for receiving a signal and a drain terminal connected to a signal output terminal for outputting a signal; And an input / output circuit part 51 including two differential MOS transistors M11 and M12 having a source terminal grounded through a current source; A switching controller 52 providing a switching signal for frequency selection; A GM control unit 53 for supplying a voltage required for operation; A plurality of source terminals of the differential MOS transistors M11 and M12 of the input / output circuit unit 51 are connected in parallel, are connected in common to the voltage of the GM control unit 53, and have a different resistance RGM. A GM variable portion 54 made up of MOS transistors M21-M25; A plurality of switch elements SW1A installed at source and drain terminals of the plurality of MOS transistors M21 to M25 of the GM variable unit 54 and switched on / off according to a switching signal of the switching controller 52. A switching unit 55 including SW5A, SW1B, and SW5B; And a capacitor circuit part 56 connected to an output terminal of the input / output circuit part 51 to provide a capacitance C.

In this configuration, it is characterized in that it is configured to provide a resistance (RGM) that is linearly variable according to the switching operation of the switching unit.

Weighted Current, Linear Select Filter, GM Current Cell

Description

Linear select filter using weighted BCD code {liner select filter USING WEIGHED BCD CODE}

1 is a block diagram of a general variable filter.

2 is a block diagram of a conventional linear selection filter.

3 is an equivalent circuit diagram of FIG. 2.

4 is a circuit diagram of the frequency adjusting unit of FIG. 2.

5 is a block diagram of a linear selection filter according to the present invention.

6 is a tuning graph of a linear filter according to the present invention.

Explanation of symbols on the main parts of the drawings

51: input and output circuit

52: switching control

53: GM control unit

54: GM current cell part

55: switching unit

56: capacitor circuit part

The present invention relates to a linear selection filter using a weighted BCD nose, and in particular, by using a GM current cell suitable for implementing an integrated circuit, and by implementing a GM to control a simple and low power consumption, using a GM current cell It can be implemented as an integrated circuit to reduce the loss of the area (Loss), it is possible to adjust the current of the MOS transistor using a weighted BCD code, it is possible to easily control the GM of the MOS transistor, accordingly A linear selection filter using a weighted BCD nose can reduce consumption.

In general, a filter for selecting a frequency is used in an RF front end part of a receiver. In the case of an analog filter, a switched capacitor filter (SCF), a MOS transistor filter, and an OTA ( Three types of filters, such as a filter having an Operational Transconductor Amplifier structure, are used. In order to obtain the filter characteristics of several tens of MHz band, the filter of the OTA structure is the mainstream. In this OTA filter, the GM-C filter using the transconductance (GM) is most used.

The GM-C filter has a disadvantage in that the configuration of the filter is difficult because current control is not easy, but it is known as a general structure that is most used in several tens of MHz bands. In particular, in the structure of a filter requiring a linear characteristic, it is not easy to convert the frequency into one filter.

FIG. 1 is a block diagram of a conventional variable filter. In the conventional variable filter shown in FIG. 1, when a frequency is to be varied, a filter having the same structure for different frequency selection is connected in parallel or a structure of the filter. You must redesign the new type of filter by changing.

For example, if three frequency bands are required depending on the application range, for example, three switches (SW1, SW2, SW3) and three different frequency selective filters to handle the 8 MHz, 18 MHz and 27 MHz bands (F1, F2, F3) are required. However, such a filter structure has a disadvantage in that the layout area on the chip is increased, thereby resulting in an increase in the unit cost of the chip. Filters have been proposed.

2 is a block diagram of a conventional linear selection filter.

Referring to FIG. 2, the linear channel selection filter according to the present invention includes a frequency adjusting unit 20 determining a control voltage VC according to a selection signal VS, and a control voltage VC of the frequency adjusting unit 20. ) Includes a GM current cell unit 21 that provides a resistance (RGM) that is linearly variable according to), and a capacitor circuit unit 22 that is connected to the GM current cell unit 21 to provide a capacitance (C).

FIG. 3 is an equivalent circuit diagram of FIG. 2, in which the R circuit is determined by the GM current cell unit 21 and C is determined by the capacitor circuit unit 22. The linear selection filter acts as an RC filter.

4 is a circuit diagram of the frequency adjusting unit of FIG. 2.

Referring to FIG. 4, the frequency control unit 40 may apply a D / A converter. For example, the resistance circuit unit 41 including a plurality of resistance elements between the reference voltage Vref and ground, A switch circuit portion 42 having a plurality of switch elements SW1-SW4 for selecting resistance elements of the resistance circuit portion 41 in accordance with the plurality of switching signals VS1-VS4, and the switch circuit portion 42. And a voltage generator 43 for generating the control voltage VC according to the resistance value RSW determined by the resistance element of the resistor circuit 41 selected by.

The resistance circuit part 21 of the frequency adjusting part 20 includes a plurality of resistance elements R11-R14 connected in series between the reference voltage (-Vref) and the ground, and the plurality of resistance elements R11-R14. And a plurality of resistors R21-R24 having one end connected to a connection point between the plurality of resistors, and the switch circuit unit 22 is electrically connected to the other end of each of the plurality of resistors R21-R24 and ground. It may include a plurality of switching elements (SW1-SW4) for switching the plurality of switching elements (SW1-SW4) is controlled by the plurality of switching signals VS1-VS4.

The voltage generator 23 may include an inverting terminal commonly connected to the other ends of the plurality of resistors R21 to R24, a non-inverting terminal connected to ground, and a feedback resistance element RF to the inverting terminal. The operational amplifier OP having a connected output terminal and generating a control voltage according to a ratio between the resistance value RSW of the resistance circuit portion 21 and the feedback resistance element RF determined by the switch circuit portion 22. It may include.

However, in the conventional filter as described above, a D / A converter is used as the frequency control unit for linear tuning. When such a D / A converter is added, a large portion of the chip area is devoted. There is also a problem that the consumption of current also increases.

The present invention has been proposed to solve the above problems, and its object is to use a GM current cell suitable for an integrated circuit, and to implement a GM current cell by controlling GM in a simple and low power consumption type. It can be implemented as an integrated circuit to reduce the loss of the area (Loss), the GM control can be easily performed by using a weighted BCD code, and accordingly linear with a weighted BCD nose that can reduce power consumption To provide a selection filter.

In order to achieve the above object of the present invention, the linear selection filter using the weighted BCD nose of the present invention is

In the linear selection filter consisting of resistance (R) and capacitance (C) suitable for implementation in an integrated circuit,

An input / output circuit unit comprising two differential MOS transistors having a gate terminal connected to a signal input terminal for receiving a signal, a drain terminal connected to a signal output terminal for outputting a signal, and a source terminal grounded through a current source;

A switching controller for providing a switching signal for frequency selection;

A GM control unit supplying a voltage required for operation;

A plurality of MOS transistors connected in parallel between the source terminals of the differential MOS transistors of the input / output circuit unit, connected in common to the voltages of the GM control unit, and having a different resistance and varying according to a switching operation. GM variable unit for providing RGM);

A switching unit which is provided at source and drain terminals of the plurality of MOS transistors of the GM variable unit, and includes a plurality of switch elements that are switched on / off according to a switching signal of the switching controller; And

A capacitor circuit part connected to an output terminal of the input / output circuit part to provide a capacitance;

In this configuration, it is characterized in that it is made to provide a resistance that is linearly changed according to the switching operation of the switching unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

5 is a block diagram of a linear selection filter according to the present invention.

Referring to FIG. 5, a linear selection filter using a weighted BCD nose according to the present invention is a linear selection filter having a resistance (R) and a capacitance (C) suitable for implementing as an integrated circuit, which is connected to a signal input terminal for receiving a signal. I / O circuit section 51 consisting of two differential MOS transistors M11 and M12 having a gate terminal connected, a drain terminal connected to a signal output terminal for outputting a signal, and a source terminal grounded through a current source, and switching for frequency selection Connected in parallel between a switching control unit 52 for providing a signal, a GM control unit 53 for supplying a voltage required for operation, and a source terminal of the differential MOS transistors M11 and M12 of the input / output circuit unit 51, A GM variable unit 54 connected to the voltage of the GM control unit 53 in common with the gate and composed of a plurality of MOS transistors M21 to M25 having different resistances RGM, and the GM; A plurality of switch elements SW1A to SW5A which are respectively provided at source and drain terminals of the plurality of MOS transistors M21 to M25 of the variable unit 54 and switched on / off according to a switching signal of the switching controller 52. And a switching unit 55 including SW1B-SW5B, and a capacitor circuit unit 56 connected to an output terminal of the input / output circuit unit 51 to provide a capacitance C.

In the filter of the present invention configured as described above, it is made to provide a resistance (RGM) that varies linearly according to the switching operation of the switching unit.

The input / output circuit 51 may include a first MOS transistor M11 having a drain terminal connected to a power supply Vcc terminal and a gate terminal connected to one input terminal of a differential input voltage Vin terminal, and the first MOS transistor M11. A first current source CS11 connected between the source terminal and the ground of the MOS transistor M11, a drain terminal connected to a power supply Vcc terminal, and a gate terminal connected to the other of the differential input voltage Vin terminal; A second MOS transistor M12 and a second current source CS12 connected between a source terminal of the second MOS transistor M12 and a ground are included.

The GM variable unit 54 includes a drain terminal connected to the source terminal of the first MOS transistor M11, a source terminal connected to the source terminal of the second MOS transistor M12, and a control of the GM control unit 53. A plurality of MOS transistors having a gate terminal connected to a voltage VC stage, each of the plurality of MOS transistors having different resistances between the drain terminal and the source terminal according to the control voltage VC of the GM control unit 53; (RGM).

In the above-described filter of the present invention, the input / output circuit portion and the GM variable portion form a GM current cell. In this case, the filter of the present invention operates according to a control voltage, and a MOS transistor is selected by switching. An equivalent sum resistance of the resistance RGM is formed. Here, the switching operation is controlled by a switching signal consisting of a BCD code. In addition, the BCD code may switch the plurality of switching transistors to different states according to different code values, and accordingly, the current flowing through each MOS transistor is adjusted. At this time, in consideration of the variable degree in the present invention, when the BCD code is a weighted BCD code, the current corresponding thereto is referred to as a weighted current.

The GM variable unit 54 is configured to select one or more MOS transistors among the plurality of MOS transistors by the switching unit 55.

Hereinafter, the operation and effects of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a GM current cell suitable for an integrated circuit is implemented, and a simple and low power consumption can be implemented to control the GM. Thus, the present invention can be implemented as an integrated circuit using a GM current cell. ), And the GM control can be easily performed using the weighted BCD code, thereby reducing the power consumption, which will be described with reference to FIGS. 5 and 6.

Referring to FIG. 5, in the filter of the present invention, the input / output circuit 51 receives an input signal to the gates of the differential MOS transistors M11 and M12, and an output terminal connected to the drain of the differential MOS transistors M11 and M12. In this case, the GM variable unit 54 of the present invention is adjusted to different GMs according to the switching control signal of the switching control unit 52 to provide different resistances.

The switching control unit 52 provides a switching signal for selecting a frequency. The switching signal is made of a BCD code corresponding to the number of MOS transistors included in the GM variable unit 54. For example, the GM variable When the unit 54 includes five MOS transistors, the switching signal may include a 5-bit BCD code.

Specifically, the switching signal of the present invention may be formed of a BCD code. In this case, the number of bits of the BCD code corresponds to the number of switches of the switching unit 55 to be controlled. Since the number of switches corresponds to the number of MOS transistors to be switched in the GM variable part 54, the number of bits of the BCD code eventually corresponds to the number of MOS transistors to be switched in the GM variable part 54.

For example, one MOS transistor to be switched in the GM variable unit 54 requires one switch on each side, that is, two switches, and both switches of one MOS transistor are in a state of 1 bit, that is, "1". The switching operation should be synchronized with each other by "or" 0 ".

In addition, when the GM variable unit 54 includes a non-switched MOS transistor, the bit of the switching signal may be determined corresponding to the number of MOS transistors to be switched.

Through such an operation process, the switching control unit 52 may select any number of MOS transistors among the plurality of MOS transistors included in the GM variable unit 54 using the switching signal composed of the BCD code. In this case, the GM voltage by the GM control unit 53 is supplied to the gate of the selected MOS transistor so that the selected MOS transistor is in an operating state.

That is, in accordance with the combination of the plurality of MOS transistors, resistance in various cases can be provided. Among the plurality of MOS transistors included in the GM variable unit 54, switching is performed by a switching signal of the switching control unit 52. After the additional operation, an arbitrary MOS transistor is selected, and when the GM control section 53 of the present invention applies a voltage to the gate of the selected MOS transistor, current flows to the selected MOS transistor, in which case the selected MOS transistor Will provide a predetermined resistance.

In this case, each of the plurality of MOSS transistors included in the GM variable unit 54 provides a predetermined internal resistance during operation. For example, when the plurality of MOSS transistors includes five MOS transistors, the reference resistance is defined as' GM ', the MOS selected when five MOS transistors are set to' 1 × GM ',' 2 × GM ',' 4 × GM ',' 8 × GM 'and '16 × GM', etc., respectively. The transistor will provide a preset resistance.

As a specific example, when the switching signals b0-b4 are '10000', both switches of the first MOS transistor M21 of the GM variable unit 54 of the switching unit 55 are 'on'. , All other switches are off. At this time, when the first MOS transistor M21 is set to 'GM', the resistance determined by the GM variable unit 54 becomes 'GM'. As another example, when the switching signals b0-b4 are '00110', both sides of the third and fourth MOS transistors M23 and M24 of the GM variable unit 54 of the switching unit 55 are included. The switch is 'on' and all other switches are off. In this case, when the third and fourth MOS transistors M23.M24 are set to '4 × GM' and '8 × GM', the resistance determined by the GM variable unit 54 may be set to '4 × GM'. It becomes the equivalent total resistance of '8 × GM'.

As shown in FIG. 5, in order to control the frequency of the filter with an external 5-bit control bit, the MOS transistor corresponding to each control bit may have a width size of the MOS transistor proportional to the weight value of the bit. . For example, in the case of 5 bits, if the ratio of the width sizes of the MOS transistors is "1: 2: 4: 8: 16", the current is also linearly selected according to the control bit.

Through the above-described process, when the resistance R is determined in the GM variable unit 54 of the present invention, the resistance is operated as an RC filter together with the capacitance C by the capacitor circuit unit 56 of the present invention. The desired frequency is selected by the RC filter, and it can be seen that the frequency selection characteristic can be changed linearly as shown in FIG. 6.

6 is a tuning graph of a linear filter according to the present invention.

Referring to FIG. 6, in the filter of the present invention, the current controlled by the conventional D / A converter does not use the D / A converter, and linear control is performed by an external control bit. As one can see, the filter has a linear selectivity.

In the present invention as described above, the current cell consisting of the MOS transistor selected by the BCD can be implemented in a very small area than the conventional filter using a D / A converter, there is an advantage that the current consumption is also consumed less.

According to the present invention as described above, by using a GM current cell suitable for implementing an integrated circuit, and to implement a simple and low power consumption to control the GM, it can be implemented as an integrated circuit using a GM current cell Loss on the area can be reduced, and GM control can be easily performed using a weighted BCD code, thereby reducing power consumption.

Since the above description is only a description of specific embodiments of the present invention, the present invention is not limited to these specific embodiments, and various changes and modifications of the configuration are possible from the above-described specific embodiments of the present invention. It will be apparent to those skilled in the art to which the present invention pertains.

Claims (4)

An input / output circuit section 51 comprising two differential MOS transistors M11 and M12 having a gate terminal connected to a signal input terminal for receiving a signal, a drain terminal connected to a signal output terminal for outputting a signal, and a source terminal grounded through a current source. ); A switching controller 52 providing a switching signal for frequency selection; A GM control unit 53 for supplying a voltage required for operation; A plurality of source terminals of the differential MOS transistors M11 and M12 of the input / output circuit unit 51 are connected in parallel, are connected in common to the voltage of the GM control unit 53, and have a different resistance RGM. A GM variable portion 54 including MOS transistors M21-M25 and providing a resistance RGM variable according to a switching operation; A plurality of switch elements SW1A installed at source and drain terminals of the plurality of MOS transistors M21 to M25 of the GM variable unit 54 and switched on / off according to a switching signal of the switching controller 52. A switching unit 55 including SW5A, SW1B, and SW5B; And A capacitor circuit part 56 connected to an output terminal of the input / output circuit part 51 to provide a capacitance C; Linear selection filter using a weighted BCD nose, characterized in that it comprises a. The method of claim 1, wherein the input and output circuit section 51 A first MOS transistor M11 including a drain terminal connected to a power supply Vcc terminal and a gate terminal connected to one input terminal of a differential input voltage Vin terminal; A first current source CS11 connected between the source terminal of the first MOS transistor M11 and a ground; A second MOS transistor M12 having a drain terminal connected to a power supply Vcc terminal and a gate terminal connected to the other of the differential input voltage Vin terminals; And Second current source CS12 connected between the source terminal of the second MOS transistor M12 and ground. Linear selection filter using a weighted BCD nose, characterized in that it comprises a. The method of claim 1, wherein the GM variable 54 is A drain terminal connected to the source terminal of the first MOS transistor M11, a source terminal connected to the source terminal of the second MOS transistor M12, and a control voltage VC terminal of the GM control unit 53. A plurality of MOS transistors having a gate stage, Each of the plurality of MOS transistors The linear selection filter using a weighted BCD nose, characterized in that it has a different resistance (RGM) between the drain terminal and the source terminal according to the control voltage (VC) of the GM control unit (53). The method of claim 1, wherein the GM variable 54 is Linear selection filter using a weighted BCD nose, characterized in that the switching unit 55 selects one or more MOS transistors among the plurality of MOS transistors.

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