KR100626100B1 - Data recording device and data recording method and recording medium - Google Patents

Abstract

In order to enable high-density recording and high-speed random access, in a case where data is recorded in a modified constant angular velocity (MCAV) method with respect to a phase change disk, an area with a low linear velocity and a high linear velocity Marks and spaces are formed in accordance with the recording pulses in which the start pulse and the end pulse are delayed to suit the area. That is, the pulse width is changed by changing the positions of the rising edge or falling edge of each of the start pulse and the end pulse constituting the recording pulse corresponding to the area. As a result, recording compensation suitable for each linear velocity is performed.

Description

Data recording apparatus and data recording method and recording medium

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a data recording apparatus, a data recording method, and a recording medium. In particular, a mark and a space are formed on a recording medium such as, for example, a phase change disk, to be suitable for use in recording data. A data recording apparatus, a data recording method and a recording medium.

As a next generation high density recording medium, a phase change disk is attracting attention. As shown in Fig. 14, the recording of the information onto the phase change disk is in an amorphous state when heated to a predetermined melting point or more (for example, about 600 degrees) and quenched, and is below the melting point (for example, About 400 degrees) and gradually cool down, using the property (phase change) of the recording film to recrystallize, and information reproduction is performed using different reflectances of light in an amorphous state and a crystalline state. Here, each of the amorphous or crystalline portions is usually called a mark or a space, and therefore, it can be said that information recording on the phase change disk is performed by forming marks and spaces corresponding to the information therein.

By the way, for example, a magneto-optical disc represented by a mini disc (trademark) or the like can be directly overwritten by a magnetic field modulation method, but high-speed recording and reproduction are difficult. On the other hand, with the optical modulation method, it is possible to perform high-speed recording and reproduction, but it is necessary to use a special recording film in order to realize direct overwrite.

On the other hand, in the phase change disk, as shown in Fig. 15, the marks and spaces are already recorded by switching the laser light into intermediate power (erase level) and high power (write (write) level). Direct overwrite which simultaneously erases existing data and writes new data can be easily realized. The data is reproduced by irradiating laser light with a low power (reproduction level) such that the recording film does not cause a phase change. That is, since the reflectance of the amorphous mark is low and the reflectance of the crystalline space is high, the data is reproduced based on the light amount of the reflected light obtained by irradiating the laser light.

As described above, the phase change disk can be easily overwritten, and compared with the magneto-optical disk, (1) the pickup (optical pickup) structure is simple, (2) the reproduction signal is large, and C The high carrier to noise ratio (N), (3) the thermal conductivity of the recording layer is small, and the erasing operation temperature is high, making it difficult to influence the marks of adjacent tracks, and the density of the tracks can be increased. The reproducing is performed not only by the difference in reflectance but also by the phase difference of the reflected light, so that there is an advantage that the density can be easily increased, for example, the signal strength of minute marks can be increased.

In addition, recording of data on the phase change disk is pure thermal recording, and therefore, thermal management at the time of recording and erasing data becomes the most important to realize high density recording.

As a recording method of data on a phase change disk, there is a mark edge recording method which allocates information to both lengths by forming marks and spaces of various lengths. According to this mark edge recording method, in order to form a relatively long mark, laser light at a recording level may be irradiated for a long time. In this case, due to the heat storage effect of the recording film, the second half of the mark has a width in the radial direction of the disc. Thick tear marks are formed. When reproducing such tear marks, the error rate increases because the edges of the end portions thereof are displaced at the ideal positions.

Therefore, in the latter half of the mark, a recording method that weakens the amount of irradiation light in the latter half of the mark by driving light emitting means such as a laser diode that generates laser light with a multipulse so that the width in the radial direction is not widened (A There is).

According to this recording method A, as shown in Fig. 16A, when the pulse width corresponding to one clock (data rate) is T, the mark of length nT (where n is an integer) is It forms by driving a laser diode by the signal A shown by following formula (Hereinafter, the signal for driving light emitting means, such as a laser diode, is suitably called a recording pulse).

A = 1.5 M + (n-2) (0.5 S + 0.5 M) + 0.5 S... (One)

Here, M means the H level of the length T, and S means the L level of the length T (M may correspond to L level and S may correspond to H level).

Therefore, in the case where the data (Fig. 16 (B)) is, for example, 2M, that is, n = 2, in the formula (1), the recording pulse A (1.5 levels of 1.5T + H level (recording) Level) and L level (clear level) of 0.5T), the laser diode is driven (Fig. 16 (C)). In addition, when the data (Fig. 16 (B)) is, for example, 3M, that is, when n = 3, the laser diode is caused by the write pulse A of 1.5M + 0.5S + 0.5M + 0.5S. Is driven (Fig. 16 (C)). In addition, when the data (Fig. 16 (B)) is 5M, that is, when n = 5, 1.5M + 3 (0.5S + 0.5M) + 0.5S (= 1.5M + 0.5S + The laser diode is driven by the write pulse A of 0.5M + 0.5S + 0.5M + 0.5S + 0.5M + 0.5S (Fig. 16 (C)).

In addition, in the recording method A (the same applies to the recording method B described later), the recording pulse A for the nS portion of the data is nS as it is.

However, in the recording method A, since the amount of irradiation light is weak at the latter part of the mark, the edge of the terminal part becomes thermally unstable, and in particular, when the linear velocity at the time of recording is high, the variation of the position is remarkable. There was a problem to get rid of.

Thus, for example, "Review of the high-speed recording rate and high-density recording system for phase change disks", Television Society Technical Report, Urumiya et al., ITE Technical Report Vol. 17, No. 79, PP.7-12, VIR'93-83, (Dec. 1993) (hereinafter referred to as Document 1), and Japanese Patent Laid-Open No. 6-295440 (hereinafter referred to as Document 2), Japanese Patent Laid-Open No. 7-129959 Japanese Patent Application Publication (hereinafter referred to as Document 3) and the like disclose a recording method B for irradiating a certain amount of light to an end portion of a mark.

According to this recording method B, a mark of length nT is formed by driving a laser diode with a recording pulse B represented by the following equation.

A = 1.0M + (n-2) (0.5S + 0.5M) + 0.5M + 0.5S

Therefore, when the data (Fig. 16 (B)) is, for example, 2M, i.e., n = 2, in the formula (2), recording of 1.0M + 0.5M + 0.5S = 1.5M + 0.5S By the pulse B, the laser diode is driven (Fig. 16 (D)). In addition, when data (FIG. 16 (B)) is 3M, for example, when n = 3, 1.0M + 0.5S + 0.5M + 0.5M + 0.5S = 1.0M + 0.5S + 1.0 The laser diode is driven by the write pulse B of M + 0.5S (Fig. 16 (D)). In addition, when the data (Fig. 16 (B)) is 5M, that is, when n = 5, 1.0M + 3 (0.5S + 0.5M) + 0.5M + 0.5S (= 1.0M + The laser diode is driven by the write pulse B of 0.5S + 0.5M + 0.5S + 0.5M + 0.5S + 1.0M + 0.5S) (Fig. 16 (D)).

However, also in the case of the recording method B, for example, thermal interference occurs between portions where short marks and spaces such as 2T and 3T are formed, in particular, marks between which the short spaces are interposed, and the position of the edges thereof. There is a problem that the deviation occurs at an ideal position, whereby the error rate is increased.

Thus, in Documents 1 and 3 described above, data corresponding to a short mark and a space is detected, and the recording pulse corresponding to such data is changed by changing the position of the edge of the start end and the edge of the end part. Disclosed is a method (recording compensation method) for recording by compensating for the positional shift of an edge due to thermal interference or the like.

Fig. 17 shows a configuration of an example of a conventional write compensation circuit for performing such write compensation.

In the start pulse generator 101, the gate generator 102, the end pulse generator 103, and the mark / space length detector 104, modulation data obtained by modulating information to be recorded (Fig. 16 (B)). ) Is supplied.

Here, the modulated data is obtained by modulating the information by combining, for example, (1, 7) Run Length Limited (RLL) and Non Return to Zero Inverted (NRZI), and therefore, the modulated data is isolated. There is no reversal. The minimum inversion width or the maximum inversion width is 2 or 8, respectively (hence, in the above case, n in the formula (2) becomes a value in the range of 2 to 8).

In the start pulse generator 101, the pulse width rising at the position delayed by 0.5T from the rising edge of the modulated data is generated by the start pulse of IT (a pulse corresponding to the first term 1.0M of the right side in Equation (2)). Then, it is supplied to the OR gate 110 through the delay line 108.

In the gate generator 102, a gate signal having a pulse width corresponding to n in Expression (2) is generated from the modulated data and supplied to one input terminal of the AND gate 109. A clock (Fig. 16A) is supplied to the other input terminal of the AND gate 109, and the AND gate 109 calculates the logical product of the clock and the gate signal. Thus, in the AND gate 109, a burst pulse (a pulse corresponding to the one except the last 0.5M in the second term (n-2) (0.5S + 0.5M) on the right side in the formula (2) ) Is generated and supplied to the OR gate 110.

Further, in the terminal pulse generator 103, the pulse width falling at the position of the falling edge of the modulation data is 1T terminal pulse (second term (n-2) on the right side in equation (2) (0.5S + 0.5M). ) And a pulse corresponding to the sum of 0.5M and the third term 0.5M) are generated and supplied to the OR gate 110 through the delay line 107.

In the OR gate 110, the logical sum of the start pulse, the burst pulse, and the end pulse is calculated, whereby the write pulse B (Fig. 16 (D)) given in equation (2) is generated and output.

On the other hand, the mark / space length detector 104 detects from the modulated data corresponding to a short mark and a space, such as 2T or 3T, for example, and the detection result is supplied to the selectors 105 and 106. In the selectors 105 and 106, a delay amount for delaying the start pulse or the end pulse is determined based on the detection result from the mark / space length detector 104, and is supplied to the delay lines 107 or 108, respectively.

Each of the delay lines 107 or 108 is output by being delayed by a delay amount from which the start pulse or the end pulse is supplied from the selector 105 or 106.

As described above, with respect to the recording pulse corresponding to the data corresponding to the short mark and the space, the position of the edge of the start end and the edge of the end part is changed, whereby the position of the edge resulting from thermal interference or the like. Recording compensation of misalignment is performed.

By the way, data is recorded on an optical disc, a magneto-optical disc, etc. in a CAV (Constant Angular Velocity) method. In the CAV system, since the angular velocity (rotational speed of the disc) is constant, if the data rate is constant, the linear density is high on the inner circumferential side of the disc and low on the outer circumferential side, and as a result, the recording capacity as a whole becomes small.

On the other hand, when data is recorded by the CLV (Constant Linear Velocity) method, the linear velocity is constant. Therefore, when the data rate is constant, the linear density is also constant. As a result, the recording capacity as a whole can be increased. However, in the CLV method, it is necessary to continuously change the rotation speed of the spindle motor for rotating the disk from the innermost to outermost circumferences, which complicates the control system.

Therefore, it is possible to rotate at a constant angular velocity, that is, a method that combines both the advantages of the CAV method, which is simple to control, and the advantages of the CLV method, which can increase the recording capacity. The MCAV (Modified CAV) (MZ-CAV (Multi -Zone- CAV)).

In the MCAV system, as in the CAV system, rotational driving is performed at a constant angular velocity, but the disk is divided into several regions (for example, about 50) from the innermost to outermost circumferences, and the outer circumferential side. Recording is performed at a higher data rate. The data rate is controlled so that the linear density in the innermost periphery of each area is constant, whereby the recording capacity can be increased like the CLV method.

When high density recording is realized by the phase change disk, it is preferable to adopt a CLV method having a constant linear velocity that can cope with constant recording compensation from the viewpoint of recording compensation. That is, since the recording of data to the phase change disk is pure thermal recording, if the linear velocity is constant, it ends when constant recording compensation is performed.

However, in the CLV system, in the case of traverse (track jump), it is necessary to change the rotational speed of the disc from a value suitable for the position before traverse to a value suitable for the position after traverse. Can't. For this reason, when compared with a tape-shaped recording medium such as a video tape, there is a drawback that the speed of random access, which is an important feature of the disc, is slow.

Therefore, in order to prevent the use of the phase change disk from being limited by such drawbacks, there is a method that adopts the MCAV system which has a large recording capacity and enables fast random access.

However, in the MCAV system, since the linear velocity changes from the innermost to the outermost, it was difficult to cope with constant recording compensation.

The present invention has been made in view of such a situation, and is intended to facilitate recording compensation corresponding to the linear velocity.

The data recording apparatus described in the present invention is a data recording apparatus for recording data on a recording medium in accordance with a recording pulse obtained by synthesizing a start pulse, a burst pulse, and an end pulse, and by changing the position of the start edge of the start pulse. The start pulse change means (for example, the multi-pulse generator 16, the programmable delay line 18 and the write signal generator 21, etc.) shown in FIG. End pulse changing means (e.g., the multi-pulse generator 16, the programmable delay line 17 and the recording signal generator 21, etc.) for changing the pulse width by changing the position; Characterized in that.

The data recording apparatus described in the present invention further includes recording means (for example, pickup 3 shown in Fig. 1) for recording data by forming marks and spaces in the recording medium in accordance with recording pulses, Each of the start pulse change means or the end pulse change means changes the position of the start edge or the end edge based on the relative speed between the recording medium and the recording means.

The data recording apparatus according to the present invention is a data recording apparatus for recording data by forming a mark and a space into a recording medium in accordance with a recording pulse corresponding to the data, wherein the pulse width for one clock having the beginning of the data as the beginning of the data A start pulse generating means (e.g., DFF (D flip-flop) 52, 54, AND gate 56, etc.) shown in FIG. End pulse generating means (for example, DFFs 51 and 52 and AND gates 57 and the like shown in FIG. 7) for generating end pulses having a pulse width equivalent to a clock, and a first delay amount x of data; A first delay means (e.g., programmable delay line 18 shown in FIG. 7) delaying by as much as a second delay amount (y) of the data that is temporally preceded by a predetermined amount of clock. 2 delay means (e.g., the programmable delay line shown in FIG. (17) and the like, and the recording pulse generating means (for example, shown in FIG. 7) that generates the recording pulse by logically calculating the outputs of the start pulse generating means, the end pulse generating means, and the first and second delay means. The OR gate 58 and the AND gates 61, 62, etc.), and the pulse width corresponding to one clock is T, and one of the H or L levels of the write pulse of length T is M, the other. When S is expressed as S, a recording pulse whose length corresponds to a mark of nT (where n is an integer) is expressed by the formula xS + (1.5-x) M + (n-2) (0.5S + 0.5M) + yM + (0.5-y) S or the formula xS + (1.5-x) M + (n-3) (0.5S + 0.5M) + 0.5S + yM + (1.0-y) S.

The data recording apparatus according to the present invention is characterized in that the recording pulse generating means includes first calculation means (for example, an OR gate shown in FIG. (58), etc.), second calculating means (e.g., AND gate 61 shown in FIG. 7) for calculating the logical product of the outputs of the first and second delay means, and first and second calculations. And third computing means (e.g., AND gate 62 shown in FIG. 7) for calculating the logical product of the output of the means.

The data recording apparatus described in the present invention further includes delay setting means (for example, the microcomputer 11 shown in Fig. 3) for adaptively setting each of the first or second delay amounts x or y. Characterized in that.

The data recording apparatus described in the present invention further includes recording means (for example, pickup 3 shown in Fig. 1) for recording data by forming marks and spaces in the recording medium in accordance with recording pulses, The delay amount setting means sets each of the first or second delay amounts x or y based on the relative speed between the recording medium and the recording means.

The data recording apparatus described in the present invention includes measuring means for measuring the number of stages of an inverter required for a predetermined delay amount (for example, the DFF 81, the unit delay element 82, and the OR gate 83 shown in FIG. 10). And selectors 84, 86, NOR gates 87, and RSFF (RS flip-flop) 88).

Fig. 1 shows the configuration of one embodiment of a disk drive to which the present invention is applied.

The disk 1 is, for example, a phase change disk as described above, and is rotationally driven by the spindle motor 2. The spindle motor 2 constitutes a spindle servo system, and rotates the disk 1 at a constant rotational speed (rotational speed).

At the time of data recording, for example, as described above, the data to be recorded is supplied to the recording circuit 4 with modulated data modulated by a modulation method in which (1, 7) RLL and NRZI are combined. . In the recording circuit 4, recording compensation corresponding to the modulated data is generated and supplied to the pickup 3. The pickup 3 drives light emitting means such as a built-in laser diode in accordance with a recording pulse. Thereby, the disk 1 is irradiated with the laser beam of the power as described with reference to FIG. 15 according to a recording pulse, and the mark and space corresponding to the data input into the recording circuit 4 are formed, for example. For example, data is recorded by the mark edge recording method.

On the other hand, at the time of reproduction of data, the pickup 3 is irradiated with the laser light of the reproduction level to the disk 1, and the reflected light is received. In the pickup 3, the received reflected light is photoelectrically converted, and the resulting RF (Radio Frequency) signal is supplied to the reproduction circuit 5. In the reproduction circuit 5, predetermined processing is performed on the RF signal, and the modulated data is reproduced and output. This modulated data is restored to its original state in a circular recovery circuit (not shown), and becomes original data.

In addition, in this embodiment, the disk 1 is divided into several areas (for example, about 50 or so) from the innermost circumference to the outermost circumference, for example, and as much as the area on the outer circumference side, Recording is performed at a high data rate. The data rate is such that the linear density in the innermost circumference of each area is controlled to be constant. Therefore, the recording and reproducing of data are performed on the disc 1 by the MCAV method.

Next, with reference to FIG. 2, the write compensation in the write circuit 4 of FIG. 1 is demonstrated.

FIG. 2 is a waveform diagram as shown in FIG. 16, and as described above, according to the recording method A or B represented by the formula (1) or (2), under the clock as shown in FIG. Given the modulation data as shown in figure B, a write pulse A or B as shown in figure C or D, respectively, is generated.

Here, according to the recording method A, as described above, when the linear speed of the disc 1, that is, the relative speed of the disc 1 and the pickup 3 is high, the positional variation of the mark edge is remarkable. However, this is not the case when the linear velocity is low (for example, about 4 m / s (meter / second)), and therefore it is known to be suitable for low linear velocity. In addition, the recording method B is not suitable when the linear velocity is low, but is known to be suitable when the linear velocity is high (for example, about 10 m / s).

Therefore, as in the MCAV system, when the linear velocity changes from the innermost to the outermost circumference from low speed to high speed, the recording pulse is also changed from that obtained by the recording method A to that obtained by the recording method B. In this case, recording compensation corresponding to the linear velocity can be performed.

Thus, as shown by the dotted line in Fig. 2C, the recording circuit 4 has the starting edge or falling edge of each of the start pulse or the end pulse of the start pulse or the end pulse constituting the write pulse A according to the write method A. FIG. By changing the position, their pulse width is changed. As a result, the recording pulse is changed to correspond to the linear velocity, for example, to the area. Alternatively, as shown by the dotted line in Fig. 2D, the recording circuit 4 has the rising edge or falling edge of each of the start pulse and the end pulse of the start pulse or the end pulse constituting the write pulse B according to the write method B. By changing the positions, the pulse widths thereof are changed, whereby the recording pulses are changed corresponding to the linear velocity, for example, the area.

Next, FIG. 3 shows a configuration example of the write circuit 4 of FIG.

The microcomputer 11 constitutes the recording circuit 4 by various signals CS, WR, OW, AB [15: 0], CLK, D [7: 0], Z [7: 0], and the like. To control each block. Here, for example, the notation data D [7: 0] means the 0th to 7th bits of the data D. Thus, when data D is composed of 8 bits, data D [7: 0] represents data D itself. In addition, for example, the notation "data D [0]" means the 0th bit of data (D). In addition, it is assumed that the 0th bit represents LSB (least significant bit), for example.

That is, when the microcomputer 11 writes the data D [7: 0] to the RAM (Random Access Memory) 15, for example, the chip selector signal CS that is usually at the L level, for example. It is made to make H level. The microcomputer 11 is configured to set the write signal WR to H or L level, respectively, when writing the data D to the RAM 11 or when reading the data D. FIG. In addition, the microcomputer 11 is configured to output an overwrite signal OW indicating whether or not to directly overwrite, that is, whether to write modulation data.

In addition, when the microcomputer 11 reads and writes data to and from the RAM 15, the microcomputer 11 is configured to output an address signal AB [15: 0] for designating the address. In addition, the microcomputer 11 is configured to supply the clock CLK to the necessary one of the blocks constituting the recording circuit 4. In addition, the microcomputer 11 outputs the data D [7: 0] to be written to the RAM 15 and receives the data D [7: 0] read out from the RAM 15. In addition, the microcomputer 11 detects the area | region to which the pickup 3 is irradiating a laser beam, and outputs area data Z [7: 0] which shows the area | region.

3, for example, the address signal AB [15: 0] is a 15-bit signal, and the data D [7: 0] and the area data Z [7: 0] are 8-bit signals. It is.

In the microcomputer 11, the controller 12 is provided such that the chip selector signal CS, the write signal WR, or the overwrite signal OW are supplied to the input terminal CSIN, WRIN, or OWIN, respectively. have. In the controller 12, among the 12-bit data AA [11: 0] output by the shifter 14, data AA [7: 4] composed of the fourth to seventh bits is input terminal D [3: 0]. ] To be supplied.

The controller 12 is a signal to be output from each of its output terminals OE, CS or WR in the chip selector signal CS, the write signal WR and the overwrite signal OW input thereto (hereinafter, appropriately). The signal output from the output terminal OE is referred to as an enable signal OE, and the signal output from the output terminals CS and WR is a chip selector signal CS input to the controller 12. Since they correspond to the write signals WR, these signals are also configured to generate and output chip selector signals CS and write signals WR, respectively, as appropriate. Further, the controller 12 detects the rising edge or the falling edge of the modulated data D based on the data AA [7: 4] and at that timing, for example, only one clock, from H level to H The rising edge signal RISE or FALL, which becomes the level, is output at its output terminal RISE or FALL, respectively.

The selector 13 is, for example, a 16-bit selector, where the overwrite signal OW and the address signal AB [15: 0] are input terminals A / B and B in the microcomputer 11. [15: 0] each to be supplied. The selector 13 further includes data AA [3: 0] and AA [11: 8 consisting of the 0th to 3rd bits and the 8th to 11th bits of the data AA [11: 0] output by the shifter 14. ] Is the lower 8 bits, and 16 bits of data having the upper 8 bits of the area data Z [7: 0] outputted by the microcomputer 11 (this data is the same as the RAM (address signal AB [15: 0]). Since it becomes the 15-bit address of 15), the address signal AB '[15: 0] is suitably described below) so as to be supplied to the input terminal A [15: 0].

The selector 13 selects the address signals AB [15: 0] or AB '[15: 0], respectively, at the output terminal C [15: 0] when the overwrite signal OW is at the L or H level. And output as the address signal ADR [15: 0].

The shifter 14 is, for example, a 12-bit shifter, in which modulation data DATA and a clock CLK are supplied to each of the input terminals DIN and CLK. The shifter 14 incorporates a 12-bit register, and in synchronization with the clock CLK, stores the modulated data DATA in the LSB of the register, and copies each bit of the register into one high-order bit. That is, it is made to perform left shift of 1 bit. The stored value of the register with the shifter 14, i.e., the modulated data AA [11: 0] of parallel data in units of 12 bits, is the 0th to 3rd bits AA [3: 0], the 4th to 7th bits. Divided into AA [7: 4] and eighth to eleventh bits AA [11: 8], and as described above, the zeroth to third bits AA [3: 0] and the eighth to eleventh bits AA [11]. : 8] is supplied to the selector 13 so that the fourth to seventh bits AA [7: 4] are supplied to the controller 12.

The third bit AA [3] of the modulated data AA [11: 0] is also supplied to the multipulse generator 16.

The RAM 15 is, for example, a RAM having 16 bits of address space and storing 8 bits of data, from which the chip selector signal CS or the write signal WR is input from the controller 12. It is configured to be supplied to the terminal CS or WR, respectively. The RAM 15 is also configured so that the address signal ADR [15: 0] is supplied to the input terminal A [15: 0] from the selector 13. The data terminal DIN of the RAM 15 is configured to supply data D [7: 0] output from the microcomputer 11.

The RAM 15 stores data D [7: 0] outputted by the microcomputer 11 when the chip selector signal CS is at the H level and the write signal is at the H level, and the address signal ADR [15: 0]. The data D [7: 0] is stored from the address indicated by the address signal ADR [15: 0] when the chip selector signal CS is at the H level and the write signal is at the L level. It reads out and is output as data DO [7: 0] from the output terminal DOUT [7: 0].

In the multipulse generator 16, the third bit AA [3] of the 12-bit modulation data AA [11:] from the shifter 14 is supplied to the input terminal INDATA, and is also clocked from the microcomputer 11. CLK is supplied to the input terminal CLK.

The multipulse generator 16 generates data DATA1 serving as an end pulse, data MP serving as a burst pulse and data DATA2 serving as a start pulse based on the third bit AA [3] of the modulated data and the clock CLK. Each is output from the output terminals Q1, MP, and Q2.

The programmable delay line 17 or 18 supplies a predetermined amount y or data DATA1 or DATA2 according to the 4-bit data FALL_DATA [3: 0] or RISE_DATA [3: 0] supplied from the DFF 19 or 20, respectively. It is delayed by the amount of x), and is output from each output terminal OUT as delay data DDATA1 or DDATA2.

The DFF 19 or 20 is supplied with the lower 4 bit DO [3: 0] or the upper 4 bit DO [7: 4] out of the data DO [7: 0] output from the RAM 15 from the controller 12. Latch at the timing of edge signal FALL or rising edge signal RISE to supply to programmable delay line 17 or 18 as data FALL_DATA [3: 0] or RISE_DATA [3: 0], respectively. consist of.

The write signal generator 21 performs a logical operation using the delay data DDATA1 or DDATA2 from each of the programmable delay lines 17 or 18 and the data MP from the multipulse generator 16. In FIG. The write pulse as described above is generated and output from the output terminal REC.

The gate circuit 22 is an 8-bit, three-state gate, for example, and receives the data DO [7: 0] read from the RAM 15, and the enable signal OE output by the controller 12 is output. Is provided at the L or H level, for example, at the H level, the received data DO [7: 0] is supplied to the microcomputer 11 as the data D [7: 0].

In the recording circuit 4 configured as described above, as described later, the position of the rising or falling edge of the start pulse or the end pulse constituting the write pulse is changed by the delay amount, whereby each pulse width is changed. Is changed. In the microcomputer 11, the data D [7: 0] as the delay amount x of the start pulse and the delay amount y of the end pulse constituting the recording pulse is each linear speed, i.e., here. It is set for each area and supplied to and stored in the RAM 15. The mode in which such processing is performed is called a data setting mode. In direct overwrite (Giroxy), a write pulse with a delay is generated based on the data D [7: 0]. The mode in which such a process is performed is called an overlait mode.

That is, in the data setting mode, the microcomputer 11 sets both directions of the chip selector signal CS and the write signal WR to the H level, and the overwrite signal OW to the L level.

Further, the microcomputer 11 sets four bits of RISE_DATA [3: 0] or FALL_DATA [3: 0] respectively corresponding to the appropriate delay amount x or y for each region, and differs from RISE_DATA [3: 0]. 8 bits of data D [7: 0] are generated using 4 bits and FALL_DATA [3: 0] as the lower 4 bits.

Here, the recording compensation needs to be performed in correspondence with the linear velocity, in addition to the mark or space length to be formed, in particular in response to the short mark or space as described above.

Thus, in the microcomputer 11, a suitable delay amount for each area and a length of a mark and a space to be formed, that is, one suitable for the modulated data to be recorded are set.

Specifically, for example, in the case of paying attention to any 12 consecutive bits of the modulated data, an appropriate delay is based on a total of 8 bits of the upper 4 bits and the lower 4 bits and the bidirectional direction of the region where the modulated data is recorded. Data D [7: 0] as the quantity is obtained.

This data D [7: 0] is supplied from the microcomputer 11 to the RAM 15.

The data D [7: 0] is preferably obtained by, for example, experimenting in advance, and stored in a ROM (Read Only Memory) or the like (not shown). In this case, the microcomputer 11 may read the data D [7: 0] from the ROM in the data setting mode.

As described above, when the microcomputer 11 pays attention to any successive 12 bits of the modulated data, the data AD1 composed of 8 bits of the upper 4 bits and the lower 4 bits, and the modulation data are recorded. When data D [7: 0] as an appropriate delay amount is obtained based on both directions of the area z, the 8-bit data AD1 is a lower address and the area z is shown. For example, the 16-bit address signal AB [15: 0] is generated as the upper address using the 8-bit data AD2 and output to the selector 13.

As described above, in the present case, since the overwrite signal OW is at the L level, in the selector 13, the address signal AB [15 from the microcomputer 11 input to the input terminal B [15: 0]. : 0] is selected and supplied to the RAM 15 as the address signal ADR [15: 0].

On the other hand, when the controller 12 receives the H level chip selector signal CS and the write signal WR and the L level overwrite signal OW, the controller 12 selects the H level chip selector signal CS and the write signal ( WR) is output to the RAM 15.

Therefore, in the RAM 15, the data D [7: 0] is stored (written) at the address indicated by the address signal ADR [15: 0].

In the same manner, the RAM 15 stores therein a delay amount suitable for each area, and the length of the mark and space to be formed, that is, data D [7: 0] of each value corresponding to that suitable for the modulation data to be recorded. .

The data D [7: 0] at a certain address ADR [15: 0] is transferred from the RAM 15 to confirm whether or not the data D [7: 0] stored in the RAM 15 is correct. When reading, the microcomputer 11 sets the chip selector signal CS to the H level, and the write signal WR and the overwrite signal OW to the L level. The microcomputer 11 also outputs the address AB [15: 0] to the selector 13. In this case, the controller 12 outputs the level chip selector signal CS and the L level write signal WR to the RAM 15, and simultaneously gates the H level enable signal OE. Output to the circuit 22. The selector 13 also selects the address AB [15: 0] from the microcomputer 11 and outputs it to the RAM 15 as the address signal ADR [15: 0].

When the RAM 15 receives the H level chip selector signal CS, the L level write signal WR, and the address signal ADR [15: 0], the RAM 15 receives the address signal ADR [15: 0] as described above. Data D [7: 0] is read from the corresponding address and output to the gate circuit 22 as data DO [7: 0]. As described above, the gate circuit 22 outputs the data from the RAM 15 to the microcomputer 11 when the enable signal OE of the H level is received. As a result, the RAM 15 The data DO [7: 0] read from is supplied to the microcomputer 11.

Next, in the overwrite mode, the microcomputer 11 sets the chip selector signal CS and the overwrite signal OW to H level, and the write signal WR to L level. The microcomputer 11 also recognizes the area that the pickup 3 is accessing, and supplies the selector 13 with the area data Z [7: 0] corresponding to the area.

In this case, the shifter 14 is supplied with modulated data DATA synchronized with the clock CLK. The shifter 14 stores the modulated data DATA supplied thereto at the timing of the clock CLK in the LSB of the 12-bit register embedded therein, and shifts the storage value of the register, resulting in a 12-bit unit. Output the modulated data AA [11: 0]. Of these 12 bits of modulation data AA [11: 0], the 0th to 3rd bits AA [3: 0] and the 8th to 11th bits AA [11: 8] are assigned to the selector 13, and the third bit AA. [3] is supplied to the multipulse generator 16, and the fourth to seventh bits AA [7: 4] are supplied to the controller 12, respectively.

The area data Z [7: 0] output by the microcomputer 11 and the modulation data AA [3: 0] and AA [11: 8] output by the shifter 14 are arranged as one 16-bit data. That is, as described above, for example, 16-bit data (address signal) listed in order of area data Z [7: 0], modulation data AA [3: 0], and AA [11: 8] from the most significant bit. ) AB '[15: 0] is configured and supplied to the input terminal A [15: 0] of the selector 13.

In the present case, since the overwrite signal OW is at the H level, the selector 13 selects the address signal AB '[15: 0] supplied to the input terminal A [15: 0], and the address signal ADR [ 15: 0] to the RAM 15.

On the other hand, when the controller 12 receives the chip selector signal CS at the H level and the write signal WR at the L level, the controller 12 outputs the chip selector signal CS and the write signal WR, such as those, to the RAM 15. Output to

Therefore, in the above case, in the RAM 15, data D [7: 0] is read from the address corresponding to the address signal ADR [15: 0] and output as data DO [7: 0]. That is, in the above case, as the delay amount suitable for the area (linear speed) for recording the modulation data, the data DO [7: 0] corresponding to that suitable for the modulation data is output from the RAM 15. Of these data DO [7: 0], the upper four bits DO [7: 4] are supplied to the DFF 20 and the lower four bits DO [3: 0] are supplied to the DFF 19.

In addition, upon receiving the modulation data AA [7: 4], the controller 12 detects the rising edge and the falling edge of the modulation data based on the modulation data AA [7: 4]. That is, in the present embodiment, since the modulation data is obtained by the combination of the (1, 7) RLL and the NRZI as described above, there is no isolated inversion. For this reason, if there is a rising edge in the modulation data, in the process of shifting the modulation data in the shifter 14, AA [7] = 0, AA [6] = 0, AA [5] = 1, AA [4 ] = 1 must occur. If there is a falling edge in the modulation data, in the process of shifting the modulation data in the shifter 14, AA [7] = 1, AA [6] = 1, AA [5] = 0, AA [4] Must always be zero.

Thus, if the controller 12 detects AA [7] = 0, AA [6] = 0, AA [5] = 1, AA [4] = 1, the controller 12 detects the rising edge and generates the rising edge signal RISE. Output In addition, when the controller 12 detects AA [7] = 1, AA [6] = 1, AA [5] = 0, AA [4] = 0, the controller 12 detects the falling edge and falls on the falling edge signal FALL. )

In addition, when the minimum inversion width of the modulated data is not 2, it is necessary to change the detection method of the rising edge and falling edge in the controller 12 correspondingly.

The falling edge signal FALL or the rising edge signal RISE is output to the DFF 19 or 20, respectively. The DFF 19 or 20 latches data D [3: 0] or D [7: 4] from the RAM 15 at the timing of the falling edge signal FALL or the rising edge signal RISE, and the data FALL_DATA. Output as [8: 0] or RISE_DATA [3: 0] to the programmable delay line 17 or 18, respectively.

On the other hand, the multi-pulse generator 16 receives data AA [3] from the shifter 14 as modulation data, generates data DATA1, DATA2, and MP from the modulation data, and each of the delay lines 17, which can be programmed. 18) and outputs to the recording signal generator 21. In the programmable delay line 17 or 18, according to the 4-bit data FALL_DATA [3: 0] or RISE_DATA [3: 0] supplied from the DFF 19 or 20, the data DATA1 or DATA2 is respectively a predetermined amount y or delayed by x) and supplied as the delayed data DDATA1 or DDATA2 to the write signal generator 21. In the write signal generator 21, based on the delay data DDATA1 or DDATA2 from each of the programmable delay lines 17 or 18 and the data MP from the multipulse generator 16, a write pulse is generated and output.

Here, in the actual circuit, the data corresponding to the falling edge or rising edge of the modulated data with respect to the programmable delay line 17 or 18 by definition (operation speed) such as the shifter 14 or the RAM 15. A shift may occur between the timing at which DATA1 or DATA2 is input and the timing at which data FALL_DATA [3: 0] or RISE_DATA [3: 0] is input. In such a case, for example, a delay circuit or the like is provided at the front end of the input terminal INDATA of the multi-pulse generation circuit 16 to which the modulation data AA [3] is inputted so that the above-described timings are made to coincide with each other. There is. In addition, this can be realized by, for example, modulating data supplied from the shifter 14 to the multipulse generator 16 to AA [2] or AA [4] instead of AA [3]. .

Next, the controller 12 will be described in detail based on FIG. 4 showing an example of the configuration of the controller 12 in FIG.

Modulation data AA [4] and AA [5] are input to the AND gate 31, where both AND (logical products) are calculated and input to one input terminal of the AND gate 33. In addition, the output of the NOR gate 35 is input to the other input terminal of the AND gate 33, and the AND of the output of the AND gate 31 and the NOR gate 35 is calculated in the AND gate 33. , The calculation result is output as the falling edge signal FALL. Modulation data AA [6] and AA [7] are input to the NOR gate 35, where both NORs (negative logical sums) are calculated.

Therefore, only when AA [7] = 1, AA [6] = 1, AA [5] = 0, AA [4] = 0, the falling edge signal FALL of the H level 1 from the AND gate 33 is FALL. ) Is output.

Modulation data AA [6] and AA [7] are input to the AND gate 32. Both ANDs are calculated therein and input to one input terminal of the AND gate 34. In addition, the output of the NOR gate 36 is input to the other input terminal of the AND gate 34, and the AND, which is the output of the AND gate 32 and the NOR gate 36, is calculated at the AND gate 34. , The operation result is output as the rising edge signal RISE. The NOR gate 36 is configured to input modulation data AA [4] and AA [5], where both NORs are calculated.

Therefore, only when AA [7] = 0, AA [6] = 0, AA [5] = 1, AA [4] = 1, the rising edge signal RISE of H level 1 from AND gate 34 ) Is output.

On the other hand, the chip selector signal CS in the microcomputer 11 is connected to one input terminal of the OR gate 38 and one input terminal of the AND gate 39, and the overwrite signal OW is OR gate 38. The write signal WR is input to one input terminal of the AND gate 40, respectively, to the other input terminal and the inverter 37.

The OR gate 38 calculates an OR (logical sum) of the chip selector signal CS and the overwrite signal OW, and outputs the result of the operation as the chip selector signal CS. Therefore, the chip selector signal CS output by the controller 12 becomes H level when either one of the chip selector signal CS or the overwrite signal OW output by the microcomputer 11 is H level, When both of them are L level, it will become L level.

In the inverter 37, the overwrite signal OW is inverted and supplied to the other input terminal of the AND gate 39 and the other input terminal of the AND gate 40. In the AND gate 39, the AND of the chip selector signal CS and the output of the inverter 37 are calculated, and the result of the calculation is output as the enable signal OE. Therefore, the enable signal OE becomes H level only when the chip selector signal output from the microcomputer 11 is at the H level, and the overwrite signal OW is at L level. .

In the AND gate 40, the output of the inverter 37 and the AND of the write signal WR are calculated, and the result of the calculation is output as the write signal WR. Therefore, the write signal WR from which the controller 12 is output becomes H level only when the overwrite signal OW from which the microcomputer 11 is output is L level and the write signal WR is H level, In other cases, the level is L.

FIG. 5 shows an example of the configuration of the multipulse generator 16 of FIG.

The data DATA, which is the modulation data AA [3], is supplied to the DFF 51 and latched therein at the timing of the clock CLK (the timing of the clock CLK, for example, the rising edge, etc.). To the DFFs 52 and 53. The DFF 51 also supplies the inverted output (/ Q) of the latched data DATA to one input terminal of the AND gate 57.

The DFF 53 is configured to latch the output of the DFF 51 at the output timing of the inverter 55 (eg, the timing of the rising edge of the output of the inverter 55, for example). ) Is supplied to supply a clock CLK. Therefore, in the DFF 53, data that is preceded in time by 1/2 clock is latched from the data latched by the DFF 52 described later. Data advanced by this half clock is output as data DATA1.

On the other hand, in the DFF 52, the output of the DFF 51 is latched at the timing of the clock CLK, and is output as the data DATA2, and at the same time, one input terminal of the DFF 54 and the AND gate 56 and the AND gate ( 57) to the other input terminal. Also in the DFF 54, the output of the DFF 52 is latched at the timing of the clock CLK, and its inverted output is supplied to the other input terminal of the AND gate 56.

In the AND gate 56, the AND of the output of the DFF 52 and the inverted output of the DFF 54 is calculated and supplied to the OR gate 58. In addition, the AND gate 57 calculates the AND of the inverted output of the DFF 51 and the output of the DFF 52, which is also supplied to the OR gate 58.

In addition to the outputs of the AND gates 56 and 57, the OR gate 58 is supplied with a clock CLK, where these ORs are calculated, and the result of the calculation is output as data MP.

FIG. 6 shows an example of the configuration of the recording signal generator 21 of FIG.

The data DDATA1 or DDATA2 from each of the programmable delay lines 17 or 18 are all input to the AND gate 61. In the AND gate 61, the AND of the data DDATA1 and DDATA2 is calculated, and the AND gate 62 Is supplied to one of the input terminals. Data MP is input to the other input terminal of the AND gate 62. As the AND gate 62, the output of the AND gate 61 and the AND of the data MP are calculated. Is output as a recording pulse.

Next, with reference to FIGS. 7 and 8, the processing of the multipulse generator 16, the programmable delay lines 17 and 18 and the write signal generator 21 of FIG. 3 will also be described.

7 shows the programmable delay lines 17 and 18 in addition to the multi-pulse generator 16 shown in FIG. 5 and the write signal generator 21 shown in FIG. 6, and FIG. The waveform of the signal is shown.

The clock CLK (FIG. 8A) from the microcomputer 11 (FIG. 3) is supplied to the DFFs 51, 52, and 54, the inverter 55, and the OR gate 58. As shown in FIG. The modulated data AA [3] is supplied to the DFF 51 and sequentially latched at the rising edge of the clock CLK in the DFF 51 and the DFFs 52 and 54.

Here, the latch output Q of the DFF 52 is represented by DATA [k], with k being a variable corresponding to time. In this case, the modulation data AA [3] supplied to the DFF 51 is data DATA [k + 2], the latch output of the DFF 51 is data DATA [k + 1], and the latches of the DFF 54. The output can be represented by data DATA [k-1], respectively.

On the other hand, in the inverter 55, the clock CLK is inverted and supplied to the DFF 53 (clock terminal of the DFF 53). The input terminal D of the DFF 53 is supplied with the data DATA [k + 1], which is the latch output of the DFF 51, and the data DATA [k + 1] is the inverted clock CLK in the DFF 53. Latches at the timing of the rising edge.

As a result, if data DATA [k] is as shown in FIG. 8 (B), for example, the latch data of DFF 53 is the above data DATA [k as shown in FIG. 8 (D). You get the data DATA [k + 1/2], which is 1/2 clock ahead.

The data DATA [k] or DATA [k + 1/2], which is the latch output of the DFF 52 or 53, is supplied to the programmable delay line 18 or 17, where there is a small amount x or y, respectively. Delay, whereby data DATA [k] (FIG. 8 (B)) or DATA [k + 1/2] (FIG. 8 (D)) is different from that shown in FIG. 8 (C) or (E), respectively. The same delay data DDATA [k] (DDATA2 in FIG. 3) or DDATA [k + 1/2] (DATA1 in FIG. 3). Thus, both of the delay data DDATA [k] and DDATA [k + 1/2] are supplied to the AND gate 61.

In the AND gate 61, the AND of the delay data DDATA [k] (Fig. 8 (C)) and DDATA [k + 1/2] (Fig. 8 (E)) is calculated, whereby Fig. 8F is obtained. The gate signal GATE as shown in FIG. This gate signal GATE is supplied to the AND gate 62.

Here, for the data DATA [k] of nM (H level of nT width), a gate signal GATE having a width of (n-x + y) T is generated.

On the other hand, in the DFF 54, the data DATA [k] from the DFF 52 is latched, so that the data DATA [k-1] is delayed by one clock. The inverted output! DATA [k-1] ("! Indicates an inversion) and is supplied to one input terminal of the AND gate 56. The other input terminal of the AND gate 56 is supplied with data DATA [k], which is the latch output of the DFF 52, and the AND gate 56 is an AND of data! DATA [k-1] and DATA [k]. Is calculated, a start pulse (TOP) having a pulse width of one clock having the start of the data DATA [k] as the start of the circuit (this start pulse TOP is the data DATA [k). Corresponding to the derivative value at the rising edge portion of the N2) is generated and supplied to the OR gate 58.

Further,! DATA [k + 1] data in which data DATA [k + 1] is inverted from the DFF 51 is supplied to the AND gate 57, and data DATA [k] is supplied from the DFF 52. There, the AND of the data! DATA [k + 1] and DATA [k] is calculated. As a result, in the AND gate 57, as shown in Fig. 8H, an end pulse END having a pulse width of one clock whose end is the end of the data DATA [k] (this end END is Corresponds to the derivative at the falling edge portion of data DATA [k]) and is supplied to the OR gate 58.

In the OR gate 58, the clock CLK (burst pulse) (Fig. 8 (A)), the start pulse TOP (Fig. 8 (G)), and the termination pulse END (Fig. 8 (H)) supplied thereto are provided. Is calculated, and thereby data (multipulse) MP as shown in Fig. 8 (I) is generated. This data MP is supplied to the AND gate 62.

In the AND gate 62, the AND of the gate signal GATE (Fig. 8 (F)) and the data MP (Fig. 8 (I)) are calculated, whereby as shown in Fig. 8 (J). Is a recording pulse whose length corresponds to a mark of nT, the signal REC represented by the formula xS + (1.5-x) M + (n-2) (0.5S + 0.5M) + yM + (0.5-y) S Is generated.

Thus, for example, when x = y = 0, the recording pulse is represented by the formula 1.5M + (n-2) (0.5S + 0.5M) + 0.5S, which is described in the above-described recording scheme A. Is the same as

Further, for example, when x = y = 0.5, the recording pulse is represented by the formula 1.0M + (n-2) (0.5S + 0.5M) + 0.5M + 0.5S, which is the above-described recording method (B The same as in the case of).

From the above, by varying the delay amounts x and y in the range of 0.0 to 0.5 with x = y, the recording signal A (i.e., according to the linear velocity (here, the region as described above)) is described. A recording method (recording compensation method) capable of continuously changing between Figs. 2C and 2B (Fig. 2D) can be realized. Therefore, it is possible to easily perform recording compensation corresponding to the linear velocity, for example, to realize a system having a large recording capacity by the MCAV and enabling high-speed random access.

In addition, the delay amount (x, y) is changed not only based on the linear velocity but also on the modulation data string, and in particular, recording compensation for edge misalignment caused by thermal interference or the like for data corresponding to short marks and spaces. It is possible to do this.

In addition, when the delay amounts (x, y) are changed in the range of 0.0 to 0.5 as described above, the pulse widths of the start pulse and the end pulse vary in the range of 1.0T to 1.5T, but the delay amount ( In the case where x, y) is changed to other values, for example, in the range of 0.0 to 1.0, the pulse widths of the start pulse and the end pulse change in the range of 0.5T to 1.5T.

In the above-described write compensation circuit of FIG. 17, the write pulse obtained as described above has only a change in the position of the edge and a constant pulse width in addition to the positions of the start pulse and the end pulse edge. It is fundamentally different from the recording pulse obtained from.

That is, in the above-described recording pulse in Fig. 17, the start pulse and the end pulse only move back and forth with a constant pulse width. On the other hand, in the recording pulse obtained from the recording circuit 4, the positions of the rising edge of the start pulse and the falling edge of the termination pulse change, and accordingly, the respective pulse widths also change. As a result, although the scale of the recording circuit 4 is almost the same as in the conventional case, recording compensation with a large variable range and a large degree of freedom is possible.

In the case where the disk drive of FIG. 1 is incorporated into the system, the recording circuit 4 is preferably IC integrated into one chip. In addition, IC is particularly preferable in terms of cost, for example, by a CMOS process. However, at the time of IC, it becomes a problem how to constitute programmable delay lines 17 and 18 with good precision in the IC.

That is, for example, when the programmable delay lines 17 and 18 are configured by connecting a plurality of inverters to a cascade and setting the delay amounts x and y by the number of connected stages, and the like. In some cases, variations in the amount of delay of about one to three times occur due to various factors such as the temperature, speed, and power supply voltage of the CMOS process. Therefore, always making it possible to obtain a desired delay amount (x, y) becomes an important problem in CMOS-ICting the write circuit 4.

Thus, the recording circuit 4 can be configured, for example, as shown in Fig. 9, whereby it can be realized as an IC of one chip.

That is, FIG. 9 shows another configuration example of the recording circuit 4. In addition, in the figure, the same code | symbol is attached | subjected about the part corresponding to the case in FIG. 3, and the description is abbreviate | omitted suitably below. In other words, the write circuit 4 is provided with selectors 71 and 72 newly provided, and instead of the programmable delay lines 17 or 18, programmable delay lines 73 or 74 are provided, respectively. Basically, it is comprised like the case in FIG.

In addition, in the embodiment of FIG. 9, the microcomputer 11 transmits and receives the signals DL_TEST and receives the signals FLAG1 and FLAG2 in addition to transmitting and receiving the signals described with reference to FIG. 3. Control according to the present invention is also performed.

In addition, in the embodiment of Fig. 9, RISE_DATA and FALL_DATA corresponding to the delay amounts (x, y) are 6 bits instead of 4 bits. Accordingly, the RAM 15 has 12 (= 6 + 6) bits. RAM. Further, the DFF 19 or 20 latches the lower 6 bit DO [5: 0] or the upper 6 bit DO [11: 6] of the 12 bit data DO [11: 0] output from the RAM 15, respectively. It is made to

The selector 71 is, for example, a 6-bit selector. In the microcomputer 11, the signal DL_TEST and the lower 6 bits [5: 0] of the data D [11: 0] are input terminals A thereof. / B and A [5: 0], respectively. In addition, the latch output of the DFF 19 is supplied to the input terminal B [5: 0] of the selector 71. The selector 71 selects an input to the input terminal A [5: 0] or B [5: 0] when the signal DL_TEST is 1 or 0, for example, and the output terminal C [5: 0]. That is, the selector 71 is the lower 6 bits [5: 0] of the data D [11: 0] from the microcomputer 1 or RAM latched by the DFF 19 when the signal DL_TEST is 1 or 0. The lower 6 bits DO [5: 0] of the data DO [11: 0] read from 15) are respectively selected and output. The output of the selector 71 is supplied to the programmable delay line 73 as data FALL_DATA [5: 0] corresponding to the delay amount y.

Like the selector 71, the selector 72 is also a 6-bit selector. From the microcomputer 11, the signal DL_TEST and the upper six bits [11: 6] of the data D [11: 0] are included. It is configured to be supplied to the input terminals A / B and A [5: 0], respectively. In addition, the latch output of the DFF 20 is supplied to the input terminal B [5: 0] of the selector 72. The selector 72, like the selector 71, selects an input to the input terminal A [5: 0] or B [5: 0] when the signal DL_TEST is 1 or 0, for example. It outputs from the output terminal C [5: 0]. Therefore, in the selector 72, when the signal DL_TEST is 1 or 0, the upper 6 bits [11: 6] of the data D [11: 0] from the microcomputer 1, or RAM latched by the DFF 20 The upper six bits DO [11: 6] of the data DO [11: 0] read out from (15) are respectively selected and output. The output of the selector 72 is supplied to the programmable delay line 74 as data RISE_DATA [5: 0] corresponding to the delay amount x.

Programmable delay line 73 or 74, like programmable delay line 17 or 18, depends on the six bits of data FALL_DATA [5: 0] or RISE_DATA [5: 0] supplied from selector 71 or 72. The data DATA1 or DATA2 is delayed by a predetermined amount (y or x), respectively, and outputted as delay data DDATA1 or DDATA2, respectively.

In addition, the microcomputer 11 is supplied with the signals DL_TEST, the clear signal CLR, and the clock CLK to the programmable delay lines 73 and 74, where measurement processing as described later is performed. Flags FLAG2 and FLAG1 corresponding to the processing result are output.

That is, FIG. 10 shows an example of the configuration of the programmable delay line 73, and FIG. 11 shows the waveform of each part signal of the programmable delay line 73. As shown in FIG. Since the programmable delay line 74 is configured like the programmable delay line 73, the description thereof is omitted.

The inverting (/ Q) of the latch output is supplied to the input terminal D of the DFF 81, where the rising edge of the clock CLK (Fig. 11 (A)) from the microcomputer is there, for example. At the timing of, the input to its input terminal D is latched. As a result, the signal REF_SIGNAL (Fig. 11 (B)) obtained by dividing the clock CLK by two is output as the latch output Q of the DFF 81.

That is, since the duty ratio of the clock CLK is generally not 50%, the clock CLK is divided in two in the DFF 81, so that a signal REF_SIGNAL having a duty ratio of 50% is generated.

This signal REF_SIGNAL is supplied to one input terminal of the unit delay element 82 and the OR gate 83.

For example, the unit delay element (DCELL) 82 is configured by connecting the inverter INV in two stages, as shown in FIG. 12, where the signal REF_SIGNAL is somewhat delayed, and the OR gate 83 is used. Is supplied to the other input terminal. The OR gate 83 calculates an OR of the signal REF_SIGNAL and a delay slightly from the unit delay element 82, and the operation result is supplied to the input terminal B of the selector 84.

The input terminal A of the selector 84 is supplied with data DATAI (DL_IN) from the multipulse generator 16 (data DATA2 with respect to the programmable delay line 74), and the input terminal A / The signal DL_TEST from the microcomputer 11 is supplied to B. The selector 84 selects an output of the data DATA1 (DL_IN) or the OR gate 83 supplied to the input terminal A or B when the signal DL_TEST is 1 or 0, for example, and selects the output terminal ( Output from C). The output of this selector 84 is supplied to one input terminal of the delay matrix 85 and the NOR gate 87.

For example, as shown in FIG. 13, the delay matrix 85 is configured in which the unit delay elements of FIG. 12 are arranged in a matrix and connected in series. That is, in the embodiment of Fig. 13, the delay matrix 85 is formed by arranging 63 (9 x 7) unit delay elements in a matrix shape, and the output of each of the 63 unit delay elements is selected by 86). The selector 86 is also supplied with a signal before input to the first unit delay element of the delay matrix 85. Therefore, 64 signals obtained by delaying the output SEL_IN of the selector 84 to the unit delay elements of 0 to 63 are supplied from the delay matrix 85 to the selector 86.

The selector 86 is supplied with 64 signals from the delay matrix 85, and the selector 71 (FIG. 9) is supplied with the data FALL_DATA [5: 0] (DSEL [5: 0]) (programmable delay). Regarding line 74, data RISE_DATA [5: 0] is supplied from selector 72). The selector 86 selects one of the 64 signals from the delay matrix 85 according to the data FALL_DATA [5: 0] from the selector 71, and selects the selected signal from the multipulse generator 16. Data DATA1 is output as data DDATA1 (DL_OUT) which is delayed in accordance with FALL_DATA [5: 0].

This data DDATA1 (DL_OUT) is also supplied to the other input terminal of the NOR gate 87. As the NOR gate 87, an output SEL_IN of the selector 84 and a NOR (non-logical sum of logical sum) of the data DDATA1 (DL_OUT) from the selector 86 are calculated, and the result of the calculation is that NOR is RSFF (RS flip-flop). It is supplied to the S terminal of (88).

The R terminal of the RSFF 88 is supplied with a clear signal CLR (FIG. 11 (F)) from the microcomputer 11, and when the clear signal CLR is 0 or 1, respectively, of the NOR gate 87 The output is latched or its contents (value latched) are cleared and output. The output Q of the RSFF 88 is supplied to the microcomputer 11 as the flag FLAG1.

Therefore, when the signal DL_TEST is 1, the output of the OR gate 83 is selected by the selector 84 and supplied to the delay matrix 85 and the NOR gate 87. Here, since the output of the OR gate 83 is the logical sum of the signal REF_SIGNAL (FIG. 11 (B)) and the signal which delayed it somewhat, it shows the falling edge of the signal REF_SIGNAL, as shown in FIG. 11 (C). I barely delayed.

The delay matrix 85 outputs 64 signals obtained by delaying the output of the selector 84 to the unit delay elements of 0 to 63, and the selector 86 outputs data FALL_DATA [5: 0] ( Corresponding to DSEL [5: 0]) is selected, and the selection signal DL_OUT is supplied to the NOR gate 87.

Therefore, the selection signal DL_OUT (any one of 64 signals each having delayed the output of the selector 84 to 0 to 63 unit delay elements) with respect to the signal REF_SIGNAL (Fig. 11 (B)) (Fig. 11 (D)). When the delay amount of is smaller than the period T of the clock CLK and larger than the period T, the H level appears at the output of the NOR gate 87 as shown in Fig. 11E. When the delay amount coincides with the period T of the clock CLK, the output of the NOR gate 87 remains at the L level (Fig. 11E).

When the H level appears at the output of the NOR gate 87 (FIG. 11 (E)), when the clear signal CLR (FIG. 11 (F)) becomes 1 (H level), FLAG1, which is the output of the RSFF 88, is also shown in FIG. 11 (G) and when the output of the NOR gate 87 remains at the L level (FIG. 11E), regardless of the level of the clear signal CLR (FIG. 11F). FLAG1, which is the output of the RSFF 88, remains 0 (L level) (Fig. 11 (G)).

From the above, the signal DL_TEST is set to 0, the clear signal CLR is set to 1, the RSFF 88 is reset, and the data FALL_DATA [5: 0] (DSEL [5: 0]), that is, the selector 86 is reset. The data selected when the flag FLAG1 remains 0 is changed by changing the signal selected in step S0 and then clearing the signal CLR to 0, and then setting the signal DL_TEST to 1. FALL_DATA [5: 0] (DSEL [5: 0 ]) Is obtained, which is set to a value corresponding to the number of stages of the unit delay element required for one clock delay (time T delay).

Thus, according to the programmable delay line 73 of FIG. 10, the number of stages of the unit delay element (in this case comprised of an inverter as shown in FIG. 12) required for one clock delay can be measured.

Here, when the signal DL_TEST is set to 1, the selector 71 of Fig. 9 selects the lower 6 bits D [5: 0] of the data D [11: 0] in the microcomputer 11 as described above. It is supplied to the programmable delay line 73 as data FALL_DATA [5: 0] (DSEL [5: 0]). Therefore, the microcomputer 11 monitors the flag FLAG1 and, as described above, changes the signal DL_TEST and the clear signal CLR, and changes the data D [11: 0], thereby delaying one clock. The data FALL_DATA [5: 0] corresponding to can be recognized, and based on the recognition result, the RAM 15 can store data having an appropriate value.

On the other hand, when the recording pulse is generated, the microcomputer 11 sets the signal DL_TEST to 0. In the selector 71 of FIG. 9, as described above, the output of the DFF 19 is selected. The lower 6-bit DO [5: 0] 0 of the data DO [11: 0] read out from the RAM 15 by means of the data FALL-DATA [5: 0] (DSEL [5: 0) is programmable. Supplied to line 73. In this case, in the programmable delay line 73, the data DATA1 (DL_IN) from the multi-pulse generator 16 is selected and supplied to the delay matrix 85 in the selector 84 (FIG. 10). In the selector 86, the data DATA1 (DL_IN) from the multipulse generator 16 is converted into a unit delay element of 0 to 63 corresponding to the data FALL_DATA [5: 0] (DSEL [5: 0). Any one of the 64 signals which are delayed each is selected, and it is output as data DDATA1 (DL_OUT).

As described above, since the programmable delay line 73 (74) can measure the number of units of the unit delay element required for one clock delay, the CMOS process is performed when the recording circuit 4 is made into one chip. Even if the delay time of one unit delay element changes due to various factors such as temperature, speed, power supply voltage, and the like, the data D [11: 0] stored in the RAM 15 in response to the change. By rewriting this, it becomes possible to cope.

In addition, the measurement of the number of stages of the unit delay element required for the delay of one clock as described above, and the rewriting of the RAM 15 in the data corresponding to the measurement result are, for example, when the system is powered on, or It is possible to carry out regularly after the power is turned on. In addition, regarding the above-described programmable delay line 73 (or 74), the detailed description is disclosed, for example, in Japanese Patent Application No. 7-244963 etc. which the applicant filed earlier.

Although the case where the present invention is applied to a disk drive for driving a phase change disk has been described, the present invention can be applied to an apparatus for driving a recording medium other than a disk shape such as a card shape, for example. In addition, the scope of application of the present invention is not limited to recording by phase change, recording by MCAV system, or the like.

In addition, in the present embodiment, the delay amounts (x, y) are changed to the same value, but the delay amounts (x, y) need not be the same.

In the present embodiment, the programmable delay line 17 is to delay the data DATA1 preceding in time by 1/2 the clock obtained by the DFF 53 (FIG. 7). However, in the DFF 53, one clock is delayed. It is also possible to generate the preceding data in time and delay the data on the programmable delay line 17. In the above case, the recording pulse corresponding to the mark of length nT is expressed by the formula xS + (1.5-x) M + (n-3) (0.5S + 0.5M) + 0.5S + yM + (1.0-y) S. Will appear.

According to the data recording apparatus according to claim 1 and the data recording method according to claim 5, by changing the position of the start edge of the start pulse, the pulse width is changed and the position of the end edge of the termination pulse. The pulse width is changed. Therefore, for example, it is possible to easily perform recording compensation corresponding to the linear velocity or the like.

In the recording medium according to claim 6, the position of the start edge of the start pulse is changed so that the pulse width is changed, and the position of the end edge of the end pulse is changed. And space are formed. Thus, for example, high density recording and fast random access are enabled.

According to the data recording apparatus of claim 7, the recording pulse corresponding to the mark whose length is nT is expressed by the formula xS + (1.5-x) M + (n-2) (0.5S + 0.5M) + yM + (0.5 y) S, or the formula xS + (1.5-x) M + (n-3) (0.5S + 0.5M) + 0.5S + yM + (1.0-y) S, and recording is performed according to this recording pulse. Is done. Therefore, for example, it is possible to easily perform recording compensation corresponding to the linear velocity or the like.

1 is a block diagram showing the configuration of an embodiment of a disk drive to which the present invention is applied.

FIG. 2 is a diagram for explaining a recording compensation method in the recording circuit 4 of FIG.

3 is a block diagram showing an example of the configuration of the write circuit 4 of FIG.

4 is a circuit diagram showing an example of the configuration of the controller 12 in FIG.

FIG. 5 is a circuit diagram showing an example of the configuration of the multipulse generator 16 of FIG.

FIG. 6 is a circuit diagram showing a configuration example of the write signal generator 21 of FIG.

7 is a block diagram showing an example of the configuration of the multipulse generator 16, the programmable delay lines 17 and 18, and the write signal generator 21 of FIG.

FIG. 8 is a timing diagram for explaining the operation of the multipulse generator 16, the programmable delay lines 17 and 18 and the write signal generator 21 of FIG.

9 is a block diagram showing another example of the configuration of the write circuit 4 of FIG.

FIG. 10 is a block diagram showing a configuration example of the programmable delay lines 73 and 74 of FIG.

11 is a timing diagram for explaining the operation of the programmable delay line 73 in FIG.

FIG. 12 is a circuit diagram showing a configuration example of the unit delay element 82 of FIG.

FIG. 13 is a block diagram showing a configuration example of a delay matrix 85 of FIG.

14 is a diagram for explaining the recording principle of a phase change disk.

15 is a diagram for explaining direct overwrite;

16 is a diagram for explaining a conventional recording compensation method.

17 is a block diagram showing a configuration of an example of a circuit for performing conventional write compensation.

※ Explanation of code about main part of drawing ※

1: disc 2: spindle motor

3: pickup 4: recording circuit

5: regeneration circuit

Claims (18)

Relative speeds between the recording means for recording data and the recording medium change, and recording means causes marks and spaces to be recorded on the recording medium by recording pulses in which start, burst, and end pulses are combined. A data recording apparatus for forming and recording data, A start pulse changing means for changing the start pulse width by changing a position of a start edge of the start pulse; And an end pulse changing means for changing the end pulse width by changing the position of an end edge of the end pulse. The method of claim 1, And the start pulse changing means or the end pulse changing means changes the position of the start edge or the end edge in accordance with a change in the relative speed between the recording means and the recording medium. The method of claim 1, And the start pulse changing means or the end pulse changing means changes the position of the start edge or the end edge based on the length of the mark or the space. The method of claim 2 or 3, When the pulse width corresponding to the clock at the time of recording the data is T, the start pulse changing means or the end pulse changing means sets the pulse width of the start pulse or the end pulse in the range of 0.5T to 1.5T. A data recording apparatus, characterized in that for changing. The relative speed between the recording means for recording data and the recording medium changes, and the recording means forms a mark and a space on the recording medium to record the data by a recording pulse obtained by combining the start pulse, the burst pulse, and the end pulse. In the data recording method, Synthesizing a start pulse, a burst pulse, and an end pulse; Delaying the position of the start edge of the start pulse and the position of the end edge of the termination pulse; And forming a mark and a space in the recording medium by a recording pulse having a changed pulse width. A recording medium in which a relative speed with a recording means for recording data is changed, and the recording means forms a mark and a space by recording pulses in which a start pulse, a burst pulse, and an end pulse are combined to record data. And the mark is formed by the start pulse whose position of the start edge of the pulse is changed to change the pulse width and the end pulse whose position of the end edge of the pulse is changed to change the pulse width. The relative speed between the recording means for recording data and the recording medium changes, and the recording means forms a mark and a space on the recording medium to record the data by a recording pulse obtained by combining the start pulse, the burst pulse, and the end pulse. In the data recording apparatus, A start pulse generating means for generating the start of the data as a start pulse having a pulse width of one clock; End pulse generation means for generating an end of the data as an end pulse having a pulse width of one clock; First delay means for delaying the data by a first delay amount x; Second delay means for delaying the data by a second delay amount y; And a recording pulse synthesizing means for synthesizing the recording pulses by calculating outputs of the start pulse generating means, the end pulse generating means, and the first and second delay means. The method of claim 7, wherein If the pulse width corresponding to one clock is T, and one of the H or L levels of the recording pulse is represented by M and the other is represented by S, the recording pulse corresponding to a mark having a length of nT (n is an integer), xS + (1.5-x) M + (n-2) (0.5S + 0.5M) + yM + (0.5-y) S or A data recording apparatus, characterized by xS + (1.5-x) M + (n-3) (0.5S + 0.5M) + 0.5S + yM + (1.0-y) S. 9. The recording pulse according to claim 8, wherein when said second delay means delays said data one half clock or one clock ahead, said recording pulse corresponding to a mark of length nT, xS + (1.5-x) M + (n-2) (0.5S + 0.5M) + yM + (0.5-y) S or A data recording apparatus, characterized by xS + (1.5-x) M + (n-3) (0.5S + 0.5M) + 0.5S + yM + (1.0-y) S. The method of claim 7, wherein And the first or second delay amount (x or y) is a value in the range of 0T to 0.5T. The method of claim 7, wherein The recording pulse synthesizing means comprises: first calculating means for calculating a logical sum of an output of the start pulse generating means and the end pulse generating means and a clock; Second calculating means for calculating the logical product of the outputs of the first and second delay means; And a third calculating means for calculating the logical product of the outputs of the first and second calculating means. The method of claim 7, wherein And a delay amount setting means for adaptively setting each of the first or second delay amounts (x or y). The method of claim 12, And the delay amount setting means sets each of the first or second delay amounts (x or y) based on the relative speed between the recording medium and the recording means. The method of claim 12, And the delay amount setting means sets each of the first or second delay amounts (x or y) based on the data. The method of claim 7, wherein And the start pulse generating means, the end pulse generating means, the first and second delay means, and the write pulse generating means are integrated into one chip. The method of claim 7, wherein And said first and second delay means comprise an inverter. The method of claim 16, And a measuring means for measuring the number of stages of the inverter required for a predetermined delay amount. A data recording apparatus for recording data on a recording medium in accordance with a recording pulse, Multi-pulse generating means for generating a multi-pulse consisting of start pulse, burst pulse and end pulse; First signal generating means for generating a first signal for defining a front end of the recording pulse; Second signal generating means for generating a second signal for determining an end of the recording pulse; Third signal generating means for generating a third signal by calculating a logical product of the first signal generated by the first recording signal generating means and the second signal generated by the second signal generating means; And recording pulse generating means for generating the recording pulse by calculating a logical product of the multi-pulse generated by the multi-pulse generating means and the third signal generated by the third signal generating means. Data recording apparatus.

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