KR100625796B1 - Data strobe signal driver in memory device - Google Patents

Abstract

The present invention provides an output driving means for outputting a data strobe signal in response to a pull-up signal and a pull-down signal in order to provide a data strobe signal driving device which improves an operation speed and reduces an implementation area by implementing a pipeline latch using only a pull-down transistor. ; Precharge means for precharging the pull-up signal and the pull-down signal in response to a first control signal and a second control signal; And a pull-up signal or the pull-down signal by receiving a corresponding counter signal received from a plurality of bits of an even pipe counter signal and an odd pipe counter signal and a third and fourth control signals from the precharge means. And a plurality of pipeline latches for selectively toggling the data strobe signal to support a toggle operation of the data strobe signal, wherein the plurality of pipeline latches respectively receive and store the third and fourth control signals. Control signal storage means; A first circuit portion having first and second pull-down means, for pulling down the pull-up signal pulled up in response to an output signal from the corresponding counter signal and the control signal storage means; And second and fourth pull-down means, the second circuit section for pull-down driving the pull-down signal pulled up in response to the counter signal and the output signal from the control signal storage means.

Data strobe signal, pipe count signal, pipeline latch, precharge part, output driver

Description

DATA STROBE SIGNAL DRIVER IN MEMORY DEVICE}             

1 is a configuration diagram of an apparatus for driving a data strobe signal according to the present invention.

2 is an internal circuit diagram of a precharge unit of the data strobe signal driving device of FIG. 1 according to the present invention;

3 is an internal circuit diagram of a pipeline latch of the data strobe signal driving device of FIG. 1 according to the present invention;

4 is an overall operation waveform diagram of the data strobe signal driving device according to the present invention;

* Description of the main parts of the drawing

100: precharge part, 110 to 160: pipeline latch

170: output driver

The present invention relates to a data strobe signal driver of a semiconductor memory device.

Semiconductor memory devices have been continually improved to increase their integration and to increase their operating speed. In particular, in DRAM (Dynamic Random Access Memory), so-called synchronous DRAM (hereinafter referred to as "SDRAM") that can operate in synchronism with a clock given from the outside of the memory chip to improve its operation speed has come to emerge One conventional SDRAM is a so-called single data rate (SDR) SDRAM which inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from outside the chip. . On the other hand, the SDR SDRAM as described above is also insufficient to satisfy the speed of the system that requires high-speed operation, and thus a method of processing two data in one clock cycle (double data rate; hereinafter referred to as "DDR") This has been proposed. In each of the data pins of the DDR SDRAM, two data are inputted and outputted in synchronization with the rising and falling edges of the externally input clock. Compared to SDR SDRAM, at least twice the bandwidth can be realized, so that high speed operation can be realized.

On the other hand, in order to inform the CPU or memory controller outside the memory device of the exact timing of the data output by the operation of the DDR SDRAM, the DDR SDRAM is a data strobe signal along with the data signal outside the chip. The data strobe signal (QS signal) is outputted, and the circuit for driving the data strobe signal (QS signal) is a data strobe signal driving device.

The data strobe signal (QS signal) output from the data strobe signal driver must be output in accordance with the data read timing in the DDR SDRAM, and therefore the data strobe signal driver must drive the corresponding data strobe signal QS.

First, the data strobe signal QS must maintain a high impedance state (hi-z, a middle level between 'high' and 'low'), and must have a 'low' state before the clock before the data DQ is generated ( preamble), when the data (DQ) comes out, it toggles (ie, "low" "high" "low" "high" until its edge is triggered at the edge Signal) and remain 'low' for the half clock after the last data (DQ). In this case, the system outside the memory chip recognizes that the data DQ is output at the rising edge and the falling edge of the data strobe signal QS.

Conventional data strobe signal driving apparatus for driving a data strobe signal satisfying the above condition has a plurality of pipeline latches, and toggles to "low" "high" "low" "high" when outputting data DQ. In order to output a data strobe signal, each of the pipeline latches includes both a pull-up transistor and a pull-down transistor to output a pull-up signal and a pull-down signal for controlling the output driver.

Therefore, the conventional data strobe signal driving device has a large implementation area due to the pull-up transistor and the pull-down transistor of the pipeline latch, and the operation speed also decreases due to the additional control operation for the control of the pull-up transistor and the pull-down transistor. have.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data strobe signal driving apparatus which improves an operation speed and reduces an implementation area by implementing a pipeline latch using only a pull-down transistor.

The present invention for achieving the above object, the output drive means for outputting a data strobe signal in response to the pull-up signal and the pull-down signal; Precharge means for precharging the pull-up signal and the pull-down signal in response to a first control signal and a second control signal; And a pull-up signal or the pull-down signal by receiving a corresponding counter signal received from a plurality of bits of an even pipe counter signal and an odd pipe counter signal and a third and fourth control signals from the precharge means. And a plurality of pipeline latches for selectively toggling the data strobe signal to support a toggle operation of the data strobe signal, wherein the plurality of pipeline latches respectively receive and store the third and fourth control signals. Control signal storage means; A first circuit portion having first and second pull-down means, for pulling down the pull-up signal pulled up in response to an output signal from the corresponding counter signal and the control signal storage means; And second and fourth pull-down means, the second circuit section for pull-down driving the pull-down signal pulled up in response to the counter signal and the output signal from the control signal storage means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a configuration diagram of an apparatus for driving data strobe signals according to the present invention.

First, the signal shown in the figure will be described. qsen is an enable signal for controlling the operation of the data strobe signal driving device, and qsen_pre is a signal for controlling the preamble state of the data strobe signal QS. Pcnt_even [0: 2] is an even pipe counter signal synchronized to the rising edge of the main clock, and pcnt_odd [0: 2] is an odd pipe counter signal synchronized with the falling edge of the main clock to control the pipeline latch. The data and odd data are output to the data output driver. The even pipe counter signal and the odd pipe counter signal are enabled once within one clock. In this case, since even-numbered pipe counter signal pcnt_even and odd-numbered pipe counter signal pcnt_odd have a priority determined according to address information, even data and odd data stored in pipeline latch are output priority. Are determined and output in order.

Referring to the drawings, the data strobe signal driving apparatus of the present invention generates an output driver 170 for generating and outputting the data strobe signal QS in response to the pull-up signal pu and the pull-down signal pd, the enable signal qsen, and the control signal qsen_pre. In response, the precharge unit 100 for precharging the pull-up signal up and pull-down signals dn, the even-numbered pipe counter signal pcnt_even and the odd-numbered pipe counter signal pcnt_odd, respectively, are input to the corresponding counter signal and the corresponding counter signal. A plurality of pipeline latches for receiving the input control signals pd_d and pu_d from the precharge unit 100 to selectively pull down the pull-up signal up or pull-down signal dn to support a toggling operation of the data strobe signal QS. 110 to 160).

For convenience of explanation, the output driver 170 which receives the pull-down signal pd and the pull-up signal pu will be described first. The output driver 170 generates and outputs the data strobe signal QS in response to the pull-up signal pu and the pull-down signal pd. The output driver 170 has a structure and driving capability similar to that of a data output driver used for a general data pin.
The circuit configuration of the output floating portion 170 is substantially the same as the conventional bar, it is configured as a conventional NAND latch and driver. Looking at the final output of the QS according to the pull-up signal pu and the pull-down signal pd by this configuration, when the pull-up signal pu is pulled down to become a 'lo' pulse, the data strobe signal QS becomes 'high' and the pull-down signal pd is 'lo'. When the pull-down signal pd becomes 'lo', the data strobe signal QS becomes 'lo' and latches until the pull-up signal pu becomes 'lo'. This process is repeated. This operation will be described in detail later with reference to FIG. 4.
FIG. 2 is an internal circuit diagram of a precharge unit of the data strobe signal driving device of FIG. 1 according to the present invention, and receives a control signal qsen_pre to control a preamble state of a data strobe signal QS. a preamble control pulse generator 200 for generating a pulse), an enable signal qsen, a pulldown signal pd, a pullup signal pu, and a preamble control pulse from the preamble control pulse generator 200. and a pull-up driver 210 for driving the pull-up signal pd and the pull-down signal pd. In particular, the pull-up driver 210 is output to the pipeline latch 120 in response to the enable signal qsen, the pull-down signal pd, and the pull-up signal pu. Pipeline input control unit 211 for generating input control signals pd_d and pu_d, pd pull-up driving unit 212 and pull-up driving pull-down signal pd A pu pull-up driving unit 213 for driving the up signal pu is provided.

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Specifically, in the present embodiment of FIG. 2, the preamble control pulse generator 200 includes an odd number of serially connected inverters I1 to I5 for inverting / delaying the control signal qsen_pre and an output signal of the final inverter I5. Is configured as a NAND gate ND1 having one input and the control signal qsen_pre as a type force, and the preamble control pulse generator 200 senses a time at which the control signal qsen_pre is activated (rising edge) to a predetermined width. Generate a preamble control pulse having:

The pipeline input control unit 211 uses two inverters I6 and I7 for inverting the pull-down signal pd and the pull-up signal, respectively, and an output signal of each inverter I6 and I7 as one input, and the enable signal qsen The NAND is configured as two NAND gates ND2 and ND3 for outputting the input control signals pd_d and pu_d of the pipeline latch.

In addition, the pd pull-up driving unit 212 includes an odd number of serially connected inverters I8 to I12 for inverting / delaying the output signal of the NAND gate ND2 (that is, the input control signal pd_d of the pipeline latch), and Receives the pull gate signal NR1 of the output signal of the inverter I12 and the output signal of the power supply terminal and the output drive unit 130 as well as the NR1 gate having the type signal as the preamble control pulse generator 200 as the input signal. A source-drain path is connected between nodes, and a PMOS transistor P1 receives an output signal of the NOR gate NR1 as a gate.

In addition, the pu pull-up driving unit 213 includes an even number of serially connected inverters I13 to I18 for delaying the output signal of the NAND gate ND3 (that is, the input control signal pu_d of the pipeline latch), and a power supply terminal. A source-drain path is connected between the pull-up signal pu receiving nodes of the output driver 130, and the PMOS transistor P2 receives the output signal of the final inverter I18 as a gate.

Therefore, when the control signal qsen_pre is enabled as "high", the preamble control pulse generator 200 outputs a "high" preamble control pulse, and then the pd pull-up driver 210 receiving the "high" pulse. The pull-down signal pd is set to "high" by outputting a "low" signal from the NOA gate NR1 and turning on the PMOS transistor P1. Then, the QS signal of "low" is output from the output driver 130 by the pull-down signal pd set to "high." At the moment when the enable signal qsen becomes "high", the pull-up signal pu is also set to "high" through the pu pull-up driving unit 213.

Subsequently, if the pu and pd signals set to "high" transition to "low", the signal is "high" again after a delay time through the inverter chain of the pd pull-up driver 212 and the pu pull-up driver 213. Will be pulled up.

The pipeline input control unit 211 outputs the input control signals pd_d and pu_d of the pipeline latch to the pipeline latch 120.

3 is an internal circuit diagram of any one of the pipeline latches of the plurality of pipeline latches of FIG. 1 according to the present invention, each of the plurality of pipeline latches 110 to 160 is configured with the same internal circuit.

Each of the plurality of pipeline latches 110 to 160 receives the input control signals pd_d and pu_d from the pipeline input control unit 211, a control signal storage unit 300 for storing the values, and a pipe counter signal pcnt and In response to the output signal from the control signal storage unit 300, the pull-down signal in response to the output signal from the pu pull-down driving unit 310 and the pipe counter signal pcnt and the control signal storage unit 300 for pull-down driving the pull-up signal pu The pd pull-down driving unit 320 for driving the pd down.

In the present embodiment of FIG. 3, the control signal storage unit 300 uses the input control signal pd_d as one input and the NAND gate ND4 which uses the output signal of the NAND gate ND5 as a type force, and the input control signal pu_d. The NAND gate ND5 is configured as one input and the output signal of the NAND gate ND4 is a type force. The output signal of the NAND gate ND4 is input to the pu pull-down driving unit 310, and the NAND gate ND5. ) Is input to the pd pull-down driver 320.

In the present embodiment, the pu pull-down driving unit 310 uses the inverter I19 for inverting the pipe counter signal pcnt and the output signal of the inverter I19 as one input, and outputs the output signal of the NAND gate ND4. NAND gate ND6, which is a type force, an odd number of serially connected inverters I20 to I22 for inverting / delaying the output signal of the NAND gate ND6, and a pull-up signal pu receiving node of the output driver 130. And an NMOS transistor N1 connected in series between the ground power supply terminal and the ground power supply terminal and receiving the pipe counter signal pcnt to the gate terminal and the output signal of the final inverter I22 to the gate terminal.

In the present embodiment, the pd pull-down driving unit 320 uses the inverted pipe counter signal pcnt as one input and the output signal of the NAND gate ND5 as the type force, and the NAND gate ND7. Odd number of serially connected inverters I23 to I25 for inverting / delaying the output signal of the output signal and the pull-down signal pd of the output driver 130 are connected in series between the receiving node and the ground power supply terminal, and the pipe counter signal pcnt is connected to the gate terminal. The NMOS transistor N3 receives N and the NMOS transistor N4 receives an output signal of the final inverter I25 through a gate terminal.

As shown in FIG. 3, the pipeline latches 110 to 160, which are configured as shown in FIG. 3, first input signal Pd_d is "high", pu_d signal is transitioned to "low" in the form of a pulse and then "high" When the "low" pulse is input, the "low" of the pu_d signal is stored in the control signal storage unit 300. That is, the output terminal of the NAND gate ND4 is "low", and the output terminal of the NAND gate ND5 is "high". Then, when the pipe counter signal pcnt is enabled "high", a "high" signal at the gate terminal of the NMOS transistor N4 through the NAND gate ND7 and the inverters I23 to I25 of the pd pull-down driver 320. Is applied to pull down signal pd to " low ". In this case, the time when the pull-down signal pd is pulled down to "low" is maintained by the delay time through the NAND gate ND7 of the pd pull-down driver 320 and the inverters I20 to I22. In addition, a "low" signal is applied to the gate terminal of the NMOS transistor N2 of the pu pull-down driving unit 310 so that the pull-up signal pu is not pull-down driven.

In the above pull-down operation, when the pull-down signal pd becomes "low", the input control signal pd_d of the "low" pulse is input from the precharge unit, and the pull-up signal pu is "low" when the counter signal pcnt is "high". Transition to. Subsequently, when the pull-up signal pu transitions to "low", then the pull-down signal pd becomes "low", and the toggling operation of the pull-up signal pu and the pull-down signal pd continues while the pipe counter signal pcnt is repeated in this order. Is done.

4 is an overall operation waveform diagram of the data strobe signal driving apparatus according to the present invention.

First, when the control signal qsen_pre is enabled as "high", the pull-down signal pd is pulled up to "high" through the precharge unit 110, and the data strobe signal QS of "low" through the output driver 130. By outputting the preamble section before full data output is generated. The enable signal qsen is enabled as "high" at the same time as the control signal qsen_pre, but the control signal pd_d of the "high" is stored in the control signal of the pipeline latches 110 to 160 after a delay through the pipeline input control unit 211. The unit 300 is stored in the NAND latch. When either the even pipe counter signal pcnt_even [0: 3] or the odd pipe counter signal pcnt_odd [0: 3] is enabled as “high”, the NMOS transistor of the pd pull-down driving unit 320 of the pipeline latch is enabled. (N3, N4) is turned on to pull down the pulldown signal pd to " low ".

Subsequently, in the operation described in the pipeline latch description, the pull-up signal pu and the pull-down signal pd are alternated in synchronization with the rising edge of the pipe counter signal pcnt.

Accordingly, the output driver 130 alternately performs pull-down and pull-up driving by the toggled pull-up signal pu and the pull-down signal pd to finally output the QS signal as shown in the drawing.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, a plurality of pipeline latches for supporting the toggling operation of the data strobe signal QS by selectively pulling down the pull-up signal up or the pull-down signal dn with the pull-down transistor alone without using the pull-up transistor By implementing, it is possible to improve the operation speed and reduce the implementation area.

Claims (10)

Output driving means for outputting a data strobe signal in response to the pull-up signal and the pull-down signal; Preamble control pulse generating means for generating a preamble control pulse for controlling a preamble state of the data strobe signal in response to a second control signal, a first control signal, the pull-down signal, the pull-up signal, and the preamble control pulse generating means Precharge means including pull-up driving means for respectively pulling up the pull-up signal and the pull-down signal in response to a preamble control pulse from the preamble control pulse; And The pull-up signal or the pull-down signal is received by receiving the corresponding counter signal and the third and fourth control signals from the precharge means, which are input by receiving one of a plurality of bits of an even pipe counter signal and an odd pipe counter signal. And a plurality of pipeline latches for selectively pulling down to support a toggle operation of the data strobe signal. The plurality of pipeline latch units, respectively Control signal storage means for receiving and storing the third and fourth control signals; A first circuit section having first and second pull-down means for driving the pull-up signal in response to an output signal from the corresponding counter signal and the control signal storage means; And A second circuit portion having third and fourth pull-down means for pull-down driving the pull-down signal in response to an output signal from the corresponding counter signal and the control signal storage means; A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 1, wherein the control signal storage means, A latch unit of negative logic structure having the third control signal and the fourth control signal as input terminals. A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 2, wherein the first circuit portion, First negative logic means for negatively multiplying the counter signal and the first output signal of the latch unit; An odd number of serially connected inverting means for inverting and delaying the output signal from said first negative logical means; An output signal of a final inverting means of the plurality of inverting means of the first pull-down means and a gate end of the first pull-down means connected in series between the pull-up signal receiving node of the output driving means and a ground power terminal and receiving the corresponding counter signal through a gate end; Receiving the second pull-down means A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 2, wherein the second circuit portion, First negative logic means for negatively multiplying the counter signal and the second output signal of the latch unit; An odd number of serially connected inverting means for inverting and delaying the output signal from said first negative logical means; An output signal of a final inverting means among the plurality of inverting means connected to the third pull-down means and the gate end connected in series between the pull-down signal receiving node of the output driving means and the ground power terminal; The fourth pull down means for receiving a A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 1 or 4, wherein the first to fourth pull-down means, respectively A data strobe signal driving apparatus for a semiconductor memory device having an NMOS transistor. The method of claim 1, wherein the pull-up drive means, A third circuit unit for generating the third and fourth control signals output to the plurality of pipeline latch units in response to the first control signal, the pull-down signal, and the pull-up signal; A fourth circuit unit for driving the pull-down signal up; And A fifth circuit unit for driving the pull-up signal A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 1, wherein the preamble control pulse generating means, An odd number of serially inverted means for inverting and delaying said second control signal; And Among the plurality of inverting means comprising a negative logic means for negative logic multiplication by using the output signal of the last inverting means as one input and the second control signal as a type force, And a preamble control pulse having a predetermined width by sensing a time point at which the second control signal is activated. The method of claim 6, wherein the third circuit portion, First negative logical means for receiving a negative logic of the pull-down signal and the first control signal; And A second negative logical means for receiving a negative logic of the pull-up signal and the first control signal; A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 8, wherein the fourth circuit unit, An odd number of serially connected inverting means for inverting and delaying the output signal of said first negative logical means; Negative logic means for negating and logically performing the output signal of the last inverting means of the plurality of inverting means as one input, and using the preamble control pulse from the preamble control pulse generating means as a type force; And A pull-up element connected between a power supply terminal and a pull-down signal receiving node of the output driving means and receiving an output signal of the negative logic means from a gate; A data strobe signal driving device of a semiconductor memory device comprising a. The method of claim 8, wherein the fifth circuit portion, An even number of serially connected inverting means for delaying the output signal of said second negative logical means; And A pull-up element connected between a power supply terminal and a pull-up signal receiving node of the output driving means and receiving an output signal of a final inverting means among the plurality of inverting means by a gate; A data strobe signal driving device of a semiconductor memory device comprising a.

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