KR100624915B1 - Test pattern in flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a NAND flash memory device. A decoding circuit is provided on a word line of a NAND flash memory cell to decode a signal input from a small number of probing pads, thereby selecting one word line and applying a selection voltage. The pass word can be applied to the remaining word lines, and the number of cells that can be measured using the decoder can be increased to prevent defects that may occur during the main mass production, and the failure mode during the main mass production can be analyzed in a timely manner. It can shorten the product development period and provide a test pattern of NAND flash memory device that can increase the interdependence of characteristics between the production chip and the test pattern.

Test pattern, probing pad, decoder, cell, selection voltage

Description

Test pattern in flash memory device             

1 is a test pattern of a NAND flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: cell string 200: decoding circuit

The present invention relates to a test pattern of a flash memory device, and to a method of increasing the number of cells that can be measured in testing a test pattern of a NAND flash using a probing pad.

In the NAND flash memory test pattern, at least 40 pads are required to probe 32-cell strings. With so many pads, only 96 cell characteristics can be identified. In addition, since the NAND flash memory does not use a negative voltage, it is difficult to identify an erase cell characteristic having a negative threshold voltage. Therefore, there is a problem in that the correlation between the production chip and the test pattern is difficult.

Accordingly, in order to solve the above problem, the present invention introduces a decoder to code a test pattern, thereby increasing the number of cells that can be measured, thereby detecting a defect in the main mass production. A test pattern of a flash memory device is provided.

The test pattern of the flash memory device according to the present invention includes a plurality of cell strings in which a plurality of cells are connected in series, a plurality of word lines and bit lines for selecting a cell in the cell string, a drain terminal of the cell string and the A drain select transistor connected between the bit lines and driven according to a drain select signal, a source select transistor connected between a source terminal of the cell string and a common source line and driven according to a source select signal and a word line selected according to an external signal And a decoding circuit for applying a selection voltage and applying a pass voltage to unselected word lines.                     

The decoding circuit may receive a predetermined control signal from a probing pad and generate one of the selected voltage and 31 of the pass voltages.

The drain selection signal is applied to the gate terminal of the drain selection transistor through a first probing pad, and the source selection signal is applied to the gate terminal of the source selection transistor through a second probing pad, and through the third probing pad. A common source voltage may be applied to the common source line, and a charging voltage may be applied to the bit line through a fourth probing pad.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a test pattern of a NAND flash memory device according to the present invention.

Referring to FIG. 1, a plurality of cell strings 100 in which a plurality of cells are connected in series, and a plurality of word lines W / L and bit lines B / L for selecting cells in the cell string 100 are illustrated. ), A drain select transistor T1 connected between the drain terminal of the cell string 100 and the bit line B / L and driven according to the drain select signal DSL, and the cell string 100 of the cell string 100. A source selection transistor T2 connected between the source terminal and the common source line CSL and driven according to the source selection signal SSL and a word line W / L selected according to an external signal are provided with a selection voltage Vias. And a decoding circuit 200 for applying a pass voltage Bis2 to the unselected word line W / L.

The decoding circuit 200 receives a predetermined control signal from an external pad, applies a selection voltage Bis1 to the selected word line W / L, and applies a pass voltage to the unselected word line W / L. . The decoding circuit 200 receives a predetermined test signal from five probing pads (not shown) to generate 32 signals, and generates one selection voltage Bis1 to be applied to a selected word line according to the input signal. . 31 pass voltages Bias2 to be applied to unselected word lines are generated according to the input signal. The voltage applied to the word line through the decoding circuit 200 is 0 to 18V.

As shown in FIG. 1, the decoding circuit 200 has the first and second bias (Bias1 and Bias2) output nodes so that a voltage of 18 V may be applied to any one of the first bias (Bias1) output nodes in a program operation. Is authorized. In the case of a program operation, the second bias Bias2 output node applies a voltage of 10 V to the remaining nodes except for the second bias Bias2 output node overlapping the first bias Bias1 output node to which the voltage of 18 V is applied. do.

In a read operation, a ground voltage is applied to any one of the first bias (Bias1) output nodes, and the second bias output node has a second bias overlapping the first bias (Bias1) output node to which the ground voltage is applied. (Bias2) Apply a voltage of 4.5V to all nodes except the output node.

In the erase operation, a ground voltage is applied to each of the first and second bias bias signals Bias1 and Bias2.

According to the present invention, it is possible to reduce the number of probing pads required for testing the selected cell and to reduce the difference between the cell patterns during mass production. That is, in the related art, the selection voltage Bis1 is applied to the selected word lines among the first to 32 word lines with 32 probing pads, and the pass voltage Bis2 is applied to the remaining word lines. However, the present invention may apply the selection voltage Vias to the selected word line using only at least five probing pads, and apply the pass voltage Vias to the unselected word lines.

For example, when the cells adjacent to the drain select transistor are sequentially increased as the first cell, a selection voltage is conventionally applied to the third probing pad to select the third cell, and a pass voltage is applied to the remaining probing pads. . However, in the present invention, when 00010 is applied to the decoding circuit with five probing pad values, the selection voltage is applied to the third cell and the pass voltage is applied to the remaining cells.

The present invention applies the drain select signal DSL to the gate terminal of the drain select transistor T1 through another probing pad, and the source select signal to the gate terminal of the source select transistor T2 through the other probing pad. (SSL) is applied, a common source voltage is applied to the common source line CSL through another probing pad, and a charging voltage is applied to the bit line B / L through the other probing pad. In this case, the first charging voltage may be applied to the bit lines selected through the different probing pads, and the second charging voltage may be applied to the bit lines not selected through the other probing pads. In addition, a bulk voltage may be applied to the well through the other probing pad. The present invention can test selected cells using only 10 to 13 probing pads. In addition, since only the decoding circuit needs to be added to the front of the cell pattern for mass production, the measurement difference between the normal cell string and the test pattern can be resolved. In addition, the mismatch can be eliminated in setting pulse failing and rising time when measuring programs and program disturbs.

Table 1 is a voltage table for explaining the operation of the test pattern according to the present invention.

Condition Selected wordline Unselected wordline Selected bitline Unselected Bitline DSL SSL Well Read 0 V 4.5V 1 V 0 V 4.5V 4.5V 0 V Program 18V 10 V 0 V 0 V 4.5V 0 V 0 V Inhibit Program 18V 10 V Vcc Vcc 4.5V 0 V 0 V Erase 0 V 0 V F F F F 20 V

Referring to Table 1, the voltages shown in the table are applied to the test pattern of the NAND flash memory device through the probing pads according to the respective operations, and the word lines and the selected word lines are selected through the combination of the probing pad signals by the decoding circuit. Different voltages are applied by dividing the unresolved word lines. 'F' refers to being floated. A high-voltage transistor can be bonded in front of the cell wordline to make the cell codeable. When a select voltage is applied to a selected word line by inserting an inverter behind the word line to apply a bias to the word line, a pass voltage may be applied to word lines that are not automatically selected.

As described above, the present invention places a decoding circuit on a word line of a NAND flash memory cell to decode a signal input from a small number of probing pads, thereby selecting one word line and applying a selection voltage to the remaining word lines. A pass voltage can be applied. In addition, by increasing the number of cells that can be measured using a decoder, defects that may occur during main mass production can be prevented, and failure modes during main mass production can be analyzed in a timely manner, thereby shortening the product development period. In addition, the interdependence of the characteristics of the production chip and the test pattern can be increased.

Claims (3)

A plurality of cell strings in which a plurality of cells are connected in series; A plurality of word lines and bit lines for selecting cells in the cell string; A drain select transistor connected between the drain terminal of the cell string and the bit line and driven according to a drain select signal; A source select transistor connected between a source terminal of the cell string and a common source line and driven according to a source select signal; And And a decoding circuit configured to apply a selection voltage to a word line selected according to an external signal and apply a pass voltage to the unselected word lines. The test pattern of claim 1, wherein the decoding circuit receives a predetermined control signal from a probing pad and generates one selected voltage and 31 pass voltages. The method of claim 1, wherein the drain selection signal is applied to a gate terminal of the drain selection transistor through a first probing pad, and the source selection signal is applied to a gate terminal of the source selection transistor through a second probing pad. The test pattern of the flash memory device to apply a common source voltage to the common source line through a third probing pad, and to apply a charging voltage to the bit line through a fourth probing pad.

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