KR100624138B1 - Flat panel display device - Google Patents

Abstract

Disclosed is a flat panel display in which a display panel is divided into a main panel and a sub panel so that an image is displayed. The flat panel display device uses an active organic electroluminescent display panel and a liquid crystal display panel or a liquid crystal display panel and an active organic electroluminescent display panel, respectively, as the main panel and the sub panel. In addition, one data driver for driving the main panel and the sub-panel in common. Therefore, power consumption and the cost of manufacturing the flat panel display are reduced through the flat panel display.

Organic electroluminescent display, liquid crystal display, main panel, sub panel

Description

Flat Panel Display Device

1 is a block diagram illustrating a conventional flat panel display device having a dual panel.

2 is a block diagram illustrating another flat panel display device having a conventional dual panel.

3A is a block diagram illustrating a flat panel display device according to a first embodiment of the present invention.

FIG. 3B is a circuit diagram illustrating a pixel circuit of a plurality of main pixels illustrated in FIG. 3A.

FIG. 3C is a circuit diagram illustrating a pixel circuit of a plurality of sub pixels illustrated in FIG. 3A.

4A is a block diagram illustrating a flat panel display device according to a second exemplary embodiment of the present invention.

FIG. 4B is a circuit diagram illustrating a pixel circuit of a plurality of main pixels illustrated in FIG. 4A.

4C is a circuit diagram illustrating a pixel circuit of a plurality of sub pixels illustrated in FIG. 4A.

The present invention relates to a flat panel display having a main panel and a sub panel, and more particularly, the main panel and the sub panel are each provided with an active organic electroluminescent display panel and a liquid crystal display panel. The present invention relates to a flat panel display having a data driver for driving the main panel and the sub panel in common.

Recently, a flat panel display is composed of a liquid crystal display or an organic electroluminescent display. The liquid crystal display applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and adjusts the arrangement of the liquid crystals according to the strength of the electric field, thereby radiating light from an external light source (backlight). The desired predetermined image is displayed by adjusting.

An organic electroluminescent display is a flat self-emission display that emits light by applying an electric field to a phosphor coated on a glass substrate or a transparent glass film. Electroluminescence refers to a phenomenon of emitting light when an electric field is applied to the phosphor.

The organic electroluminescent display is divided into an active matrix type and a passive matrix type according to a driving method.

In the passive matrix method, an anode and a cathode are arranged in a matrix in a screen display area, and pixels are formed in an area where the anode and the cathode cross each other.

In contrast, in the active matrix method, a thin film transistor is disposed in each pixel, and each pixel is controlled using the thin film transistor.

Recently, a number of products in the form of dual panels are appearing in mobile phones.

1 is a block diagram illustrating a conventional flat panel display device having a dual panel.

Referring to FIG. 1, a passive organic electroluminescent display panel and a liquid crystal display panel are used as the sub panel 100 and the main panel 110, respectively. The sub and main data drivers 120 and 130 for driving the sub panel 100 and the main panel 110 are used.

The sub panel 100 is a passive organic electroluminescent display panel, and the main panel 110 is a liquid crystal display panel. In particular, the main panel 110 includes a thin film transistor MD, a storage capacitor Cst, and a liquid crystal Clc. The scan signal supplied from the scan driver is applied to the gate terminal of the thin film transistor MD, and the data signal supplied from the main data driver 130 is applied to the first electrode of the thin film transistor MD. When the thin film transistor MD is turned on by the scan signal, the data signal is applied to the storage capacitor Cst and the liquid crystal Clc connected to the second electrode of the thin film transistor MD.

However, the flat panel display device has a problem in that a large manufacturing cost is required by using two dedicated data drivers 120 and 130.

2 is a block diagram illustrating another type of flat panel display device having a conventional dual panel.

Referring to FIG. 2, the flat panel display device uses the same type of liquid crystal display panel as the main panel 200 and the sub panel 210. In addition, the flat panel display includes a flexible printed circuit board connecting the main data line 222 and the sub data line 212 formed in the main panel 200 and the sub panel 210.

Each pixel of the main panel 200 has a thin film transistor TM, a storage capacitor Cstm, and a liquid crystal Clcm. In addition, each pixel of the sub-panel 210 has a thin film transistor TS, a storage capacitor Csts, and a liquid crystal Clcs.

In addition, the flat panel display includes a data driver 220 for driving the main panel 200 and the sub panel 210.

However, the flat panel display device has a disadvantage in that the main panel 200 and the sub panel 210 are driven at the same time, thereby increasing the power consumption.

An object of the present invention for overcoming the above problems is that the main panel and the sub-panel are respectively provided as an active organic light emitting display panel and a liquid crystal display panel or a liquid crystal display panel and an active organic light emitting display panel, respectively, and selectively driven. The present invention provides a flat panel display having one data driver for driving the main panel and the sub panel in common.

 According to an aspect of the present invention, there is provided a main panel including a main gate line and a main data line, a main panel for displaying a main image, a sub gate line and a sub data line, and a sub panel for displaying a sub image. In the flat panel display provided,

A scan driver for generating a main scan signal or a sub scan signal and complementarily selecting the main panel or the sub panel via the main scan signal or the sub scan signal; And a data driver including a main gamma correction unit and a sub gamma correction unit to supply a gamma corrected main data signal to the main panel or to supply a gamma corrected sub data signal to the sub panel. To provide.

In addition, an object of the present invention, the main panel for displaying a main image; A sub panel for displaying a sub image; A main scan driver for supplying a main scan signal to the main panel; A sub scan driver for supplying a sub scan signal to the sub panel; A timing controller for supplying an enable signal for selectively controlling the driving of the main scan driver or the sub scan driver; And a main gamma correction unit and a sub gamma correction unit operated according to the enable signal, and a data driver for supplying a gamma corrected main data signal or a gamma corrected sub data signal to the main panel or the sub panel, respectively. It is to provide a flat panel display device comprising.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

Example 1

3A is a block diagram illustrating a flat panel display device according to a first embodiment of the present invention.

Referring to FIG. 3A, a main panel 300, a sub panel 310, a timing controller 320, a data driver 330, a scan driver 340, and a flexible printed circuit board 350 are provided.

The main panel 300 is an active organic electroluminescent display panel in a region where the main data lines MDL1-MDLm extending in the first direction and the main gate lines MGL1-MGLn extending in the second direction cross each other. A plurality of main pixels 302 are formed, and a main image is displayed.

The plurality of main pixels 302 are selected by scan signals applied through the main gate lines MGL1-MGLn, and the selected main pixels 302 are connected via the main data lines MDL1-MDLm. The main data signal is supplied to display a predetermined image.

The sub panel 310 is a liquid crystal display panel, and is formed in a region where the sub data lines SDL1-SDLm formed extending in the first direction and the sub gate lines SGL1-SGLk formed extending in the second direction cross each other. The sub pixel 312 is provided, and the sub image is displayed.

The plurality of sub pixels 312 are selected by scan signals applied through the sub gate lines SGL1-SGLk, and the plurality of sub pixels 312 are connected to the selected plurality of sub pixels 312 through sub data lines SDL1-SDLm. The sub data signal is supplied to display the sub image.

In addition, the timing controller 320 supplies a data control signal DDC and image data RGB DATA to the data driver 330. In addition, the timing controller 320 supplies a gate control signal GDC to the scan driver 340. The main panel 300 and the sub panel 310 are complementarily selected by applying the data control signal DDC or the gate control signal GDC.

The data driver 330 includes a main gamma correction unit 332 and a sub gamma correction unit 334.

The main gamma correction unit 332 performs gamma correction on the main data signal supplied to the main panel 300, and the sub gamma correction unit 334 corrects the gamma correction on the sub data signal supplied to the sub panel 310. Do this.

FIG. 3B is a circuit diagram illustrating respective pixels of the main panel illustrated in FIG. 3A according to an exemplary embodiment of the present invention.

Referring to FIG. 3B, the pixel circuit is composed of an organic electroluminescent device OLED, two transistors M1, M2 and a capacitor Cst1.

The switching transistor M1 transfers a main data signal supplied from the main data line MDLm in response to a scan signal supplied from the main gate line MGLn. That is, the first electrode of the switching transistor M1 receives the main data signal from the main data line MDLm and supplies it to the gate terminal of the capacitor Cst1 and the driving transistor M2 through the second electrode.

The driving transistor M2 receives the main data signal through the gate terminal and receives a positive power supply voltage Vdd through the first electrode. In addition, the second electrode of the driving transistor M2 is connected to the organic electroluminescent device OLED.

The capacitor Cst1 maintains the voltage Vsg between the source and the gate of the driving transistor M2 for a period of time.

The organic electroluminescent device OLED has an anode connected to the second electrode of the driving transistor M2, a cathode connected to the line supplying the negative power supply voltage Vss, and corresponds to a current supplied from the driving transistor M2. It will emit light. However, in the pixel circuit, it is apparent to those skilled in the art that the number of thin film transistors and the number of capacitors may be variously changed according to the embodiment.

FIG. 3C is a circuit diagram illustrating pixels constituting the sub-panel shown in FIG. 3A.

Referring to FIG. 3C, the pixel circuit includes a switching transistor S1, a liquid crystal capacitor Clc, and a storage capacitor Cst2.

The switching transistor S1 transfers the sub data signals supplied from the sub data lines SDLm in response to the scan signals supplied to the sub gate lines SGLk.

The liquid crystal capacitor Clc has a predetermined alignment state according to the sub data signal applied between the pixel electrode and the common electrode, and a gray level of an image is expressed according to the alignment state.

The storage capacitor Cst2 maintains the sub data signal for a period of time.

Those skilled in the art may use the main panel 300 and the sub panel 310 as a liquid crystal display panel and an active organic electroluminescent display panel, respectively.

Referring back to FIG. 3A, the timing controller 320 uses a synchronization signal (vertical synchronization signal and horizontal synchronization signal) supplied from an external system to control the data driver control signal DDC and the scan for controlling the data driver 330. The gate control signal GDC for controlling the driver 340 is supplied.

In addition, the timing controller 320 receives and rearranges a data signal supplied from the external system (not shown) and supplies the rearranged data signal to the data driver 330 in the form of a digital signal.

The scan driver 340 receives the gate control signal GDC, supplies a scan signal to the plurality of main pixels 302 through the main gate lines MGL1-MGLn, and supplies the sub gate lines SGL1-SGLk. The scan signal is supplied to the plurality of sub-pixels 312 through.

The data driver 330 converts the digital data signal supplied from the timing controller 320 into an analog data signal using a gamma voltage according to the data driver control signal DDC. The analog data signal is selectively supplied to the plurality of main pixels 302 or the plurality of sub pixels 312 through data lines commonly formed in the main panel 300 and the sub panel 310.

In more detail, the data driver 330 includes a main gamma corrector 332 and a sub gamma corrector 334. The main gamma correction unit 332 is operated while a main scan signal is supplied to the main pixel 302 through the main gate lines MGL1-MGLn. The sub gamma correction unit 334 is operated while a sub scan signal is supplied to the plurality of sub pixels 312 through the sub gate lines SGL1-SGLk.

Accordingly, a main data signal gamma corrected through the main gamma corrector 332 is supplied to the plurality of main pixels 302 through the data line, and a main image is displayed on the main panel 300. In addition, a sub data signal gamma corrected by the sub gamma corrector 334 is supplied to the plurality of sub pixels 312 through the data line, and a sub image is displayed on the sub panel 310.

The flexible printed circuit board 350 connects the main data lines MDL1-MDLm and the sub data lines SDL1-SDLm formed in the main panel 300 and the sub panel 310, respectively. . As a result, the main panel 300 and the sub panel 310 are driven by one data driver 330.

Example 2

4A is a block diagram illustrating a flat panel display device according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, the flat panel display includes a main panel 400, a sub panel 410, a timing controller 420, a data driver 430, an inverter 440, a main scan driver 450, and a sub scan driver. 460 and the flexible printed circuit board 470.

The main panel 400 is an active organic electroluminescent display panel in a region where main data lines MDL1-MDLm extending in a first direction and main gate lines MGL1-MGLn extending in a second direction cross each other. A plurality of main pixels 402 are formed to display main data signals.

The plurality of main pixels 402 are selected by a scan signal applied through the main gate lines MGL1-MGLn, and the plurality of main pixels 402 are connected to the selected plurality of pixels 402 through the main data lines MDL1-MDLm. The main data signal is supplied to display a predetermined image.

The sub panel 410 is a liquid crystal display panel, and is formed in a region where the sub data lines SDL1-SDLm formed extending in the first direction and the sub gate lines SGL1-SGLk formed extending in the second direction cross each other. And a sub pixel 412 to display a sub image.

The plurality of sub pixels 412 is selected by a scan signal applied through the sub gate lines SGL1-SGLk, and the plurality of sub pixels 412 are connected to the selected plurality of sub pixels 412 through sub data lines SDL1-SDLm. The sub data signal is supplied to display the sub image.

In addition, the timing controller 420 supplies a data control signal DDC and image data RGB DATA to the data driver 430. In addition, the timing controller 420 supplies a gate control signal GDC to the main scan driver 450 and the sub scan driver 460. The enable signal EN is output from the timing controller 420 and applied to the inverter 440 and the sub scan driver 460. The main scan driver 450 and the sub scan driver 460 are complementarily selected by the enable signal EN, and the main panel 400 and the sub panel 410 are complementarily selected.

The inverter 440 receives the enable signal EN from the timing controller 420, inverts it, and supplies the inverted enable signal EN ′ to the main scan driver 450.

The data driver 430 includes a main gamma correction unit 432 and a sub gamma correction unit 434.

The main gamma correction unit 432 performs gamma correction on the main data signal supplied to the main panel 400, and the sub gamma correction unit 434 corrects the gamma correction on the sub data signal supplied to the sub panel 410. Do this.

The main scan driver 450 supplies scan signals to the main panel 400 through the main gate lines MGL1-MGLn according to the gate control signal GDC. In addition, the main scan driver 450 is activated according to the inverted enable signal EN '.

The sub scan driver 460 supplies the scan signals to the sub panel 410 through the sub gate lines SGL1-SGLk according to the gate control signal GDC. In addition, the sub scan driver 460 is activated according to the enable signal EN.

FIG. 4B is a circuit diagram illustrating respective pixels constituting the main panel shown in FIG. 4A.

Referring to FIG. 4B, the pixel circuit is composed of an organic electroluminescent device OLED, two transistors M3, M4 and a capacitor Cst3.

The switching transistor M3 transfers the main data signal supplied from the main data line MDLm in response to the scan signal supplied from the main gate line MGLn. That is, the first electrode of the switching transistor M3 receives the main data signal from the main data line MDLm and supplies it to the gate terminal of the capacitor Cst3 and the driving transistor M2 through the second electrode.

The driving transistor M4 receives the main data signal through the gate terminal and receives a positive power supply voltage Vdd through the first electrode. In addition, the second electrode of the driving transistor M4 is connected to the organic electroluminescent device OLED.

The capacitor Cst3 maintains the voltage Vsg between the source and gate of the driving transistor M2 for a period of time.

The organic electroluminescent device OLED has an anode connected to the second electrode of the driving transistor M4, a cathode connected to the line supplying the negative power supply voltage Vss, and corresponds to a current supplied from the driving transistor M2. It will emit light. However, in the pixel circuit, it is apparent to those skilled in the art that the number of thin film transistors and the number of capacitors can be variously changed according to the embodiment.

4C is a circuit diagram illustrating a pixel circuit of a plurality of sub pixels illustrated in FIG. 4A.

Referring to FIG. 4C, the pixel circuit includes a switching transistor S2, a liquid crystal capacitor Clc, and a storage capacitor Cst4.

The switching transistor S2 transfers the sub data signals supplied from the sub data lines SDL1-SDLm in response to a scan signal supplied to the sub gate lines SGL1-SGLk.

The liquid crystal capacitor Clc has a predetermined alignment state according to the sub data signal applied between the pixel electrode and the common electrode, and a gray level of an image is expressed according to the alignment state.

The storage capacitor Cst4 maintains the sub data signal for a period of time.

Those skilled in the art may use the main panel 400 and the sub panel 410 as a liquid crystal display panel and an active organic electroluminescent display panel, respectively.

Referring back to FIG. 4A, the timing controller 420 uses data for controlling the data driver 430 using synchronization signals (vertical synchronization signal, horizontal synchronization signal, etc.) supplied from an external system (not shown). A control signal DDC and a gate control signal GDC for controlling the main scan driver 450 and the sub scan driver 460 are supplied. The timing controller 420 also provides an enable signal EN for selectively driving the main scan driver 450 or the sub scan driver 460. The main gamma corrector 432 or the sub gamma corrector 434 of the data driver 430 is selectively driven by the enable signal EN.

In more detail, the enable signal EN is supplied to the sub scan driver 460 and the sub gamma voltage circuit unit 434. In addition, the enable signal EN supplied to the inverter 440 is inverted by the inverter 440, and the inverted enable signal EN 'is converted into the main scan driver 450 and the main gamma voltage. Supplied to the circuit portion 432. Accordingly, when the main scan driver 450 and the main gamma voltage circuit unit 432 are operated, the sub scan driver 460 and the sub gamma voltage circuit unit 430 are not operated.

In addition, the timing controller 420 receives and rearranges a data signal supplied from the external system (not shown), and arranges the rearranged data signal RGB DATA in the form of a digital signal to the data driver 430. Supply.

The inverter 440 inverts the state of the enable signal EN supplied from the timing controller 420, and converts the inverted enable signal EN ′ into the main scan driver 450 and the main gamma voltage circuit unit 432. To feed. Accordingly, when the main scan driver 450 and the main gamma voltage circuit unit 432 are operated, the sub scan driver 460 and the sub gamma voltage circuit unit 434 are not operated. On the contrary, when the main scan driver 450 and the main gamma voltage circuit unit 432 are operated, the sub scan driver 460 and the sub gamma voltage circuit unit 434 are not operated.

The data driver 430 converts the digital data signal RGB DATA supplied from the timing controller 420 into an analog data signal using a gamma voltage. The analog data signal is selectively supplied to the main panel 400 or the sub panel 410 through data lines common to the main and sub panels 400 and 410 according to the enable signal EN. .

In more detail, when the enable signal EN is supplied to the data driver 430 and the sub gamma voltage circuit unit 434 is selected, the sub gamma voltage circuit unit 434 is supplied with the digital data signal. A gamma voltage suitable for the sub panel 410 is generated to supply the gamma voltage to the sub panel 410. When the inverted enable signal EN 'is supplied to the data driver 430 and the main gamma voltage circuit unit 432 is selected, the sub gamma voltage circuit unit 434 is supplied with the digital data signal to the main panel. A gamma voltage suitable for 400 is supplied to the main panel 400.

The main scan driver 450 is driven simultaneously with the main gamma voltage circuit unit 432 according to the state of the enable signal EN ′ inverted by the inverter 440. In this case, the main scan driver 450 supplies a scan signal to the gate lines MGL1-MGLn of the main panel 400 in response to the gate control signal GDC supplied from the timing controller 420. Therefore, the plurality of main pixels 402 included in the main panel 400 are selected by the scan signal. The main data signal generated by the main gamma voltage circuit unit 432 is supplied to the selected plurality of main pixels 402 in the form of an analog signal and displayed.

The sub scan driver 460 is driven simultaneously with the sub gamma voltage circuit unit 434 according to the state of the enable signal EN supplied from the timing controller 420. In this case, the sub scan driver 460 supplies a scan signal to the gate lines SGL1-SGLk of the sub panel 410 in response to the gate control signal GDC supplied from the timing controller 420. Accordingly, the plurality of sub pixels 412 of the sub panel 410 is selected by the scan signal. Sub data signals generated by the sub gamma voltage circuit unit 434 are supplied to the selected plurality of sub pixels 412 in the form of analog signals and displayed.

The flexible printed circuit board 470 connects the main data lines MDL1-MDLm and the sub data lines SDL1-SDLm formed on the main panel 00 and the subpanel 410. do. As a result, the main panel 400 and the sub panel 410 are driven by one data driver 430.

The flat panel display according to the present invention includes an organic electroluminescent display panel and a liquid crystal display panel or vice versa as a main panel and a sub panel, respectively, and by selectively driving the main panel or the sub panel, power consumption can be reduced. have. In addition, the flat panel display may reduce the manufacturing cost of the flat panel display by supplying a main data signal or a sub data signal to the main panel or the sub panel through one data driver.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (14)

A flat panel display comprising a main gate line and a main data line, a main panel for displaying a main image, and a sub gate line and a sub data line, and a sub panel for displaying a sub image. A scan driver for generating a main scan signal or a sub scan signal and complementarily selecting the main panel or the sub panel via the main scan signal or the sub scan signal; And And a data driver for supplying a gamma corrected main data signal to the main panel or for supplying a gamma corrected sub data signal to the sub panel.  The display panel of claim 1, wherein the main panel is an active organic electroluminescent display panel.  And the sub-panel is a liquid crystal display panel.  The method of claim 1, wherein the main panel is a liquid crystal display panel,  And the sub-panel is an active organic electroluminescent display panel.  The flat panel display of claim 2 or 3, wherein the main gamma correction unit is operated in synchronization with the main scan signal, and the sub gamma correction unit is operated in synchronization with the sub scan signal.  The method of claim 4, wherein the main data line and the sub data line,  Flat panel display, characterized in that used in common.  The flat panel display of claim 5,  And a flexible printed circuit board for connecting the main data line and the sub data line. A main panel for displaying a main image; A sub panel for displaying a sub image; A main scan driver for supplying a main scan signal to the main panel; A sub scan driver for supplying a sub scan signal to the sub panel; A timing controller for supplying an enable signal for selectively controlling the driving of the main scan driver or the sub scan driver; And A main gamma correction unit and a sub gamma correction unit operated according to the enable signal, and a data driver for supplying a gamma corrected main data signal or a gamma corrected sub data signal to the main panel or the sub panel, respectively. Flat panel display device. The display panel of claim 7, wherein the main panel is an active organic light emitting display panel. And the sub-panel is a liquid crystal display panel. The method of claim 7, wherein the main panel is a liquid crystal display panel, And the sub-panel is an active organic electroluminescent display panel. The flat panel display of claim 8 or 9, And an inverter for inverting the enable signal. The method of claim 10, wherein the enable signal, And the sub-scan driver and the sub-gamma correction unit in common.  The method of claim 11, wherein the inverted enable signal, And the main scan driver and the main gamma correction unit in common. The method of claim 12, wherein the main data line and the sub data line, Flat panel display, characterized in that used in common. The flat panel display of claim 13, wherein And a flexible printed circuit board for connecting the main data line and the sub data line.

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