KR100624133B1 - Emission driver and organic electro luminescence display device having the same - Google Patents

Abstract

An organic light emitting display device including a light emission control driver for supplying a light emission control signal to a pixel portion in a panel is disclosed. The light emission control driver includes a shift register composed of a plurality of flip-flops and a logic calculator having a logic gate configured to receive two consecutive output signals of the shift register and perform a logic sum operation. Each logic gate performs a logic sum operation of input signals, and outputs one emission control signal. The flip-flop is made of a P-type MOSFET to facilitate a system on panel (SOP).

Description

Light emission control driving device and organic light emitting display device including same {Emission Driver and Organic Electro Luminescence Display Device having the same}

1 is a block diagram of a conventional organic light emitting display device.

2 is a block diagram of an organic light emitting display device using a tiling technology according to an exemplary embodiment of the present invention.

3 is a configuration diagram of an EL display panel according to an embodiment of the present invention.

4 is a circuit diagram of a pixel according to an exemplary embodiment of the present invention.

5 is a circuit diagram of a pixel according to another exemplary embodiment of the present invention.

6 is a timing diagram for describing an operation of the pixel circuit of FIG. 4 or 5.

7 is a configuration diagram of a light emission control driver according to an exemplary embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a flip-flop of the emission control driver shown in FIG. 7.

FIG. 9 is a circuit diagram illustrating an inverter of the flip-flop illustrated in FIG. 8.

FIG. 10 is a circuit diagram illustrating a logic gate of the light emission control driver illustrated in FIG. 7.

11 is a timing diagram for describing an operation of a light emission control driver according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: pixel portion

250: light emission control driver

260: shift register

270 logical operation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device. Specifically, in order to implement a SOP (System On Panel), a light emission control driver is designed as a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The present invention relates to an organic light emitting display device.

When a light emission control transistor for controlling light emission of the light emitting device is added to the pixel circuit, the organic light emitting display device includes a light emission control driving device for providing a light emission control signal to the light emission control transistor.

Recently, flat panel display devices have been actively researched. In particular, organic light emitting display devices have attracted attention as next generation flat panel display devices due to their excellent luminance and viewing angle characteristics.

Unlike the liquid crystal display, the organic light emitting display device uses a light emitting diode that emits a specific light without requiring a separate light source unit. Such a light emitting diode emits light corresponding to the amount of driving current flowing into the anode electrode.

1 is a block diagram of a conventional organic light emitting display device.

The organic light emitting display device includes a pixel unit 10, a scan driver 20, a data driver 30, and a light emission control driver 40.

The pixel unit 10 includes a plurality of pixels P11 to Pnm positioned in an area where a plurality of scan lines S1 to Sn, a plurality of data lines D1 to Dm, and a plurality of emission control lines E1 to En cross each other. And a predetermined image is displayed according to the applied data voltage.

The scan driver 20 sequentially supplies scan signals to the scan lines S1 to Sn in response to a scan control signal from a timing controller (not shown), that is, a start pulse and a clock signal.

The data driver 30 supplies data voltages corresponding to the R, G, and B data to the data lines D1 to Dm in response to a data control signal supplied from a timing controller (not shown).

The emission control driver 40 sequentially supplies emission control signals to emission control lines E1 to En in response to a start pulse and a clock signal from a timing controller (not shown).

Since the switching element of the conventional light emission control driver 40 requires a fast response speed, N type and P type MOSFETs formed on a silicon substrate are used through a CMOS (Complementary Metal Oxide Semiconductor) process. Therefore, the light emission control driver 40 is not composed of only the P-type MOSFETs that are frequently used in the pixel unit 10, and thus the light emitting control driver 40 and the transistors of the pixel unit 10 cannot be manufactured in the same process.

The light emission control driver 40 is attached to a panel on which the pixel portion 10 is formed by a tape carrier package (TCP) method which is manufactured as a separate integrated circuit and mounted on a tape film connected to the panel. In addition, the pixel unit 10 may be directly mounted on the glass substrate, which is called a chip on glass (COG) method. However, this method has a problem in that the production yield is lowered and the manufacturing cost is increased due to the complicated process.

Therefore, in recent years, a driving unit is designed in a panel in which the pixel unit 10 is formed to implement a system on panel (SOP) for simultaneously manufacturing circuits of the pixel unit 10 and circuits of the driving unit. In particular, in the case of an organic light emitting display device using tiling in which a plurality of panels are joined to form one panel, the surface on which the integrated circuit forming the driving unit can be bonded to the panel is reduced. Therefore, it is necessary to design a part of the driving part directly on the panel by the SOP method.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a light emission control driver which is designed in an SOP method inside an EL display panel to control light emission of pixels.

According to an aspect of the present invention, a pixel unit for displaying an image includes: a scan driver for sequentially supplying a scan signal to the pixel unit; A data driver for supplying a data signal to the pixel portion; And a light emission control driver for supplying a light emission control signal to the pixel unit, wherein the light emission control driver receives a start pulse and supplies a plurality of flip-flops in synchronization with a clock signal and a clock signal inverted. ; And a plurality of logic gates receiving two output signals from two adjacent flip-flops and performing a logic sum operation to supply a light emission control signal to the pixel portion. do.

In addition, the present invention for achieving the above object, a first flip-flop is applied to the start pulse, and generates an output signal in synchronization with the clock signal and the clock signal inverted; A second flip-flop receiving an output signal of the first flip-flop and generating an output signal in synchronization with the clock signal and the inverted clock signal; And a logic gate configured to receive output signals from the first flip-flop and the second flip-flop, and perform a logic sum operation to supply a light emission control signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

2 is a block diagram of an organic light emitting display device using a tiling technology according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an organic light emitting display device according to an exemplary embodiment of the present invention includes a large panel formed by bonding a plurality of EL display panels 1 to 8 and data connected to each EL display panel 1 to 8. It consists of the drive parts 1-8.

One EL display panel 400 and one data driver 300 connected to the EL display panel 400 constitute one sub organic light emitting display device 450 constituting the organic light emitting display device.

Each EL display panel 400 is electrically connected to the data driver 300. Electrical connection between one EL display panel 400 and the data driver 500 is achieved through a metal pattern printed on the flexible film. That is, the output terminal of the data driver 300 is electrically connected to one end of the metal pattern, and the data line provided on the EL display panel 400 is electrically connected to the other end of the metal pattern.

Each data driver 500 supplies a data signal to the pixel part through a plurality of conductive lines provided on the flexible film.

In addition, a circuit for generating a scanning signal for selecting a pixel constituting the pixel portion and a light emission control signal for controlling the light emission operation of the pixel is incorporated in the EL display panel 400. Therefore, the EL display panel 400 does not require scanning signal generating means or light emitting control signal generating means separately provided externally.

In such an EL display panel 400, the thin film transistors forming the thin film transistor, the scan driver and the light emission control driver of each pixel have polysilicon as a channel for fast response speed and uniformity. At this time, the polysilicon forms an amorphous silicon layer on the glass substrate, and then crystallizes the amorphous silicon layer into polysilicon through a Low Temperature Poly Si (LTPS) process.

One EL display panel 400 can be produced through the same manufacturing process as the panel of an organic light emitting display device used in the related art. Therefore, one large panel is formed by bonding the same several EL display panels 400 produced through the same manufacturing process. Each of the EL display panels 400 may be bonded to a neighboring EL display panel 400 by using a UV curable resin or a thermosetting resin, specifically an epoxy resin.

3 is a configuration diagram of an EL display panel according to an embodiment of the present invention.

Referring to Fig. 3, the EL display panel 400 is composed of a pixel portion 100, a scan driver 200 and a light emission control driver 250. The EL display panel 400 forms a data driver 300 and one sub organic light emitting display device 450 which are bonded to the panel by the TCP method.

In FIG. 3, the direction of pixels activated by the n-th scan signal is referred to as the first direction, and the direction perpendicular to the first direction is referred to as the second direction.

The scan driver 200 and the emission control driver 250 are positioned in the EL display panel 400, and the data driver 300 positioned outside the EL display panel 400 and the pixel unit 100 positioned in the EL display panel 400. Formed between). This is to form a driving unit for applying a data signal, a scanning signal, and a light emission control signal to one side of the pixel unit 100 in order to bond a plurality of EL display panels 400 to manufacture one organic light emitting display device.

The scan driver 200 and the emission control driver 250 receive clock signals from a timing controller (not shown) and output the scan signal and the emission control signal to the pixel unit 100.

The scan line Sn extending from the scan driver 200 is formed in the second direction. In addition, the emission control line En extending from the emission control driver 250 is formed in the second direction in parallel with the scan line Sn. The scan line Sn and the emission control line En must sequentially activate the pixels Pn1 to Pnm in the first direction with one scan signal and one emission control signal. Therefore, the scan line Sn and the emission control line En are intersected with the scan line Sn and the emission control line En by using metal wires formed in the first direction, respectively, to correspond to the pixels Pn1 to Pnm in the first direction. Connected.

Each of the metal wires is formed across the pixels Pn1 to Pnm formed in the first direction. The metal line connected to the scan line Sn is connected to the gate electrode of the thin film transistor on the pixels Pn1 to Pnm in the first direction turned on by the scan signal. In addition, the metal wiring connected to the emission control line En is connected to the gate electrode of the emission control transistor on the pixels Pn1 to Pnm in the first direction turned on by the emission control signal. The electrical connection between the scan line Sn and the emission control line En and the metal wires is achieved through the contact hole.

The pixel unit 100 includes a plurality of pixels P11 to Pnm, and one unit pixel Pnm includes red, green, and blue subpixels. The pixels P11 to Pnm are formed by repeating red, green, and blue subpixels regularly along a first direction, and repeating the same shape along the second direction.

The red, green, and blue subpixels emit red, green, and blue light corresponding to the current applied to the organic EL element OLED. Accordingly, the pixel Pnm displays a specific color by combining light emitted by the red, green, and blue subpixels forming the pixel Pnm.

In the pixel unit 100, a plurality of scan lines S1 to Sn, emission control lines E1 to En, and a plurality of data lines D1 to Dm are formed on the pixels P11 to Pnm in a second direction. .

Each pixel Pnm receives a scan signal and a light emission control signal from a metal line connected to the scan line Sn and the light emission control line En, and receives a data signal from the data line Dm to display a predetermined image. .

4 is a circuit diagram of a pixel according to an exemplary embodiment of the present invention, and FIG. 6 is a timing diagram for describing an operation of the pixel circuit of FIG. 4.

In FIG. 4, only the pixel circuit Pnm connected to the m th data line and the n th scan line is shown for convenience of description.

Referring to FIG. 4, the pixel circuit Pnm according to the exemplary embodiment of the present invention includes an organic EL element OLED, transistors M1, M2, and M3, and a capacitor Cst1.

The driving transistor M1 is a transistor for controlling the driving current flowing through the organic EL element OLED. The source electrode is connected to the power supply voltage VDD, and the drain electrode is connected to the source electrode of the light emission control transistor M3. .

The light emission control transistor M3 is connected between the drive transistor M1 and the organic EL element OLED and flows the driving current in response to a light emission control signal of the light emission control line En connected to the gate electrode. Block it.

The organic EL device OLED emits light corresponding to the amount of driving current applied from the driving transistor M1 by connecting the cathode to the power supply voltage VSS and the anode to the drain electrode of the light emitting control transistor M3. do.

The switching transistor M2 transfers the data voltage Vdata applied to the data line Dm to one electrode of the capacitor Cst1 in response to the scan signal from the scan line Sn.

One electrode of the capacitor Cst1 is connected to the gate electrode of the switching transistor M2, and the other electrode is connected to the power supply voltage VDD.

Hereinafter, the operation of the pixel circuit Pnm of the organic light emitting display device of FIG. 4 will be described using the signal waveform of FIG. 6.

First, when the n th scan signal S [n] of the low level is applied, the switching transistor M2 is turned on to apply the data voltage Vdata to one electrode of the capacitor Cst1. Therefore, the capacitor Cst1 is charged with a charge corresponding to the difference between the power supply voltage VDD and the data voltage Vdata. However, at this time, since the light emission control signal En is at a high level, the light emission control transistor M3 is turned off and no current flows to the organic EL element OLED.

Next, when the high level nth scan signal S [n] is applied and the low level light emission control signal En is applied, the light emission control transistor M3 is turned on to the organic EL element OLED. Current will flow.

5 is a circuit diagram of a pixel according to another exemplary embodiment of the present invention.

In FIG. 5, only the pixel circuit Pnm connected to the m th data line and the n th scan line is shown for convenience of description.

Referring to FIG. 5, a pixel circuit Pnm according to another exemplary embodiment of the present invention includes an organic EL element OLED, transistors M4, M5, M6, M7, and M8, and capacitors Cst2 and Cvth. .

The driving transistor M4 is a transistor for controlling the driving current flowing through the organic EL element OLED. The source electrode is connected to the power supply voltage VDD, and the drain electrode is connected to the source electrode of the light emission control transistor M8. .

An emission control transistor M8 is connected between the driving transistor M5 and the organic EL element OLED, and flows or blocks the driving current in response to an emission control signal applied to a gate electrode.

The organic EL element OLED emits light corresponding to the amount of driving current applied from the driving transistor M4 by connecting the cathode to the power supply voltage VSS and the anode to the drain electrode of the light emitting control transistor M8. do.

The first switching transistor M7 receives the data voltage Vdata in response to an nth scan signal S [n] from the scan line Sn connected to a source electrode connected to the data line Dm and connected to the gate electrode. Transfer to one electrode of the capacitor (Cst2).

One electrode of the capacitor Cst2 is connected to the drain electrode of the first switching transistor M7, and the other electrode is connected to the power supply voltage VDD.

One electrode of the capacitor Cvth is connected to the gate electrode of the driving transistor M4, and the other electrode is connected to one electrode of the capacitor Cst2.

The threshold voltage compensation transistor M5 is positioned between the gate electrode and the drain electrode of the driving transistor M4, and diode-connects the driving transistor M4 in response to the n−1 th scan signal S [n−1].

The second switching transistor M6 is positioned between the auxiliary power supply voltage Vsus and the one electrode of the capacitor Cst2, and the one of the capacitor Cst2 in response to the n-1 th scan signal S [n-1]. An auxiliary power supply voltage Vsus is applied to the electrode.

Hereinafter, the operation of the pixel circuit Pnm of the organic light emitting display device of FIG. 5 will be described using the signal waveform of FIG. 6.

First, when the low level n-1 th scan signal S [n-1] is applied, the transistors M5 and M6 are turned on. When the low level light emission control signal En is applied, the light emission control transistor M8 is applied. When is turned on, the capacitors Cst2 and Cvth are initialized.

At this time, the low level emission control signal En lasts for a short time, and maintains the high level again to block the current remaining in the driving transistor M4 from flowing to the organic EL element OLED.

When the threshold voltage compensation transistor M5 is turned on and the driving transistor M4 is diode-connected, a voltage of VDD-Vth is applied to the gate electrode of the driving transistor M4, and the second switching transistor M6 is turned on to turn on the capacitor ( The auxiliary power supply voltage Vsus is applied to one electrode of Cst2).

Therefore, the capacitor Cst2 is charged with a charge corresponding to the difference between the power supply voltage VDD and the auxiliary power supply voltage Vsus, and the capacitor Cvth is applied to the auxiliary power supply voltage Vsus and the gate electrode of the driving transistor M4. The charge corresponding to the difference between the voltages VDD-Vth is charged.

Next, when the n th scan signal S [n] of the low level is applied, the first switching transistor M7 is turned on. Therefore, the data voltage Vdata is applied to one electrode of the capacitor Cst2, and the voltage applied to the gate electrode of the driving transistor M4 becomes VDD-Vth-ΔV. In this case, ΔV means a difference between the auxiliary power supply voltage Vsus and the data voltage Vdata.

Next, when the low level light emission control signal En is applied, the light emission control transistor M8 is turned on so that the current I flowing through the output terminal of the driving transistor M4 flows to the organic EL element OLED, and thus the organic EL element. OLED emits light.

The current flowing from the drain electrode of the driving transistor M4 to the organic EL element OLED is shown in Equation 1 below.

When ΔV is substituted in Equation 1 above, the current flowing from the drain electrode of the driving transistor M4 to the organic EL element OLED is represented by Equation 2 below.

Here, VDD represents a power supply voltage, Vth represents a threshold voltage of the driving transistor M4, Vdata represents a data voltage, and Vsus represents an auxiliary supply voltage.

In the case of the auxiliary power supply voltage Vsus, since the voltage drop does not occur since it is not substantially a current source source, a pixel circuit Pnm in which Vth and IR-drop are compensated may be implemented.

Referring to FIG. 3 again, the emission control driver 250 is positioned in the EL display panel 400 and supplies an emission control signal for controlling on / off of the emission control transistor of each pixel of the pixel unit 100. do. The light emission control driver 250 may be designed as a P-type MOSFET and formed through the same process as the transistors of the pixel unit 100. Hereinafter, the light emission control driver 250 will be described in detail with reference to a preferred embodiment.

7 is a configuration diagram of a light emission control driver according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the emission control driver 250 receives a scan pulse Vsp and sequentially generates an output signal OUT in synchronization with a clock signal VCLK and an inverted clock signal VCLKB. A plurality of logic gates OR1, OR2, which are supplied with two consecutive output signals of the 260 and the shift register 260, and perform a logic sum operation to supply the emission control signal to the pixel unit 100. And a logical operation unit 270 having a ...).

The shift register 260 is composed of a plurality of flip-flops FF1, FF2, FF3, ... that are synchronized with the common clock signal VCLK and the inverted clock signal VCLKB.

The first flip-flop FF1 receives the start pulse Vsp, the clock signal VCLK, and the inverted clock signal VCLKB, and samples the start pulse Vsp at the falling edge of the clock signal VCLK. The output signal OUT1 maintained for one period is generated.

The second flip-flop FF2 receives the output signal OUT1 of the first flip-flop FF1 as an input signal and is synchronized with the clock signal VCLK and the inverted clock signal VCLKB. Accordingly, the second flip-flop FF2 samples the output signal OUT1 of the first flip-flop FF1 at the falling edge of the clock signal VCLK shifted by one clock cycle, and maintains the output signal OUT2 for one clock cycle. )

Successive flip-flops FF3, FF4, FF5, ... also receive the output signal of the previous flip-flop, sample at the falling edge of the clock signal VCLK, and sequentially output the output signal shifted by one clock cycle. .

The logic operator 270 is composed of a plurality of logic gates OR1, OR2, OR3,... Each logic gate receives two successive output signals from the flip-flops FF1, FF2, FF3,... And generates light emission control signals E1, E2, E3,... 100).

The first logic gate OR1 receives the output signal OUT1 of the first flip-flop FF1 and the output signal OUT2 of the second flip-flop FF2. The first logic gate OR1 performs a logic sum operation of the two output signals OUT1 and OUT2. That is, when at least one of the two output signals OUT1 and OUT2 has a high level, the first emission control signal E1 having a high level is generated. In addition, when both output signals OUT1 and OUT2 are low level, the first emission control signal E1 having a low level is generated.

The second logic gate OR2 receives the output signal OUT2 of the second flip-flop FF2 and the output signal OUT3 of the third flip-flop FF3. The second logic gate OR2 outputs the second emission control signal E2 by performing a logical sum operation of the two output signals OUT2 and OUT3.

The third to nth logic gates OR3 to ORn also perform the same operations as the first and second logic gates OR1 and OR2 to output the third to nth emission control signals E3 to En. .

Hereinafter, the configuration of the flip-flop and the logic gate will be described in detail.

FIG. 8 is a circuit diagram illustrating a flip-flop of the emission control driver shown in FIG. 7.

Referring to FIG. 8, the flip-flop FF1 includes two transistors M9 and M10 and two inverters INV1 and INV2.

The switching transistor M9 has a start pulse Vsp applied to the source electrode, a drain electrode connected to the first inverter INV1, and is turned on / off according to the inverted clock signal VCLKB to operate the first inverter INV1. Transmits the input signal.

The first inverter INV1 receives the output signal of the switching transistor M9, inverts it, and transfers the inverted signal to the sampling transistor M10.

The sampling transistor M10 receives the output signal of the first inverter INV1 and samples the output signal from the falling edge of the clock signal VCLK.

The second inverter INV2 receives the output signal of the sampling transistor M10, inverts it, and outputs the inverted signal to the first logic gate OR1.

The flip-flop FF1 receives the start pulse Vsp, the clock signal VCLK, and the inverted clock signal VCLKB, and outputs an output signal OUT1 having a duty equal to a clock period. The output signal OUT1 of the first flip-flop FF1 becomes an input signal of the second flip-flop FF2 again. Accordingly, the inverted clock signal VCLKB of the low level is applied to the switching transistor M9 of the second flip-flop FF2 and transferred to the first inverter INV1. 1 is inverted by the inverter INV1 and transferred to the sampling transistor M10. The sampling transistor M10 samples the output signal OUT1 of the first inverter INV1 at the next falling edge of the applied clock signal VCLK, and inverts and outputs the sampled signal by the second inverter INV2. .

Therefore, the output signal OUT2 of the second flip-flop FF2 has the same duty cycle as the output signal OUT1 of the first flip-flop FF1, and has the same duty cycle as that of the first flip-flop FF1. The output signal OUT1 is shifted by one clock period and output.

The output signal OUT1 of the first flip-flop FF1 and the output signal OUT2 of the second flip-flop FF2 become input signals of the first logic gate OR1, and the first logic gate OR1 is The first summation control signal E1 is generated by performing a logic sum operation.

Hereinafter, the configuration of the first and second inverters constituting the flip-flop will be described.

FIG. 9 is a circuit diagram illustrating an inverter of the flip-flop illustrated in FIG. 8.

Referring to FIG. 9, the first and second inverters INV1 and INV2 have the same configuration, and are formed of three transistors M11, M12, and M13, respectively.

The transistor M11 is connected with a positive power supply voltage VDD and a source electrode, and a drain electrode is connected with an output terminal (out) for extracting output signals of the inverters INV1 and INV2. The transistor M11 performs a turn on / off operation according to an input signal of the inverters INV1 and INV2, that is, an output signal of the switching transistor M9 or the sampling transistor M10, thereby applying a positive power supply voltage VDD. It passes to the output (out).

The transistor M12 has a negative power supply voltage VSS and a drain electrode connected thereto, and a source electrode connected to the output terminal out. The transistor M12 operates as an active load that adjusts the current flowing to the output terminal according to the voltage applied to the gate electrode.

The transistor M13 is connected between the gate electrode and the drain electrode of the transistor M2, and the gate electrode and the drain electrode are connected to operate as a diode. Accordingly, the transistor M13 maintains a turn-on state, and at this time, a voltage corresponding to the sum of the negative power supply voltage VDD and the threshold voltage value of the transistor M13 is applied to the gate electrode of the transistor M12 to transmit the transistor M12. To control the on / off.

In addition, the inverters INV1 and INV2 further include a capacitor C1 formed between the control electrode of the transistor M9 and the output terminal N1. When the capacitor C1 is applied with the high level clock signal VCLK and the inverted clock signal VCLKB, and the input signal applied to the inverters INV1 and INV2 is cut off, the output signal of the previous half cycle during the clock half cycle Outputs the same output signal as

Referring to the operation of the inverters INV1 and INV2, when a low level input signal is applied to the transistors M11 of the inverters INV1 and INV2, the transistor M11 is turned on. At this time, since the transistor M13 is turned on, a voltage corresponding to the sum of the negative power supply voltage VSS and the threshold voltage of the transistor M13 is applied to the gate electrode of the transistor M12. Thus, transistor M12 is turned on. Therefore, both the positive power supply voltage VDD or the negative power supply voltage VSS may be output to the output terminal out, but the turn-on resistors of the transistors M12 and M13 connected to the negative power supply voltage VSS may be output. It is designed to be larger than the turn-on resistance of the transistor M11 connected to the positive power supply voltage VDD, so that the output signal output to the output terminal has a positive power supply voltage VDD. The turn-on resistance of the transistors M11, M12, and M13 may be formed by adjusting the length of the channel (Len gth) and the width of the channel (Width).

Next, when a high level input signal is applied to the transistors M11 of the inverters INV1 and INV2, the transistor M11 is turned off. Therefore, the voltage at the output terminal (out) is gradually changed to the low level through the transistor M12 that is already turned on. At this time, the capacitor C1 formed between the gate / source of the transistor M12 maintains the voltage between the gate / source before the transistor M11 is turned off. For example, when the positive power supply voltage VDD is 5V and the negative power supply voltage VSS is -7V, the voltage at which the transistor M11 is turned on and output to the output terminal is 5V, and the transistor M12 is ), The gate voltage is -7V. Therefore, in order to maintain a constant voltage, the capacitor C1 changes the gate voltage of the transistor M12 to a low level as the voltage at the output terminal out changes to a low level. At this time, while the gate voltage of the transistor M12 changes to a low level, a reverse bias voltage is applied to the transistor M13, and the transistor M13 is turned off. Therefore, the transistor M12 remains turned on by the parasitic capacitor Cgs even when the transistor M13 is turned off, and the output terminal changes to -7V, which is a negative power supply voltage VDD level, so that Output the output signal.

In addition, when the high level clock signal and the inverted clock signal are applied to the sampling transistor M10 of the flip-flop FF1 for a half clock period, the input signal is not applied to the inverter INV2. At this time, the capacitor C1 of the inverter INV2 supplies a voltage having a level corresponding to the output signal during the previous clock half cycle to the output terminal out. Accordingly, the flip-flop FF1 generates the high level output signal OUT for one clock period.

Hereinafter, a logic operation unit 270 that receives two successive output signals from the shift register 260 and performs their logic sum operation to sequentially output the light emission control signals will be described.

FIG. 10 is a circuit diagram illustrating a logic gate of the light emission control driver shown in FIG. 7.

Referring to FIG. 10, one logic gate OR1 generating one light emission control signal E1 is formed between the positive power supply voltage VDD and the first output terminal N1 and adjacent two flip-flops. Two input signals OUT1 and OUT2 outputted continuously from (FF1 and FF2) are applied between the input unit 271 and the negative power supply voltage VSS and the first output terminal N1. In response to the on / off operation of the input unit 271, the output signals of the first active load 277 and the first output terminal N1 that control the current flowing to the first output terminal N1 are inverted to generate the light emission control signal ( An inverter 273 for outputting E1).

The input unit 271 includes two transistors M14 and M15 connected in series between the positive power supply voltage VDD and the first output terminal N1. In the transistor M14, the source electrode is connected to the positive power supply voltage VDD and the drain electrode is connected to the source electrode of the transistor M15 to receive the output signal OUT1 of the first flip-flop FF1. On / off In the transistor M15, a source electrode is connected to the drain electrode of the transistor M14, and a drain electrode is connected to the first output terminal N1 to receive the output signal OUT2 of the second flip-flop FF2. Works off.

Therefore, only when the output signal OUT1 of the first flip-flop FF1 and the output signal OUT2 of the second flip-flop FF2 have a low level at the same time, the input unit 271 is the positive power supply voltage VDD. Is transmitted to the first output terminal (N1), otherwise it is turned off.

The first active load 277 has a negative power supply voltage VSS connected to the drain electrode, a first output terminal N1 connected to the source electrode, and a negative power supply voltage VSS according to the voltage applied to the gate electrode. ) Has a transistor M16 that transfers.) To a first output terminal N1. A transistor M17 for controlling the gate voltage of the transistor M16 is formed between the gate electrode and the drain electrode of the transistor M16. The transistor M17 is diode-connected to remain turned on. These transistors M16 and M17 are turned on when the input unit 271 is turned on and a positive power supply voltage VDD is applied to the first output terminal N1 to turn the negative power supply voltage VSS to the first output terminal. To pass. Therefore, the turn-on resistance of the transistors M14 and M15 of the input unit 271 is designed to be smaller than the turn-on resistance of the transistors M16 and M17 so that the first output terminal N1 outputs a positive power supply voltage VDD. Do it. The turn-on resistance of these transistors M14, M15, M16, and M17 can be adjusted by the length and width of the channel of the transistor.

When the input unit 271 is turned off, the first output terminal N1 is changed to a negative power supply voltage VSS level, and the gate voltage of the transistor M16 is also low level according to the voltage variation of the first output terminal N1. To change. This change in voltage can be achieved by a capacitor between the source / gate of transistor M16. Effectively, capacitor C2 is additionally formed to maintain the source / gate voltage of transistor M16. As the gate voltage of the transistor M16 continues to fall, the transistor M17 is turned off by applying a reverse bias voltage, and the transistor M16 is turned on by the capacitor C2. Accordingly, the first output terminal N1 outputs a signal having a negative power supply voltage VSS level.

The inverter 273 receives the output signal of the first output terminal N1 and inverts it to output the light emission control signal E1 to the second output terminal N2.

The inverter 273 is formed between the positive power supply voltage VDD and the negative power supply voltage VSS, and is connected to the positive power supply voltage VDD or the negative power supply voltage by the output signal of the first output terminal N1. And transistors M18, M19, and M20 for selectively outputting VSS.

The transistor M18 has a source electrode connected to a positive power supply voltage VDD, a drain electrode connected to a second output terminal N2, and turned on / off according to an output signal of the first output terminal N1. The positive power supply voltage VDD is transferred to the second output terminal N2.

The transistor M19 has a negative power supply voltage VSS and a drain electrode connected thereto, a source electrode connected to the second output terminal N2, and turned on / off according to a voltage applied to the gate electrode N2. It acts as an active load 275 that controls its output current.

The transistor M20 is formed by diode connection between the gate electrode and the drain electrode of the transistor M19. Accordingly, the transistor M20 maintains a turn-on state to apply a voltage corresponding to the sum of the negative power supply voltage VSS and the threshold voltage of the transistor M20 to the gate electrode of the transistor M19.

In addition, the inverter 273 may further include a capacitor C3 formed between the gate electrode of the transistor M19 and the second output terminal N2. The capacitor C3 maintains the turn-on state of the transistor M19 by maintaining a constant voltage between the gate electrode and the source electrode of the transistor M19 even when the transistor M20 is turned off.

Referring to the operation of the inverter 273, when a low level input signal is applied to the transistor M18 of the inverter 273, the transistor M18 is turned on. At this time, the transistor M20 is turned on to apply a voltage corresponding to the sum of the negative power supply voltage VSS and the threshold voltage of the transistor M20 to the gate electrode of the transistor M19. Thus, transistor M19 is also turned on. Since the inverter 273 needs to generate a high level output signal with respect to the low level input signal, the turn-on resistance of the transistors M19 and M20 connected to the negative power supply voltage VSS is positive in the power supply voltage VDD. It is designed to be larger than the turn-on resistance of the transistor M18 that is connected to. Therefore, the emission control signal E1 output to the second output terminal N2 has a high level of positive power supply voltage VDD. The turn-on resistance of the transistors M18, M19, and M20 may be adjusted by adjusting the length of the channel and the width of the channel.

Next, when a high level input signal is applied to the transistor M18 of the inverter 273, the transistor M18 is turned off. Accordingly, the voltage of the second output terminal N2 gradually changes to the low level through the transistor M19 that is already turned on. At this time, the capacitor C3 formed between the gate / source of the transistor M19 maintains the voltage between the gate / source before the transistor M18 is turned off. For example, when the positive power supply voltage VDD is 5V and the negative power supply voltage VSS is -7V, the voltage of the transistor M18 is turned on and output to the second output terminal N2 is 5V. The gate voltage of M19 is -7V. Therefore, in order to maintain a constant voltage, the capacitor C3 also changes the gate voltage of the transistor M19 to a low level as the voltage of the second output terminal N2 changes to a low level. At this time, while the gate voltage of the transistor M19 is changed to the low level, the reverse bias voltage is applied to the transistor M20, and the transistor M20 is turned off. Thus, the transistor M19 remains turned on by the capacitor C3 even when the transistor M20 is turned off. The second output terminal N2 changes to a negative power supply voltage VSS level of -7V to output the low level light emission control signal E1.

Hereinafter, the operation of the logic gate according to the output signals OUT1 and OUT2 of the successive flip-flops FF1 and FF2 will be described.

When the output signal OUT1 of the first flip-flop FF1 applied to the input unit 271 is at a low level, and the output signal OUT2 of the second flip-flop F2 is also at a low level, the input unit 271 is provided. Is turned on to output the output signal of the positive power supply voltage VDD to the first output terminal N1.

The output signal of the first output terminal N1 turns off the transistor M18 of the inverter 273. Accordingly, the second output terminal N2 outputs the low level emission control signal E1 corresponding to the negative power supply voltage VSS through the transistor M19 that is already turned on.

Next, the output signal OUT1 of the first flip-flop FF1 applied to the input unit 271 is at a low level, and the output signal OUT2 of the second flip-flop FF2 is at a high level, or a first flip. The case where the output signal OUT1 of the flop FF1 is high level and the output signal OUT2 of the second flip-flop FF2 is low level will be described.

In this case, since the transistors M14 and M15 of the input unit 271 are connected in series, the input unit 271 is turned off. When the input unit 271 is turned off, the first output terminal N1 changes to a negative power supply voltage VSS level, and the voltage of the gate electrode of the transistor M16 is changed according to the voltage variation of the first output terminal N1. Descend. As the voltage of the transistor M16 continues to fall, the transistor M17 is turned off by applying a reverse bias voltage, and the transistor M16 is turned on by the capacitor C2. Accordingly, the first output terminal N1 outputs a low level output signal corresponding to the negative power supply voltage VSS.

Accordingly, the transistor M18 of the inverter 273 is turned on by receiving the output signal of the first output terminal N1 having a low level, and transmits a positive power supply voltage VDD to the second output terminal N2. Accordingly, a high level emission control signal E1 corresponding to the positive power supply voltage VDD is generated at the second output terminal N2.

The transistors constituting the flip-flops FF1 to FFn + 1 and the transistors constituting the logic gates OR1 to ORn are all P-type MOSFETs, and thus transistors for driving each pixel of the pixel portion 100. It can manufacture in the same process as these.

 11 is a timing diagram illustrating an operation of a light emission control driver according to an exemplary embodiment of the present invention.

Referring to FIG. 11, the plurality of flip-flops FF1 to FFn + 1 of the shift register 260 are commonly applied with the clock signal CLK and the inverted clock signal CLKB, and receive the output signal of the previous flip-flop. It is applied as an input signal.

First, when the start pulse Vsp is applied to the input of the first flip-flop FF1, the first flip-flop FF1 receives the high level output signal OUT1 at the first falling edge of the clock signal CLK. Output for one clock cycle.

Next, when the output signal OUT1 of the first flip-flop FF1 is applied to the input of the second flip-flop FF2, the second flip-flop FF2 is the second falling edge of the clock signal CLK. Outputs the high level output signal OUT2 for one clock cycle.

By repeating the above operation, when the output signal OUTn of the nth flip-flop FFn is applied to the input of the n + 1th flip-flop FFn + 1, the n + 1th flip-flop FFn + 1 ) Outputs the high level output signal OUTn + 1 for one cycle at the n + 1th falling edge of the clock signal CLK. Accordingly, the shift register 260 applies the output signals OUT1 to OUTn + 1, which are shifted every clock cycle, to the logic operation unit 270.

The logic operation unit 270 includes a plurality of logic gates OR1 to ORn, and receives the output signals OUT1 to OUTn + 1 of the flip-flop FF1 to FFn + 1 to perform a logic sum operation to control light emission. Output signals E1 to En.

The first logic gate OR1 receives the output signal OUT1 of the first flip-flop FF1 and the output signal OUT2 of the second flip-flop FF2. Therefore, when the first output signal OUT1 and the second output signal OUT2 are at the low level, the first logic gate OR1 outputs the light emission control signal E1 at a low level, and other level states. Outputs a high level light emission control signal E1.

Next, the second logic gate OR2 receives the output signal OUT2 of the second flip-flop FF2 and the output signal OUT3 of the third flip-flop FF3. Therefore, when the second output signal OUT2 and the third output signal OUT3 are at the low level, the second logic gate OR2 outputs the light emission control signal E2 at the low level, and other level states. Outputs a high level light emission control signal E2. Therefore, the second emission control signal E2 is shifted by a clock cycle than the first emission control signal E1 and output.

By repeating the above operation, the n-th logic gate ORn finally outputs the output signal OUTn of the nth flip-flop FFn and the output signal OUT n of the n + 1th flip-flop FFn + 1. +1) is authorized. Therefore, when the nth output signal OUTn and the n + 1th output signal OUTn + 1 are at a low level, the nth logic gate ORn outputs a low level emission control signal En, In other levels, the high level light emission control signal En is output.

Since the transistors forming the shift register 260 and the logic operation unit 270 are all formed of a P-type MOSFET, the SOP (System On Panel) can be easily implemented.

According to the present invention as described above, the emission control driver for applying the emission control signal to the pixel portion is formed of transistors of the same type as the transistors forming the pixel portion. Therefore, the light emission control driver can be manufactured in the same process as the pixel portion, and the process is simplified. In addition, since the connection space between the emission control driver and the panel is not required, the area of the pixel portion, that is, the image, may be increased on the substrate having a predetermined size.

In the case of an organic light emitting display device in which a plurality of panels are formed using a tiling method, an area in which the panel and the driver integrated circuit can be bonded is reduced, so that the emission control driver can be formed on the panel, which is more useful.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (16)

Pixel part for displaying images: A scan driver for sequentially supplying scan signals to the pixel portion; A data driver for supplying a data signal to the pixel portion; And A light emission control driver for supplying a light emission control signal to the pixel unit; A plurality of flip-flops receiving a start pulse and supplying an output signal in synchronization with a clock signal and an inverted clock signal; And And a plurality of logic gates receiving two output signals from two adjacent flip-flops and performing a logic sum operation to supply a light emission control signal to the pixel portion. The method of claim 1, wherein each of the flip-flops, A first transistor turned on by the inverted clock signal to transfer an input signal; A first inverter for inverting the output signal of the first transistor; A second transistor sampling an output signal of the first inverter at a falling edge of the clock signal; And And a second inverter for inverting the output signal of the second transistor. The method of claim 2, wherein the first and second inverters, A third transistor connected between a positive power supply voltage and an output terminal and turned on by an output signal of the first or second transistor to transfer the positive power supply voltage to the output terminal; And And a fourth transistor connected between a negative power supply voltage and the output terminal and controlling an amount of current flowing to the output terminal according to on / off of the third transistor. The method of claim 3, wherein the first and second inverters, And a fifth transistor connected between the negative power supply voltage and the gate electrode of the fourth transistor and diode-connected for controlling the gate voltage of the fourth transistor. The method of claim 4, wherein the first and second inverters, And a capacitor formed between the output terminal and the gate electrode of the fourth transistor to maintain a constant voltage between the output terminal and the gate electrode of the fourth transistor. The organic light emitting display device of claim 5, wherein the turn-on resistance of the third transistor is smaller than that of the fourth and fifth transistors. The organic light emitting display device of claim 6, wherein the first to fifth transistors are metal oxide semiconductor field effect transistors (P MOSFETs). The method of claim 1, And the pixel portion, the scan driver, the data driver, and the light emission control driver are formed on one substrate. The method of claim 1, The organic electroluminescent display device is characterized in that a plurality of organic electroluminescent display devices are combined in a tile form to display a single image. A first flip-flop receiving a start pulse and generating an output signal in synchronization with a clock signal inverted from the clock signal; A second flip-flop receiving an output signal of the first flip-flop and generating an output signal in synchronization with the clock signal and the inverted clock signal; And And a logic gate configured to receive output signals from the first flip-flop and the second flip-flop, and perform a logic sum operation to supply an emission control signal. The method of claim 10, wherein each of the flip-flops, A first transistor turned on by the inverted clock signal to transfer an input signal; A first inverter for inverting the output signal of the first transistor; A second transistor sampling an output signal of the first inverter at a falling edge of the clock signal; And And a second inverter for inverting the output signal of the second transistor. The method of claim 11, wherein the first and second inverters, A third transistor connected between a positive power supply voltage and an output terminal and turned on by an output signal of the first or second transistor to transfer the positive power supply voltage to the output terminal; And And a fourth transistor connected between a negative power supply voltage and the output terminal and controlling an amount of current flowing to the output terminal according to on / off of the third transistor. The method of claim 12, wherein the first and second inverters, And a fifth transistor connected between the negative power supply voltage and the gate electrode of the fourth transistor and diode-connected for controlling the gate voltage of the fourth transistor. The method of claim 13, wherein the first and second inverters, And a capacitor connected between the output terminal and the gate electrode of the fourth transistor to maintain a constant voltage between the output terminal and the gate electrode of the fourth transistor. 15. The light emission control driving device according to claim 14, wherein the turn-on resistance of the third transistor is smaller than that of the fourth and fifth transistors. 16. The light emission control driving device according to claim 15, wherein the first to fifth transistors are metal oxide semiconductor field effect transistors (P MOSFETs).

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