KR100621626B1 - Semiconductor test device using leakage current and compensation system of leakage current - Google Patents

Abstract

The present invention relates to a semiconductor inspection apparatus and a leakage current compensation system using a leakage current. The semiconductor inspection apparatus according to the present invention includes MOS transistors manufactured by the same process as the MOS transistors of the semiconductor device, and detects leakage current flowing through the MOS transistors to check whether the semiconductor device is manufactured normally or abnormally. As a result of the test, a normal or abnormal signal is generated. On the other hand, the leakage current compensation device compensates for the leakage current flowing in the semiconductor device in response to the normal or abnormal signal of the semiconductor inspection device. According to the semiconductor inspection apparatus according to the present invention, abnormally manufactured MOS transistors can be easily detected, and malfunction of the semiconductor device can be prevented in advance by the leakage current compensation device.

Description

Semiconductor Inspection Device and Leakage Current Compensation System Using Leakage Current {SEMICONDUCTOR TEST DEVICE USING LEAKAGE CURRENT AND COMPENSATION SYSTEM OF LEAKAGE CURRENT}

1 is a block diagram showing a first embodiment of a semiconductor inspection apparatus using channel leakage current according to the present invention.

2 is a graph schematically illustrating a change in leakage current according to a change in channel length.

3 is a circuit diagram illustrating an embodiment of the comparator shown in FIG. 1.

4 is a circuit diagram illustrating an embodiment of the comparator shown in FIG. 1.

5 is a circuit diagram illustrating a second embodiment of a semiconductor inspection apparatus using channel leakage current according to the present invention.

6 is a block diagram showing a first embodiment of a semiconductor inspection apparatus using a gate leakage current according to the present invention.

7 is a graph schematically illustrating a change in leakage current according to a change in oxide film thickness.

FIG. 8 is a circuit diagram illustrating an embodiment of the comparator shown in FIG. 6.

FIG. 9 is a circuit diagram illustrating an embodiment of the comparator shown in FIG. 6.

10 is a circuit diagram showing a second embodiment of the semiconductor inspection apparatus using the gate leakage current according to the present invention.

11 is a circuit diagram showing an embodiment of a leakage current compensation system according to the present invention.

FIG. 12 is a circuit diagram illustrating an embodiment of an NMOS logic circuit shown in FIG. 11.

Explanation of symbols on the main parts of the drawings

100: semiconductor inspection device using channel leakage current

200: semiconductor inspection device using the gate leakage current

110, 210: first leakage current source 120, 220: second leakage current source

130, 230: comparator 300: leakage current compensation device

310: first compensation circuit 320: second compensation circuit

400: NMOS logic circuit

The present invention relates to a semiconductor inspection apparatus and a leakage current compensation system using a leakage current.

As semiconductor manufacturing methods become more sophisticated, control over the channel length of MOS transistors becomes increasingly difficult. In addition, it has become difficult to implement MOS transistors on a wafer that require minute channel lengths. Various techniques for controlling fine channel lengths, such as shorter wavelength light sources, PSM (Phase Shift Mask), PESM (Phase Edge Shift Mask), and OPC (Optical Correct) are being studied. . However, even with such precise techniques, there are MOS transistors that are beyond the process target target channel length. These MOS transistors cause the semiconductor chip to malfunction.

In order to verify the characteristics of the MOS transistors, individual transistors or very simple circuits (eg inverter delay, ring oscillator) were fabricated together on the wafer to extract various parameters that characterize the MOS transistors. However, the complexity and miniaturization of semiconductor processes has changed the characteristics of MOS transistors, making it difficult to find parameters, which has required a lot of time. In particular, a sudden change in the leakage current due to the change in the channel length in the off mode of the MOS transistor causes a malfunction in a semiconductor chip in which hundreds of thousands or millions of MOS transistors are aggregated.

On the other hand, as the semiconductor manufacturing method is miniaturized, the thickness of the oxide film of the MOS transistor is also reduced, making it difficult to control. In addition, leakage current due to tunneling increases at a fine oxide film thickness, which causes a malfunction of a semiconductor circuit. In particular, when a MOS capacitor with a large gate area is used at both ends of the power supply, a short circuit is likely to occur due to the gate leakage current. In addition, the capacitance value of the MOS capacitor is lowered due to leakage current, causing a malfunction in the circuit using the same, and it takes a lot of time to find the cause of the malfunction.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and a first object of the present invention is to provide a semiconductor inspection apparatus for easily discriminating a MOS transistor which is abnormally manufactured and causes a malfunction due to a channel leakage current in an off mode. It is. A second object of the present invention is to provide a semiconductor inspection apparatus for easily determining a MOS transistor which is abnormally manufactured and causes a malfunction due to a gate leakage current. A third object of the present invention is to provide a leakage current compensation system for compensating for leakage current in a semiconductor device which is abnormally manufactured and has a leakage current.

The semiconductor inspection apparatus using the leakage current according to the present invention for achieving the above technical problem is for inspecting a semiconductor device including at least one MOS transistor. A semiconductor inspection apparatus according to the present invention includes a first leakage current source configured to variably generate a first leakage current depending on whether the MOS transistors are normally manufactured; A second leakage current source configured to generate a second leakage current variably depending on whether the MOS transistors are normally manufactured; And a comparator comparing the first and second leakage currents to determine whether the semiconductor device is normally manufactured. Here, when the MOS transistors are normally manufactured, the first leakage current is smaller than the second leakage current. When the MOS transistors are abnormally manufactured, the first leakage current is larger than the second leakage current.

In an embodiment, the first and second leakage current sources are MOS transistors.

In another aspect of the semiconductor inspection apparatus using the leakage current according to the present invention, in the off-mode operation, each of the semiconductor inspection apparatus using a threshold channel length (hereinafter referred to as L1) and channel length (hereinafter referred to as L1 ') smaller than L1 (hereinafter referred to as L1') A first MOS transistor designed to flow first leakage currents (hereinafter, referred to as I1 and I1 ', respectively) through the channel; In the off-mode operation, second leakage currents (hereinafter, referred to as I2 and I2 ') at channel lengths longer than L1 (hereinafter referred to as L2) and channel lengths smaller than ΔL2 (hereinafter referred to as L2') are referred to below. A second MOS transistor designed to flow through the channel; And a comparator comparing the first and second leakage currents to determine whether the semiconductor device is normally manufactured, wherein the first MOS transistor has a channel width designed such that I1 is smaller than I2 and I1 'is larger than I2'. (W1), wherein the second MOS transistor has a channel width (W2) designed such that I2 is larger than I1 and I2 'is smaller than I1'.

According to another aspect of the semiconductor inspection apparatus using the leakage current according to the present invention, the first leakage currents are respectively formed at a critical oxide thickness (hereinafter referred to as T1) and at an oxide film thickness smaller than ΔT1 (hereinafter referred to as T1 ′). A first MOS capacitor (hereinafter referred to as J1 and J1 'respectively) designed to flow through the oxide film; At the oxide thickness larger than T1 (hereinafter referred to as T2) and at an oxide thickness smaller than ΔT2 (hereinafter referred to as T2 '), the second leakage currents (hereinafter referred to as J2 and J2') are respectively passed through the oxide film. A second MOS capacitor designed to flow; And a comparator comparing the first and second leakage currents to determine whether the semiconductor device is normally manufactured, wherein the first MOS capacitor has a gate area designed such that J1 is smaller than J2 and J1 'is larger than J2'. (A1), wherein the second MOS capacitor has a gate area A2 designed such that J2 is larger than J1 and J2 'is smaller than J1'.

A leakage current compensation system according to the present invention includes a semiconductor device including at least one MOS transistor; Comparing first and second leakage currents flowing through the first and second MOS transistors, including first and second MOS transistors manufactured in the same process as the MOS transistors, and as a result of the comparison of the semiconductor device. A semiconductor inspection device for determining whether the MOS transistors are normally manufactured; And a leakage current compensator for compensating for a leakage current flowing through MOS transistors of the semiconductor device in response to an output signal of the semiconductor test device.

In this embodiment, the leakage current compensator supplies a leakage current to the MOS transistors in response to an abnormal signal of the semiconductor test apparatus when the semiconductor device is abnormally manufactured and a leakage current occurs in the MOS transistors. Characterized in that.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

I. Semiconductor inspection device using channel leakage current

1 is a view showing a first embodiment of a semiconductor inspection apparatus using a channel leakage current according to the present invention. Referring to FIG. 1, the semiconductor inspection apparatus 100 according to the present invention includes a first leakage current source 110, a second leakage current source 120, and a comparator 130.

The first and second leakage current sources 110 and 120 are composed of NMOS transistors T1 and T2, respectively. The ground voltage Vss is applied to the gates of the NMOS transistors T1 and T2 to be in an off mode in which no channel is formed. The first and second leakage current sources 110 and 120 allow the first and second leakage currents I1 and I2 to flow through the channels of the NMOS transistors T1 and T2 in the off mode, respectively. In FIG. 1, the first and second leakage current sources 110 and 120 are limited to NMOS transistors, which are merely exemplary embodiments, and the same principle may be applied to a PMOS transistor.

The comparator 130 compares the first leakage current I1 flowing through the first leakage current source 110 with the second leakage current I2 flowing through the second leakage current source I2, and as a result, the output signal. Generates (Output) It is possible to know whether the semiconductor device (not shown) to be inspected by the output signal Output is normally manufactured. Here, the semiconductor device is a circuit including a MOS transistor (for example, an NMOS logic circuit in FIG. 11) and is manufactured together with the semiconductor inspection apparatus 100.

2 is a graph schematically illustrating a change in leakage current according to a change in channel length. The horizontal axis of the graph is the channel length (L) of the MOS transistor, and the vertical axis is the leakage current (Ioff) flowing through the channel in the off mode of the MOS transistor.

Channel lengths of the NMOS transistors T1 and T2 shown in FIG. 1 are referred to as L1 and L2, respectively, and leakage currents flowing through the channels are referred to as I1 and I2, respectively. In the present specification, L1 is defined as a critical channel length and is a channel length of a transistor to be implemented in a process. In a section having a channel length smaller than L1 based on the threshold channel length L1, a change in leakage current for a unit channel length is sensitive, and in a section having a channel length larger than L1, a change in leakage current for a unit channel length is determined. Is not big. It is important to note that the vertical axis of the graph is a log scale. Therefore, the leakage current rapidly increases even if it is slightly smaller than the critical channel length in the MOS transistor process, causing a circuit malfunction. L2 is a channel length belonging to a section larger than the threshold channel length L1.

In the semiconductor manufacturing process, reduced channel lengths are referred to as L1 'and L2', respectively, and leakage currents flowing through the channels are referred to as I1 'and I2', respectively. The change amount of the channel length is ΔL1 = L1-L1 'and ΔL2 = L2-L2', respectively. If DELTA L1 = DELTA L2, the rate of change in the channel length in the semiconductor manufacturing process is larger in the smaller channel length. That is, the relationship ΔL1 / L1''ΔL2 / L2 is established.

The semiconductor inspection apparatus 100 using the channel leakage current according to the present invention,

1) When the semiconductor manufacturing process proceeds normally and the channel lengths of the first and second leakage current sources 110 and 120 are L1 and L2, respectively, the leakage current flowing through the leakage current sources 110 and 120 respectively is I2. > I1 relationship is established,

2) The leakage current flowing through the leakage current sources 110 and 120 when the semiconductor manufacturing process is abnormally progressed and the channel lengths of the first and second leakage current sources 110 and 120 are L1 'and L2', respectively. To establish a relationship where I2 '<I1',

The channel width W1 of the first leakage current source 110 and the channel width W2 of the second leakage current source 120 are determined. For example, L1 = 0.13 µm, L1 '= 0.12 µm, L2 = 0.18 µm, L2' = 0.17 µm. When I1 = 2nA, I1 '= 100nA and the channel width of the first leakage current source 110 is W1, I2 is larger than I1 and I2' is smaller than I1 'of the second leakage current source 120. Determine the channel width W2.

By implementing the circuit of FIG. 1 using the first and second leakage current sources 110 and 120 having W1 and W2 satisfying the above relationship, a MOS transistor that is out of a target channel length can be found. .

FIG. 3 is a circuit diagram showing a first embodiment of the comparator shown in FIG. 1. Referring to FIG. 3, the comparator 130 includes two NMOS transistors N1 and N2, four PMOS transistors P1 to P4, and two inverters INV1 and INV2.

When the enable signal is 'L', the PMOS transistors P1 and P4 are turned on and the NMOS transistor N3 is turned off. Thus, nodes 1 and 2 become 'H'. Since the nodes 1 and 2 are 'H', the PMOS transistors P2 and P3 are turned off and the NMOS transistors N1 and N2 are turned on. At this time, when the enable signal is set to 'H', the PMOS transistors P1 and P4 are turned off and the NMOS transistor N3 is turned on.

In the above state, if the first and second leakage current sources 110 and 120 are normally manufactured, that is, if the channel lengths are L1 and L2, respectively, the second leakage current I2 is the first leakage current I1. Since it is larger, node 2 becomes 'L' and node 1 becomes 'H'. Therefore, the output signal Output_1 becomes 'L' and Output_2 becomes 'H'.

However, if the first and second leakage current sources 110 and 120 are abnormally manufactured, that is, if the channel lengths are L1 'and L2', respectively, the second leakage current I2 'is greater than the first leakage current I1'. Since it is small, the node 2 becomes 'H' and the node 1 becomes 'L'. Therefore, the output signal Output_1 becomes 'H' and Output_2 becomes 'L'. That is, it may be known whether the semiconductor device (not shown) is normally manufactured from the output signal of the comparator 130.

4 is a circuit diagram showing a second embodiment of the comparator shown in FIG. Referring to FIG. 4, the comparator 130 is composed of two PMOS transistors P5 and P6. When the enable signal is 'H' state, the NMOS transistor N4 is turned on.

If the first and second leakage current sources 110 and 120 are normally manufactured, i.e., if the channel lengths are L1 and L2, respectively, the second leakage current I2 is greater than the first leakage current I1, so that the node 2 ) Becomes 'L', and node 1 becomes 'H'. Therefore, the output signal Output becomes 'L'.

On the other hand, if the first and second leakage current sources 110 and 120 are abnormally manufactured, that is, if the channel lengths are L1 'and L2', respectively, the second leakage current I2 'is the first leakage current I1'. Node 2 becomes 'H' and node 1 becomes 'L'. Therefore, the output signal Output becomes 'H'. Therefore, when a semiconductor device (not shown) is abnormally manufactured, an output signal 'H' is generated from the comparator 130.

5 is a circuit diagram illustrating a second embodiment of a semiconductor inspection apparatus using channel leakage current according to the present invention. Referring to FIG. 5, the semiconductor inspection apparatus according to the present invention has a structure in which two semiconductor inspection apparatuses illustrated in FIG. 4 are connected in parallel.

If the enable signal is 'H' state, the NMOS transistor N5 is turned on. If the first leakage current sources 111 and 112 and the second leakage current sources 121 and 122 are normally manufactured, i.e., if the channel lengths are L1 and L2, respectively, the second leakage current I2 is greater than the first leakage current I1. Since nodes 2 and 4 are large, nodes 2 and 4 become 'H'. Therefore, the output signal Output_1 becomes 'L' and Output_2 becomes 'H'.

However, if the first leakage current sources 111 and 112 and the second leakage current sources 121 and 122 are abnormally manufactured, that is, if the channel lengths are L1 'and L2', respectively, the second leakage current I2 'becomes Since it is smaller than the first leakage current I1 ', the nodes 2 and 4 become' H 'and the nodes 1 and 3 become' L '. Therefore, the output signal Output_1 becomes 'H' and Output_2 becomes 'L'. Therefore, the output signal may indicate whether the semiconductor device (not shown) is normally manufactured.

II. Semiconductor Inspection Device Using Gate Leakage Current

6 is a view showing a first embodiment of a semiconductor inspection apparatus using a gate leakage current according to the present invention. Referring to FIG. 6, the semiconductor inspection apparatus 200 according to the present invention includes a first leakage current source 210, a second leakage current source 220, and a comparator 230. The first and second leakage current sources 210 and 220 are each composed of NMOS transistors C1 and C2. The NMOS transistors C1 and C2 are MOS capacitors having a drain and a source connected thereto. The first and second leakage current sources 210 and 220 pass through the gates of the NMOS transistors C1 and C2 to allow the first and second leakage currents J1 and J2 to flow, respectively. In FIG. 6, the first and second current sources 210 and 220 are limited to NMOS transistors. This is merely a mere embodiment, and it is apparent to those skilled in the art that the same principle applies to a PMOS transistor.

The comparator 230 compares the first leakage current J1 flowing through the first leakage current source 210 with the second leakage current J2 flowing through the second leakage current source J2, and as a result, an output signal. Generates (Output) It is possible to know whether the semiconductor device (not shown) to be inspected by the output signal Output is normally manufactured.

7 is a graph schematically illustrating a change in leakage current according to a change in oxide film thickness. The horizontal axis of the graph is the oxide film thickness Tox of the MOS transistor, and the vertical axis is the leakage current Jg flowing through the gate of the MOS transistor.

The oxide film thicknesses of the NMOS transistors C1 and C2 are referred to as T1 and T2, respectively, and the leakage currents flowing through the gate are referred to as J1 and J2, respectively. In the present specification, T1 is defined as a critical oxide thickness and is an oxide thickness of a transistor to be implemented during the process. The change in leakage current with respect to the unit oxide film thickness is sensitive in a section smaller than this based on the critical oxide film thickness T1, and the change in leakage current with respect to the unit oxide film thickness is not large in the section larger than this. T2 is an oxide film thickness belonging to a section larger than the critical oxide film thickness T1.

The reduced oxide thicknesses in the semiconductor manufacturing process are referred to as T1 'and T2', respectively, and the leakage currents flowing through the gate are referred to as J1 'and J2', respectively. The amount of change in the oxide film thickness is ΔT1 = T1-T1 'and ΔT2 = T2-T2', respectively. If DELTA T1 = DELTA T2, the rate of change of the oxide film thickness in the semiconductor manufacturing process is larger at the smaller oxide film thickness. That is, the relationship ΔT1 / T1 '' ΔT2 / T2 is established.

Features of the semiconductor inspection apparatus 200 using the gate leakage current according to the present invention

1) When the semiconductor manufacturing process proceeds normally and the oxide film thicknesses of the first and second leakage current sources 210 and 220 are T1 and T2, respectively, the relationship of the leakage current flowing through each of J2> J1 is established.

2) When the semiconductor manufacturing process is abnormally progressed and the thicknesses of the oxide films of the first and second leakage current sources 210 and 220 are T1 'and T2', respectively, the leakage current flowing through each other is J2 '<J1'. To be established,

The gate area A1 of the first leakage current source 210 and the gate area A2 of the second leakage current source 220 are determined. For example, T1 = 28 ms, T1 '= 26 ms, T2 = 34 ms, T2' = 32 ms. When J1 = 1pA, J1 '= 1nA and the gate area of the first leakage current source 210 is A1, J2 is larger than J1 and J2' is smaller than J1 'of the second leakage current source 220. The gate area A2 is determined.

By implementing the circuit as shown in FIG. 6 using the first and second leakage current sources 210 and 220 having A1 and A2 satisfying the above relationship, it is possible to find a MOS transistor that deviates from the thickness of a critical oxide layer.

FIG. 8 is a circuit diagram showing a first embodiment of the comparator shown in FIG. 6. Referring to FIG. 8, the comparator 230 includes two NMOS transistors N1 and N2, four PMOS transistors P1 to P4, and two inverters INV1 and INV2. The operation principle of the comparator 230 is the same as the comparator 130 described with reference to FIG. 3. The output signal of the comparator 230 may determine whether a semiconductor device (not shown) is normally manufactured.

FIG. 9 is a circuit diagram illustrating a second embodiment of the comparator shown in FIG. 6. Referring to FIG. 9, the comparator 230 is composed of two PMOS transistors P5 and P6. The operating principle of the comparator 230 is the same as described with reference to FIG. 4.

10 is a circuit diagram showing a second embodiment of the semiconductor inspection apparatus using the gate leakage current according to the present invention. The operating principle of the semiconductor inspection apparatus is the same as described with reference to FIG. 5.

III. Leakage Current Compensation System Using Semiconductor Inspection System

 11 is a circuit diagram showing an embodiment of a leakage current compensation system using a semiconductor inspection apparatus according to the present invention. Referring to FIG. 11, the output signal Output of the semiconductor test apparatus 100 is input to the leakage current compensator 300 through an inverter INV3. The leakage current compensator 300 includes first and second compensation circuits 310 and 320 to compensate for leakage current flowing through the NMOS logic circuit 400.

The NMOS logic circuit 400 includes at least one NMOS transistor. When the channel length of the NMOS transistor is abnormally manufactured, the NMOS logic circuit 400 malfunctions because a leakage current flows rapidly in the off mode. In this case, the semiconductor inspection apparatus 100 is required to inspect the leakage current flowing through the NMOS logic circuit 400, and the leakage current compensator 300 is provided to compensate for the leakage current flowing through the NMOS logic circuit 400. in need.

When the clock signal CLK is 'L', the PMOS transistor M4 is turned on and the NMOS transistor M5 is turned off. Thus, node A is in the 'H' state. When the clock signal CLK is changed to 'H', the PMOS transistor M4 is turned off and the NMOS transistor M5 is turned on. At this time, when the NMOS logic circuit 400 is turned off by the input signals IN1, IN2,..., And INn, the node A is maintained at the 'H' state. However, if the semiconductor fabrication process is abnormally progressed and the channel length of the NMOS transistors in the NMOS logic circuit 400 is made smaller than the critical channel length, the leakage current increases even in the off mode, and thus the node A may change to the 'L' state. There is this.

The semiconductor inspection apparatus 100 generates an output signal by detecting that the NMOS logic circuit 400 is abnormally manufactured and a leakage current flows in the off mode.

The leakage current compensator 300 prevents the node A from changing to 'L' undesirably. The first compensation circuit 310 is composed of one PMOS transistor M1. The first compensation circuit 310 is a circuit for compensating for a leakage current flowing through the NMOS logic circuit 400 when the semiconductor fabrication process is normally performed. However, if the leakage current rapidly increases due to an abnormal process, only the first compensation circuit 310 is insufficient, and thus a second compensation circuit 320 is additionally required.

If the channel length is normally manufactured, the normal signal 'L' is outputted to the output signal Output of the semiconductor inspection apparatus, and if it is abnormally manufactured, the abnormal signal 'H' is outputted. The signals are inverted when passing through the inverter INV3, and the inverted signals are input to the second compensation circuit 320. That is, 'H' is input to the second compensation circuit 320 when the channel length is normal, and 'L' is input when the channel length is abnormal.

When the semiconductor manufacturing process is normally performed and the channel length is normal, 'H' is input to the second compensation circuit 320 to turn off the PMOS transistor M2. Therefore, the second compensation circuit 320 does not work. However, when the semiconductor manufacturing process is abnormally progressed and the channel length is abnormal, the leakage current rapidly increases, and the semiconductor inspection apparatus 100 outputs an abnormal signal, and 'L' is input to the second compensation circuit 320. At this time, the PMOS transistor M2 is turned on and supplies an additional current to the node A according to the output value Out, thereby causing an unstable state or logic fail of the node A due to the leakage current of the NMOS logic circuit 400. ) Can be prevented.

FIG. 12 shows an embodiment of the leakage current compensation system shown in FIG. 11. Referring to FIG. 12, the structure and operation principle of the first and second compensation circuits 310 and 320 are the same as those of FIG. 11. In FIG. 12, when the clock signal CLK is 'H', when the ground voltage is applied to the input terminals IN1 to IN6 of the NMOS logic circuit 400 and all the NMOS transistors are in the off mode, the NMOS transistors are normally manufactured. If the leakage current is small, only the first compensation circuit 310 may prevent an unsafe state or logic failure of the node A. However, when abnormally manufactured and the leakage current rapidly increases, the second compensation circuit 320 operates to compensate for the loss due to the leakage current to prevent an unsafe state of the node A.

11 and 12 illustrate only the semiconductor inspection apparatus 100 using the channel leakage current as an embodiment of the leakage current compensation system, the same principle may be applied to the semiconductor inspection apparatus 200 using the gate leakage current. It is self-evident.

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

According to the semiconductor inspection apparatus using the channel leakage current according to the present invention, it is possible to easily detect the MOS transistor fabricated smaller than the critical channel length during the semiconductor process. According to the semiconductor inspection apparatus using the gate leakage current according to the present invention, it is possible to easily detect the MOS transistor fabricated less than the critical oxide thickness in the semiconductor process. In addition, according to the leakage current compensation system according to the present invention, it is possible to prevent the malfunction of the circuit due to the leakage current.

Claims (15)

A semiconductor inspection apparatus for inspecting a semiconductor device comprising at least one MOS transistor, the apparatus comprising: The semiconductor inspection device is manufactured in the same process as the semiconductor device; A first leakage current source configured to variably generate a first leakage current depending on whether the MOS transistors are normally manufactured; A second leakage current source configured to generate a second leakage current variably depending on whether the MOS transistors are normally manufactured; And And a comparator comparing the first and second leakage currents to determine whether the semiconductor device is normally manufactured. The method of claim 1, And the first leakage current is less than the second leakage current when the MOS transistors are normally manufactured, and the first leakage current is greater than the second leakage current when the MOS transistors are abnormally manufactured. The method of claim 1, And the first and second leakage current sources are MOS transistors. A semiconductor inspection apparatus for inspecting a semiconductor device comprising at least one MOS transistor, the apparatus comprising: The semiconductor inspection device is manufactured in the same process as the semiconductor device; In the off-mode operation, the first leakage currents (hereinafter, referred to as I1 and I1 ', respectively) at the critical channel length (hereinafter referred to as L1) and the channel length (hereinafter referred to as L1') smaller than L1 (hereinafter referred to as L1 ') respectively. A first MOS transistor designed to flow through the channel; In the off-mode operation, second leakage currents (hereinafter, referred to as I2 and I2 ') at channel lengths longer than L1 (hereinafter referred to as L2) and channel lengths smaller than ΔL2 (hereinafter referred to as L2') are referred to below. A second MOS transistor designed to flow through the channel; And Comparing the first and second leakage currents to determine whether the semiconductor device is manufactured normally, The first MOS transistor has a channel width W1 designed such that I1 is smaller than I2 and I1 'is larger than I2', and the second MOS transistor has a channel width designed such that I2 is larger than I1 and I2 'is smaller than I1'. (W2) having a semiconductor inspection device. The method of claim 4, wherein The comparator generates a normal signal when I2 is larger than I1 and generates an abnormal signal when I2 'is smaller than I1'. The method of claim 4, wherein And the first and second MOS transistors are NMOS transistors. The method of claim 4, wherein And said first and second MOS transistors are PMOS transistors. A semiconductor inspection apparatus for inspecting a semiconductor device comprising at least one MOS transistor, the apparatus comprising: The semiconductor inspection device is manufactured in the same process as the semiconductor device; The first leakage currents (hereinafter referred to as J1 and J1 ') respectively flow through the oxide film at a critical oxide thickness (hereinafter referred to as T1) and an oxide thickness (hereinafter referred to as T1') smaller than T1. A first MOS capacitor designed; At the oxide thickness larger than T1 (hereinafter referred to as T2) and at an oxide thickness smaller than ΔT2 (hereinafter referred to as T2 '), the second leakage currents (hereinafter referred to as J2 and J2') are respectively passed through the oxide film. A second MOS capacitor designed to flow; And Comparing the first and second leakage currents to determine whether the semiconductor device is manufactured normally, The first MOS capacitor has a gate area A1 designed such that J1 is smaller than J2 and J1 'is larger than J2', and the second MOS capacitor has a gate area designed such that J2 is larger than J1 and J2 'is smaller than J1'. A semiconductor inspection apparatus comprising (A2). The method of claim 8, The comparator generates a normal signal when J2 is larger than J1, and generates an abnormal signal when J2 'is smaller than J1'. The method of claim 8, And the first and second MOS capacitors are NMOS capacitors. The method of claim 8, And the first and second MOS capacitors are PMOS capacitors. In the leakage current compensation system: A semiconductor device comprising at least one MOS transistor; Comparing first and second leakage currents flowing through the first and second MOS transistors, including first and second MOS transistors manufactured in the same process as the MOS transistors, and as a result of the comparison of the semiconductor device. A semiconductor inspection device for determining whether the MOS transistors are normally manufactured; And And a leakage current compensator for compensating for a leakage current flowing through MOS transistors of the semiconductor device in response to an output signal of the semiconductor test device. The method of claim 12, In the off-mode operation, the semiconductor inspection apparatus may include first leakage currents (hereinafter, referred to as I1, respectively) at a critical channel length (hereinafter referred to as L1) and a channel length smaller than ΔL1 (hereinafter referred to as L1 ′). A first MOS transistor designed to flow through the channel; In the off-mode operation, second leakage currents (hereinafter, referred to as I2 and I2 ') at channel lengths longer than L1 (hereinafter referred to as L2) and channel lengths smaller than ΔL2 (hereinafter referred to as L2') are referred to below. A second MOS transistor designed to flow through the channel; And Comparing the first and second leakage currents to determine whether the semiconductor device is manufactured normally, The first MOS transistor has a channel width W1 designed such that I1 is smaller than I2 and I1 'is larger than I2', and the second MOS transistor has a channel width designed such that I2 is larger than I1 and I2 'is smaller than I1'. (W2), characterized in that the leakage current compensation system. The method of claim 12, The semiconductor inspection apparatus includes first leakage currents (hereinafter, referred to as J1 and J1 ', respectively) at a critical oxide thickness (hereinafter referred to as T1) and an oxide film thickness (hereinafter referred to as T1') smaller than T1. A first MOS capacitor designed to flow through the oxide film; At the oxide thickness larger than T1 (hereinafter referred to as T2) and at an oxide thickness smaller than ΔT2 (hereinafter referred to as T2 '), the second leakage currents (hereinafter referred to as J2 and J2') are respectively passed through the oxide film. A second MOS capacitor designed to flow; And Comparing the first and second leakage currents to determine whether the semiconductor device is manufactured normally, The first MOS capacitor has a gate area A1 designed such that J1 is smaller than J2 and J1 'is larger than J2', and the second MOS capacitor has a gate area designed such that J2 is larger than J1 and J2 'is smaller than J1'. A leakage current compensation system characterized by having (A2). The method of claim 12, The leakage current compensator is configured to supply a leakage current to the MOS transistors in response to an abnormal signal of the semiconductor test apparatus when the semiconductor device is abnormally manufactured and a leakage current occurs in the MOS transistors. Leakage current compensation system.

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