KR100618818B1 - Solid state image sensing device providing reset level correction for high brightness object and driving method thereof - Google Patents

Abstract

Disclosed are a solid-state imaging device and a driving method thereof for preventing the reduction of the reset level at high brightness. The solid-state imaging device, in each of the pixels arranged in a two-dimensional matrix form, generates an image signal detected by light from the optical element and converted into an electrical signal and output in the transmission period, and generates a reset signal and output in the reset period A pixel array; When the voltage level of the reset signal is checked and the voltage level becomes a high luminance state which is reduced below a certain level of the steady state, a reset corrected to the constant level voltage of the normal state in the reset period by the voltage distribution of internal transistors. A reset level correction circuit unit generating and outputting a signal; And an analog-digital converter configured to receive one of the reset signal or the corrected reset signal during the reset period, and convert an analog signal corresponding to a difference between the received signal and the video signal into a digital signal and output the digital signal. do.

Description

Solid state image sensing device providing reset level correction for high brightness object and driving method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a general CIS type solid-state imaging device.

2 is a block diagram showing a CIS type solid-state imaging device according to an embodiment of the present invention.

3 is a circuit diagram specifically illustrating the solid-state imaging device of FIG. 2.

4 is a timing diagram for describing an operation of the solid-state imaging device of FIG. 3.

5 is an operation simulation waveform diagram of the solid-state imaging device of FIG. 3.

6 is a graph summarizing simulation results of the solid-state imaging device of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image sensing device, and more particularly to a CMOS image sensor (CIS) type solid state imaging device.

The CIS-type solid-state imaging device is mounted on a mobile phone camera, a digital still camera, or the like, and captures an image developed in a field of view, converts the image into an electrical signal, and transmits it to a digital signal processor. The digital signal processing unit processes color image data R, G, and B output from the solid state image pickup device to drive a display device such as a liquid crystal display (LCD).

1 is a block diagram showing a general CIS type solid-state imaging device. Referring to FIG. 1, a general CIS type solid-state imaging device includes a pixel array 110 and an analog-digital converter (ADC) 120. In general, in the case of a color solid-state imaging device, a color filter is provided to receive only light of a specific color on each pixel, and at least three kinds of color filters are disposed to form a color signal. The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern. At this time, G (green), which is closely related to the luminance signal, is disposed in every row, and R (red) color and B (blue) color are alternately arranged in each row to increase the luminance resolution. Digital still cameras, etc. are applied to a CIS array of many million pixels or more in order to increase the resolution.

In the CIS type solid-state imaging device having the pixel structure as described above, the pixel array 110 detects light using a photodiode and converts the light into an electrical signal to generate an image signal. The image signal output from the pixel array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 120 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal.

In the general CIS type solid-state imaging device as shown in FIG. 1, when converting an image signal sensed by an optical device into a digital signal by the analog-digital converter 120, a correlated double sampling (CDS) method is used. Such a driving method is well described in the US patent, "USP5,982,318", or "USP6,067,113". In the analog-to-digital conversion of the CDS method, after receiving the reset signal from the pixel array 110, it is divided into two steps of receiving the image signal sensed by the optical device and converting it into a digital signal. Each time the optical device detects a new light at a predetermined cycle, the pixel array 110 is reset to the analog-digital converter 120 before the optical device outputs the newly detected image signal to the analog-digital converter 120. Output the signal. The analog-to-digital converter 120 receives a reset signal and resets it, and then converts an image signal received from an optical device into a digital signal and outputs the digital signal. The digital signal converted as described above is output to the digital signal processor and subjected to a predetermined interpolation process. In addition, the subsequent digital signal processor generates drive signals suitable for the corresponding resolution of the display device such as an LCD, and drives the display device.

However, when imaging an object having a high brightness, such as the sun, a charge (electron) overflow occurs in the floating diffusion region in the optical device provided in the pixel array 110, and the reset level is reduced. Accordingly, the analog-to-digital converter 120 receives a reset signal having a voltage lower than a normal reset level during a reset period when capturing a high-luminance object, and thus, converts an image signal input from an optical device into a digital signal at a maximum high brightness. It does not generate the corresponding "full saturation code". Accordingly, the display device displays an image of the high brightness object darker than the actual brightness. That is, the analog-to-digital converter 120 compares the reset signal with the video signal input from the optical device, and generates a digital code proportional to the amount of light depending on how large the video signal is than the reset signal. In particular, when imaging an object having a brightness near the maximum high luminance, when the level of the reset signal decreases, there is a problem that a normal digital code having a gray scale value proportional to the amount of light cannot be generated.

Accordingly, an object of the present invention is to provide a solid-state imaging device and a driving method thereof capable of displaying the brightness of a real object by preventing a reset level reduction and maintaining a constant level when imaging a high brightness object.

The solid-state imaging device according to the present invention for achieving the above technical problem, in each of the pixels arranged in a two-dimensional matrix form, generates an image signal detected by the light from the optical device converted into an electrical signal and output in the transmission period A pixel array for generating a reset signal and outputting the reset signal in a reset period; When the voltage level of the reset signal is checked and the voltage level becomes a high luminance state which is reduced below a certain level of the steady state, a reset corrected to the constant level voltage of the normal state in the reset period by the voltage distribution of internal transistors. A reset level correction circuit unit generating and outputting a signal; And an analog-digital converter configured to receive one of the reset signal or the corrected reset signal during the reset period, and convert an analog signal corresponding to a difference between the received signal and the video signal into a digital signal and output the digital signal. Characterized in that.

The reset level correction circuit unit may generate the corrected reset signal by the internal transistors having the same connection structure and size as that of the transistors used in generating the reset signal. The internal transistors may include: a reset transistor configured to transfer power under control of a reset gate signal; A selection transistor configured to transfer the power under the control of a selection signal; And a source follower transistor for outputting a reset signal corrected using the power supplied from the reset transistor and the selection transistor.

The reset level correction circuit unit may not output the corrected reset signal when the determination transistor under the control of the reset signal is activated in a normal state other than the high brightness state. The reset level correction circuit section is configured to receive a control of an output signal of another source follower transistor that outputs the corrected reset signal in the transmission period when the determination transistor under the control of the reset signal is not activated in the high luminance state. The control transistor is also inactive, characterized in that for outputting the corrected reset signal. The control transistor adjusts a clamp voltage indicating a start voltage level of an image signal to which the corrected reset signal is output as the control transistor changes from a normal state to a high luminance state by a voltage applied to the gate. The reset transistor may be an NMOSFET, a depletion NMOSFET, or a PMOSFET.

In accordance with another aspect of the present invention, there is provided a method of driving a solid-state imaging device, which generates and transmits an image signal that is converted into an electrical signal by detecting light from an optical device in each of pixels arranged in a two-dimensional matrix form. Outputting in a period, generating a reset signal and outputting the reset signal; When the voltage level of the reset signal is checked and the voltage level becomes a high luminance state which is reduced below a certain level of the steady state, a reset corrected to the constant level voltage of the normal state in the reset period by the voltage distribution of internal transistors. Generating and outputting a signal; And receiving one of the reset signal or the corrected reset signal in the reset period, and converting an analog signal corresponding to a difference between the received signal and the video signal into a digital signal and outputting the digital signal. It is done. The generating of the corrected reset signal may include generating the corrected reset signal by the internal transistors having the same structure and size as that of the transistors used in generating the reset signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram showing a CIS type solid-state imaging device according to an embodiment of the present invention. 2, a CIS type solid-state imaging device according to an embodiment of the present invention includes a pixel array 210, a reset level correction circuit unit 220, and an analog-digital device. An analog-digital conversion unit (ADC) 230 is provided.

The pixel array 210 generates an image signal VFD of each pixel arranged in a two-dimensional matrix form by detecting light from a photodiode (PD) and converting the light into an electrical signal. (VFD) Output during the delivery period. In addition, the pixel array 210 generates a reset signal VRST and outputs the reset signal VRST in the reset period. The operation of the pixel array 210 is described in detail in the description of FIG. 3.

As in the conventional case, the pixel array 210 is provided with a color filter having a Bayer pattern on each pixel. That is, the three-color (R, G, B) video signal (VFD) pattern output from the pixel array 210 may be R (red), G (green) two color signal patterns in one row, and in another row. G (green) and B (blue) two color signal patterns, and the video signal (VFD) of this pattern has a pattern that is repeatedly output every two rows. The pixel array 210 may be applied to a mobile phone camera, a digital still camera, or the like to have many pixels of 1 million pixels or more in order to increase the resolution.

The reset level correction circuit unit 220 includes a reset level correction circuit for each column, and corrects the reset signal VRST generated for each pixel in the same column on the pixel array 210. The reset level correction circuit unit 220 checks the voltage level of the reset signal VRST, and generates and outputs a corrected reset signal when the voltage level decreases to a high brightness level below a predetermined level. The operation of the reset level correction circuit 220 is described in detail in the description of FIG. 3.

The analog-to-digital converter 230 includes an analog-to-digital converter on a column-by-column basis, receives the analog image signal VFD output from the pixel array 210, and applies the analog image signal VFD to a voltage level of the analog image signal VFD. As a result, the signal is converted into a digital signal representing different gray scale values. In particular, the analog-to-digital converter 230 uses a correlated double sampling (CDS) scheme as is well known. In this driving scheme, the analog-digital converter 230 receives the reset signal VRST generated from the pixels on the pixel array 210 in the reset period, and transmits the image signal VFD of the optical device PD. The image signal VFD sensed by the optical device PD present in the pixels in the same column is received during the period. Accordingly, the analog-to-digital converter 230 converts an analog signal corresponding to the difference between the reset signal VRST and the image signal VFD into a digital signal representing different gray scale values according to the difference.

At this time, when the image of the object having a high brightness, such as the sun, the voltage level of the reset signal (VRST) is reduced, the analog-to-digital converter 230 is a normal indicating a gray value corresponding to the actual brightness of the object It does not generate a digital signal. As described above, the voltage level of the reset signal VRST is decreased in high luminance, as described above, and the charge from the optical device PD included in the pixel array 210 to the floating diffusion region ( E) overflow occurs. Accordingly, the present invention uses the corrected reset signal generated by the reset level correction circuit 220 to correct the decrease in the voltage level of the reset signal VRST at high brightness. That is, the reset level correction circuit unit 220 checks the voltage level of the reset signal VRST, and generates and outputs a corrected reset signal when the voltage level decreases to a high brightness level below a predetermined level. The corrected reset signal is input to the analog-digital converter 230 in place of the pre-correction reset signal VRST. Accordingly, the analog-to-digital converter 230 receives one of the reset signal VRST or the corrected reset signal during a reset period, and receives the optical signal during the image signal VFD transmission period of the optical device PD. The image signal VFD detected by the device PD is input. The analog-to-digital converter 230 may generate an analog signal corresponding to a difference between the image signal VFD with respect to either the input reset signal VRST or the corrected reset signal according to the difference. Convert to a digital signal representing a value.

When the image signal VFD transmitted from the optical device PD is converted into a digital signal having a predetermined gray scale value, the converted digital signal is subjected to predetermined interpolation in a subsequent signal processor. Further, the subsequent signal processor drives the display apparatus by signal processing the color image data R, G, and B to generate driving signals suitable for the corresponding resolution of the display apparatus such as an LCD.

3 is a circuit diagram specifically illustrating the solid-state imaging device of FIG. 2. 4 is a timing diagram for describing an operation of the solid-state imaging device of FIG. 3. Hereinafter, the timing diagram of FIG. 4 is used to explain the operation of the circuit of FIG. 3.

Referring to FIG. 3, one pixel constituting the pixel array 210 includes a photodiode (PD), a transfer transistor M2, a first reset transistor M1, a first select transistor M3, and a first source. A follower transistor M4 and a first level adjustment transistor M9 are provided. One reset level correction circuit in a column unit of the reset level correction circuit unit 220 includes a second reset transistor M5, a second selection transistor M3 ′, a second source follower transistor M4 ′, and a third selection. A transistor M3 ", a third source follower transistor M4 ", a determination transistor M6, a control transistor M7, and a second level adjustment transistor M8 are provided. The transistors constituting the pixel array 210 and the reset level correction circuit 220 are formed of n-type metal-oxide-semiconductor field effect transistors (NMOSFETs). In particular, the first reset transistor M1 and the second reset transistor M5 are preferably depletion NMOSFETs or PMOSFETs in order to prevent voltage loss by a threshold voltage. In addition, even if the positions of the first selection transistor M3 and the first source follower transistor M4 are interchanged with each other, the same function is performed. Similarly, the positions of the second select transistor M3 'and the second source follower transistor M4' may be interchanged, and the positions of the third select transistor M3 "and the third source follower transistor M4" may be changed. Can also be interchanged.

The operation of the circuit of FIG. 3 can be described by dividing the operation in the normal state and the high luminance state, not in the high luminance state. First, in the normal state, when the row selection signal VSEL on the pixel array 210 is activated from the first logic state (logical low state) to the second logic state (logical high state) and the corresponding row is selected, the pixel array is selected. At 210, the reset gate signal VRG is activated to transfer the power supply voltage VDD to the source terminal of the first reset transistor M1. The power supply voltage VDD transferred to the source terminal of the first reset transistor M1 turns on the first source follower transistor M4 and thus, the first select transistor M3 and the first source follower transistor M4 that are in an on state. And the reset signal VRST having a predetermined level of voltage (for example, 1.5 volts) is output to the source terminal of the first source follower transistor M4 by the voltage distribution of the first level adjusting transistor M9. It is assumed that a predetermined bias voltage BIAS1 required for the operation of this circuit is applied to the gate of the first level adjustment transistor M9.

In the normal state, in the reset level correction circuit unit 220, the reset gate enable signal VENRG is activated to transmit the power supply voltage VDD to the source terminal of the second reset transistor M5. At this time, since the reset signal VRST of the predetermined level (for example, 1.5 volts) output to the source terminal of the first source follower transistor M4 activates / turns on the determination transistor M6, the source terminal of the second reset transistor M5 is Connected to ground, thereby turning off the third source follower transistor M4 ". Assume that another predetermined bias voltage BIAS2 is applied to the gate of the second level adjust transistor M8 for operation of this circuit. Therefore, when the clamp control signal VCKMP is activated, the analog-to-digital converter 230 outputs the predetermined level output to the source terminal of the M4 through the switch SW that is simultaneously activated by the switch control signal VSW. For example, the reset signal VRST of 1.5 volts is input, and the analog-digital converting unit 230 is activated through the switch SW which is simultaneously activated when the transfer gate signal VTG is activated. spirit It receives the signal (VFD).

On the other hand, in the high luminance state, the optical element described above when the row selection signal VSEL on the pixel array 210 is activated and the corresponding row is selected, and then the reset gate signal VRG is activated in the pixel array 210. Due to the occurrence of charge (electron) overflow in the floating diffusion region of the PD, the power supply voltage VDD cannot be delivered to the source terminal of the first reset transistor M1, and a voltage smaller than the power supply voltage VDD is prevented. Delivered. Accordingly, the voltage of the predetermined level in the steady state (for example, 1.5 volts) is obtained by voltage distribution of the first selection transistor M3, the first source follower transistor M4, and the first level adjustment transistor M9 in the active / on state. The smaller pre-correction reset signal VRST is output to the source terminal of the first source follower transistor M4.

In the high brightness state, the reset level enable circuit 220 activates the reset gate enable signal VENRG and transmits the power supply voltage VDD to the source terminal of the second reset transistor M5. At this time, the pre-correction reset signal VRST output to the source terminal of the first source follower transistor M4 does not have sufficient voltage to activate / turn on the determination transistor M6, so the source terminal of the second reset transistor M5 is grounded. It is not connected with. At this time, the voltage of the predetermined level in the steady state (for example, 1.5 volts) is divided by the voltage distribution of the third selection transistor M3 ", the third source follower transistor M4 ", and the first level adjustment transistor M9 which are in the on state. Is reset to the source terminal of the third source follower transistor M4 ". Therefore, when the clamp control signal VCKMP is activated, the switch SW that is activated by the switch control signal VSW is simultaneously activated. The analog-to-digital converter 230 receives a corrected reset signal output to the source terminal of the third source follower transistor M4 ″. When the corrected reset signal is output to the source terminal of the third source follower transistor M4 ", the source terminal of the control transistor M7 is connected to the source transistor of the second source follower transistor M4 'in order to prevent the determination transistor M6 from being active / on. The corrected reset signal is stably outputted to the source terminal of M4 " by the control transistor M7 not being activated / on. In addition, the analog-digital converter 230 receives the image signal VFD through the switch SW which is simultaneously activated when the transfer gate signal VTG is activated.

For the stable operation of such a circuit, the connection structure of the transistors M5, M3 ", M4" used to generate the corrected reset signal in the reset level correction circuit unit 220 is the pre-correction reset signal VRST. It is preferable to have the same connection structure as the structure of the transistors M1, M3, M4 used for the generation of. The size of each transistor used at this time is also preferably the same.

5 is an operation simulation waveform diagram of the solid-state imaging device of FIG. 3. 6 is a graph summarizing simulation results of the solid-state imaging device of FIG. 3.

5 and 6, as the magnitude of the voltage of the image signal VFD decreases due to the high brightness, the voltage magnitude of the reset signal VRST decreases, and the magnitude of the voltage of the image signal VFD is 2.4 V or less. In this case, the reset level correction circuit VRST is restored to the reset signal VRST voltage level (for example, 1.5 volts) in the normal state by the reset level correction circuit unit 220, and is maintained at the constant level. As the luminance becomes high, the starting voltage level of the image signal VFD to which the corrected reset signal is output, that is, the clamp voltage VCLAMP as shown in FIG. 6 may be adjusted according to the gate voltage of the control transistor M7. have.

As described above, the solid-state imaging device according to an embodiment of the present invention can restore the reduced reset level to a reset level in a normal state by a reset level correction circuit to maintain a constant level when imaging a high brightness object. have. Therefore, the analog-digital converter 230 may generate a normal digital code proportional to the brightness of the real object, and thus a display device such as an LCD may display the brightness of the real object.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the solid-state imaging device according to the present invention generates a "full saturation code" even when imaging an object having brightness near the maximum high brightness, so that the brightness of the actual object is displayed on a display device such as an LCD. There is an effect to improve.

Claims (13)

A pixel array in each of the pixels arranged in a two-dimensional matrix form, generating an image signal which is detected by light from an optical element and converted into an electrical signal, and outputting the image signal in a transmission period, and generating and outputting a reset signal in a reset period; When the voltage level of the reset signal is checked and the voltage level becomes a high luminance state which is reduced below a certain level of the steady state, a reset corrected to the constant level voltage of the normal state in the reset period by the voltage distribution of internal transistors. A reset level correction circuit unit generating and outputting a signal; And An analog-digital converter configured to receive one of the reset signal or the corrected reset signal during the reset period, and convert an analog signal corresponding to a difference between the input signal and the video signal into a digital signal and output the digital signal; A solid-state imaging device, characterized in that. The method of claim 1, wherein the reset level correction circuit unit, And generating the corrected reset signal by the internal transistors having the same connection structure and size as that of the transistors used in generating the reset signal. The method of claim 2, wherein the internal transistors, A reset transistor configured to transfer power under the control of the reset gate signal; A selection transistor configured to transfer the power under the control of a selection signal; And And a source follower transistor configured to output a reset signal corrected using the power supplied from the reset transistor and the selection transistor. The method of claim 3, wherein the reset level correction circuit unit, And the corrected reset signal is not output when the determination transistor under the control of the reset signal is activated in a normal state other than the high brightness state. The method of claim 3, wherein the reset level correction circuit unit, In the high luminance state, the determination transistor under the control of the reset signal is not activated, and the control transistor under the control of the output signal of another source follower transistor outputting the corrected reset signal in the transmission period is also inactive. And outputting the corrected reset signal. The method of claim 5, wherein the control transistor, And a clamp voltage indicating a start voltage level of an image signal to which the corrected reset signal is output according to a high luminance state from a normal state by a voltage applied to the gate. The method of claim 3, wherein the reset transistor, A solid-state imaging device, characterized in that the NMOSFET. The method of claim 3, wherein the reset transistor, It is a depletion type NMOSFET, The solid-state image sensor characterized by the above-mentioned. The method of claim 3, wherein the reset transistor, It is a PMOSFET, The solid-state image sensor characterized by the above-mentioned. Generating pixels in each of the pixels arranged in the two-dimensional matrix form and converting them into electrical signals by sensing light from an optical device, and outputting them in a transmission period, and generating and outputting a reset signal in a reset period; When the voltage level of the reset signal is checked and the voltage level becomes a high luminance state which is reduced below a certain level of the steady state, a reset corrected to the constant level voltage of the normal state in the reset period by the voltage distribution of internal transistors. Generating and outputting a signal; And And receiving one of the reset signal or the corrected reset signal in the reset period, and converting an analog signal corresponding to a difference between the received signal and the video signal into a digital signal and outputting the digital signal. Solid-state image sensor drive method. The method of claim 10, wherein the generating of the corrected reset signal, And generating the corrected reset signal by the internal transistors having the same connection structure and size as that of the transistors used in the generation of the reset signal. The method of claim 11, wherein the generating of the corrected reset signal, And the corrected reset signal is not output when the determination transistor under the control of the reset signal is activated in a normal state other than the high brightness state. The method of claim 11, wherein the generating of the corrected reset signal, In the high luminance state, the determination transistor under the control of the reset signal is not activated, and the control transistor under the control of the output signal of the predetermined source follower transistor that transfers the corrected reset signal in the transmission period is also inactive. And outputting the corrected reset signal.

Images