KR100618540B1 - Manufacturing method for semiconductor chip package which is encapsulated by lid - Google Patents

Manufacturing method for semiconductor chip package which is encapsulated by lid Download PDF

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KR100618540B1
KR100618540B1 KR1019990022631A KR19990022631A KR100618540B1 KR 100618540 B1 KR100618540 B1 KR 100618540B1 KR 1019990022631 A KR1019990022631 A KR 1019990022631A KR 19990022631 A KR19990022631 A KR 19990022631A KR 100618540 B1 KR100618540 B1 KR 100618540B1
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semiconductor chip
package
metal cover
cavity
package body
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KR1019990022631A
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KR20010002703A (en
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이해구
송근호
오선주
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 캐버티가 형성된 패키지 몸체에 반도체 칩을 실장하여 금속덮개로 봉지하는 금속덮개 봉지형 반도체 칩 패키지의 제조 방법으로서, ⒜200-340℃이하 경화용 실버 글래스를 도포하고 반도체 칩을 패키지 몸체의 캐버티에 위치하도록 부착하는 칩 실장 단계, ⒝ 실버 글래스를 경화시켜 반도체 칩을 고정시키는 단계, ⒞ 반도체 칩과 패키지 몸체의 캐버티에 노출된 회로패턴을 도전성 금속선으로 연결시키는 와이어 본딩 단계, ⒟ 패키지 몸체와 미리 솔더 도금층이 형성되어 있는 금속덮개를 부착하고 솔더의 용융되는 분위기 온도를 인가하여 내부공간을 밀폐시키는 금속덮개 봉합 단계를 포함하는 것을 특징으로 한다. 이에 따르면, 수소 클리닝 공정을 생략할 수 있기 때문에, 폭발의 위험성이 있는 수소 가스를 사용하지 않아도 되어 안전성 측면에서 유리한 생산라인 환경을 구축할 수 있으며, 하나의 공정을 생략할 수 있어 생산성 측면에서 유리한 이점이 있다.The present invention is a method of manufacturing a metal-cover encapsulated semiconductor chip package that mounts a semiconductor chip on a package body formed with a cavity and encapsulates it with a metal cover. A chip mounting step of attaching to the cavity of the cavity, ⒝ hardening the silver glass to fix the semiconductor chip, 와이어 a wire bonding step of connecting the semiconductor chip and the circuit pattern exposed to the cavity of the package body with a conductive metal wire, ⒟ And a metal cover sealing step of attaching the package body and the metal cover in which the solder plating layer is formed in advance, and sealing the internal space by applying an atmosphere temperature at which the solder is melted. According to this, since the hydrogen cleaning process can be omitted, it is possible to construct a production line environment which is advantageous in terms of safety by eliminating the use of hydrogen gas, which may cause explosion, and one process can be omitted, which is advantageous in terms of productivity. There is an advantage.

반도체 칩 패키지, 세라믹 패키지, 금속덮개, 수소 클리닝, 실버 글래스Semiconductor Chip Package, Ceramic Package, Metal Cover, Hydrogen Cleaning, Silver Glass

Description

금속덮개 봉지형 반도체 칩 패키지 제조 방법{Manufacturing method for semiconductor chip package which is encapsulated by lid}Manufacturing method for semiconductor chip package which is encapsulated by lid}

도 1은 금속덮개 봉지형 반도체 칩 패키지의 일 예를 나타낸 단면도.1 is a cross-sectional view showing an example of a metal cover encapsulated semiconductor chip package.

도 2는 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 공정의 일부를 나타낸 공정도.Figure 2 is a process diagram showing a part of the metal lid encapsulated semiconductor chip package manufacturing process according to the present invention.

도 3은 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 공정별 상태도.Figure 3 is a state diagram for each metal cover encapsulated semiconductor chip package manufacturing process according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체 칩 패키지 20: 반도체 칩10: semiconductor chip package 20: semiconductor chip

25: 실버 글래스(silver glass) 30: 패키지 몸체25: silver glass 30: package body

31: 캐버티(cavity) 33: 회로패턴31: cavity 33: circuit pattern

40: 외부접속단자 50: 금속덮개40: external connection terminal 50: metal cover

55: 솔더(solder) 60: 도전성 금속선55: solder 60: conductive metal wire

70: 내부공간70: interior space

본 발명은 반도체 칩 패키지 제조 방법에 관한 것으로서, 더욱 상세하게는 공정의 진행에 따라 발생되는 패키지 내부공간의 수분 발생량을 감소시키기 위한 공정을 포함하는 금속덮개(metal lid) 봉지형 반도체 칩 패키지 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor chip package, and more particularly, to a method of manufacturing a metal lid encapsulated semiconductor chip package including a process for reducing the amount of moisture generated in a package internal space generated as the process proceeds. It is about.

도 1은 금속덮개 봉지형 반도체 칩 패키지의 일 예를 나타낸 단면도이다.1 is a cross-sectional view illustrating an example of a metal lid encapsulated semiconductor chip package.

도 1을 참조하면, 도시된 금속덮개 봉지형 반도체 칩 패키지(10)는 반도체 칩(20)이 패키지 몸체(30)의 캐버티(cavity;31)에 위치하도록 실장되어 있고, 금속덮개(50)가 캐버티(31)에 의해 형성된 내부공간(70)을 봉지하도록 패키지 몸체(30)에 솔더(55)로 부착되어 있으며, 반도체 칩(20)과 그 전기적인 연결부위가 외부환경으로부터의 보호되는 구조를 갖고 있다. 반도체 칩(20)은 패키지 몸체(30) 안쪽 바닥면에 고온 실버 글래스(silver glass;25)로 부착된다.Referring to FIG. 1, the illustrated metal encapsulated semiconductor chip package 10 is mounted such that the semiconductor chip 20 is positioned in a cavity 31 of the package body 30 and the metal cover 50. Is attached to the package body 30 with solder 55 so as to seal the internal space 70 formed by the cavity 31, and the semiconductor chip 20 and its electrical connection are protected from the external environment. It has a structure. The semiconductor chip 20 is attached to the bottom surface of the package body 30 by high temperature silver glass 25.

그리고, 이 반도체 칩 패키지(20)는 패키지 몸체(30)의 안쪽 바닥면에 금 도금층으로 형성된 복수의 회로패턴(33)과 반도체 칩(20)이 도전성 금속선(60)으로 와이어 본딩(wire bonding)되어 접속되고 그 회로패턴(33)과 패키지 몸체(30)의 외부로 노출되어 있는 외부접속단자(40)가 연결되어 전기적인 연결을 이룬다.In addition, the semiconductor chip package 20 includes a plurality of circuit patterns 33 formed of a gold plating layer on the inner bottom surface of the package body 30, and the semiconductor chip 20 is wire bonded to the conductive metal wire 60. And connected to the circuit pattern 33 and the external connection terminal 40 exposed to the outside of the package body 30 is connected to form an electrical connection.

이와 같은 구조의 금속덮개 봉지형 반도체 칩 패키지는 웨이퍼 소잉(sawing) 공정, 칩 실장(die attach) 공정, 경화(cure) 공정, 와이어 본딩(wire bonding) 공정, 수소 클리닝(H2 cleaning) 공정, 금속덮개 봉합(sealing) 공정, 누출 테스트 공정, 및 외관 검사 공정 등을 거쳐 제조된다.The metal cover sealed type semiconductor chip package of the same construction wafer sawing (sawing) process, a chip mounting (die attach) process, hardening (cure) step, wire bonding (wire bonding) process, hydrogen cleaning (H 2 cleaning) step, It is manufactured through a metal cover sealing process, a leak test process, and an appearance inspection process.

여기서, 수소 클리닝 공정은 반도체 칩을 패키지 몸체에 실장한 후에 그 반 도체 칩을 외부환경으로부터 보호하기 위해 실시되는 금속덮개 봉합공정을 진행하기 전에 패키지 내부의 수분을 감소시키기 위해 필요한 공정으로서, 반도체 칩이 실장된 패키지 몸체를 수소 반응로에 통과시켜 내부 공간과 봉지 영역의 금 도금층 위에 존재하는 니켈 산화물과 수소를 반응시킴으로써 산소가 환원되도록 하여 이후에 발생되는 패키지 내부 공간의 수분의 양을 감소시키게 된다.Here, the hydrogen cleaning process is a process required to reduce the moisture in the package after mounting the semiconductor chip on the package body and before performing the metal cover sealing process performed to protect the semiconductor chip from the external environment. The package body is passed through a hydrogen reactor to react oxygen with nickel oxide present on the gold plating layer of the inner space and the encapsulation area so that oxygen is reduced, thereby reducing the amount of water in the package inner space. .

금속덮개 봉지형 반도체 칩 패키지의 경우에 있어서 패키지 내부 공간에 잔류되는 수분은 부식(corrosion)과 산화, 이온의 미그레이션(ionic migration)에 의한 전기적인 누설, 전기의 미그레이션(electro migration) 등과 같은 문제를 일으켜 패키지의 장기적인 신뢰성을 저하시키기 때문에 수소 클리닝 공정은 패키지 신뢰성의 확보를 위하여 필수적인 공정이 아닐 수 없다. 보통, 신뢰성을 확보할 수 있는 내부 수분 함유량은 약 5000ppmv이하가 되도록 하고 있다.In the case of a metal encapsulated semiconductor chip package, the moisture remaining in the interior space of the package may be corroded, oxidized, electrical leakage due to ionic migration, and electricity migration. Hydrogen cleaning is indispensable for securing package reliability because it causes problems and degrades long-term reliability of the package. Usually, the internal moisture content which can ensure reliability is about 5000 ppmv or less.

그러나, 이와 같이 종래의 반도체 칩 패키지 제조 공정의 수소 클리닝 공정은 수소를 사용하기 때문에, 수소 가스의 누설에 대한 위험성과 반응로 자체가 차지하는 공간의 확보 문제, 그리고 장시간의 클리닝 타임(cleaning time)에 의한 작업이 완료되는 제품의 단위 시간당 개수(unit per hour)의 저하 등과 같은 문제점을 가지고 있다.However, since the hydrogen cleaning process of the conventional semiconductor chip package manufacturing process uses hydrogen, there is a risk of leakage of hydrogen gas, a problem of securing space occupied by the reactor itself, and a long cleaning time. It has a problem such as a decrease in the unit per hour of the product is completed by the work.

만일, 금속덮개로 봉지되는 패키지 몸체의 내부 공간에 잔류하는 수분의 양을 수소 클리닝 공정을 실시하지 않고 감소시킬 수 있는 방법이 있다면 상기와 같은 문제점들의 발생은 없을 것이다.If there is a method of reducing the amount of moisture remaining in the inner space of the package body encapsulated with the metal cover without performing the hydrogen cleaning process, the above problems will not occur.

본 발명의 목적은 수소 클리닝 공정을 진행하지 않고 패키지 몸체를 금속덮개로 봉지시킨 후에 패키지 내부 공간에 잔류하는 수분의 양을 감소시키는 금속덮개 봉지형 반도체 칩 패키지 제조 방법을 제공하는 데에 있다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a metal lid-encapsulated semiconductor chip package which reduces the amount of water remaining in the package interior space after encapsulating the package body with a metal lid without performing a hydrogen cleaning process.

이와 같은 목적을 달성하기 위한 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 방법은, 캐버티가 형성된 패키지 몸체에 반도체 칩을 실장하여 금속덮개로 봉지하는 금속덮개 봉지형 반도체 칩 패키지의 제조 방법으로서, ⒜ 200-340℃ 경화용 실버 글래스를 도포하고 반도체 칩을 패키지 몸체의 캐버티에 위치하도록 부착하는 칩 실장 단계, ⒝ 실버 글래스를 경화시켜 반도체 칩을 고정시키는 단계, ⒞ 반도체 칩과 패키지 몸체의 캐버티에 노출된 회로패턴을 도전성 금속선으로 연결시키는 와이어 본딩 단계, ⒟ 패키지 몸체와 미리 솔더 도금층이 형성되어 있는 금속덮개를 부착하고 솔더의 용융되는 분위기 온도를 인가하여 내부공간을 밀폐시키는 금속덮개 봉합 단계를 포함하는 것을 특징으로 한다.Metal cover encapsulated semiconductor chip package manufacturing method according to the present invention for achieving the above object is a method of manufacturing a metal cover encapsulated semiconductor chip package to mount a semiconductor chip in a package body formed with a cavity and sealed with a metal cover. A chip mounting step of applying silver glass for curing at 200-340 ° C. and attaching the semiconductor chip to the cavity of the package body, and fixing the semiconductor chip by hardening the silver glass, of the semiconductor chip and the package body. A wire bonding step of connecting the circuit pattern exposed to the cavity with a conductive metal wire, ⒟ Attaching the package body and the metal cover in which the solder plating layer is formed in advance and sealing the inner cover by applying the atmosphere temperature at which the solder is melted Characterized in that it comprises a step.

바람직하게는 금속덮개 봉합 단계 전에 금속덮개를 약 200℃이하에서 굽는 금속덮개 베이킹(baking) 단계를 진공중에서 실시하여 금속덮개의 솔더 도금층에서 수분이나 수소를 환원시켜 수분 발생 요인을 제거한다.Preferably, the metal lid baking step of baking the metal lid at about 200 ° C. or lower before the metal lid sealing step is performed in vacuum to reduce moisture or hydrogen in the solder plating layer of the metal lid.

이하 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 방법을 좀 더 상세하게 설명하기로 한다.Hereinafter, a method of manufacturing a metal lid encapsulated semiconductor chip package according to the present invention will be described in more detail.

도 2는 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 공정도이고,2 is a manufacturing process diagram of a metal lid encapsulated semiconductor chip package according to the present invention,

도 3a내지 3c는 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지 제조 공 정별 상태도이다.Figure 3a to 3c is a state diagram for each metal cover encapsulated semiconductor chip package manufacturing process according to the present invention.

도 2와 도 3a를 참조하면, 먼저 세라믹 재질로서 캐버티(31)가 형성되어 있는 패키지 몸체(30)에 반도체 칩(20)을 실장하는 칩 실장 단계(1)를 진행한다. 패키지 몸체(30)에 형성되어 있는 캐버티(31)에 의해 패키지 몸체(30) 상면으로부터 소정의 깊이에 형성되는 바닥면에 200-340℃의 경화온도를 갖는 실버 글래스(25)를 도포하고 반도체 칩(20)을 부착시킨다.Referring to FIGS. 2 and 3A, a chip mounting step 1 of mounting a semiconductor chip 20 on a package body 30 in which a cavity 31 is formed as a ceramic material is performed. The silver glass 25 having a curing temperature of 200-340 ° C. is applied to the bottom surface formed at a predetermined depth from the top surface of the package body 30 by the cavity 31 formed in the package body 30, and the semiconductor The chip 20 is attached.

다음으로 반도체 칩(20)을 고정시키기 위한 경화 단계(2)를 진행한다. 반도체 칩(20)을 부착시키기 위해 사용되는 실버 글래스는 종래에 사용되던 최고 360℃의 경화온도를 갖는 실버 글래스가 아닌 200-340℃의 경화온도를 갖는 실버 글래스(25)를 사용하기 때문에 반도체 칩(20)의 부착에 필요한 분위기 온도는 340℃이하로 낮아진다.Next, a curing step 2 for fixing the semiconductor chip 20 is performed. The silver glass used for attaching the semiconductor chip 20 uses a silver glass 25 having a curing temperature of 200-340 ° C. rather than a silver glass having a curing temperature of up to 360 ° C., which is conventionally used. The ambient temperature required for the attachment of (20) is lowered to 340 ° C or lower.

도 2와 도 3b를 참조하면, 반도체 칩(20)의 부착이 완료되면 반도체 칩(20)과 패키지 몸체(30)의 회로패턴(33)이 전기적으로 연결되도록 도전성 금속선(60)으로 와이어 본딩하는 단계(3)를 진행한다. 와이어 본딩에 의하여 반도체 칩(20)과 외부 접속단자(40)가 전기적으로 연결된다.2 and 3B, when the attachment of the semiconductor chip 20 is completed, wire bonding is performed with the conductive metal wire 60 to electrically connect the semiconductor chip 20 and the circuit pattern 33 of the package body 30. Proceed to step (3). The semiconductor chip 20 and the external connection terminal 40 are electrically connected by wire bonding.

도 2와 도 3c를 참조하면, 와이어 본딩이 완료되면 패키지 몸체(30)의 캐버티(31)가 밀폐되도록 금속덮개(50) 봉합 단계(5)를 진행한다. 패키지 몸체(30)와 금속덮개(50)를 접착시키는 수단으로서는 녹는점이 280℃인 솔더(Au80/Sn20;55)가 사용될 수 있다. 솔더(55)가 사전에 도포되어 있는 상태의 금속덮개(50)를 패키지 몸체(30)에 탑재한 후, 280℃ 이상의 분위기 온도를 인가하여 패키지 몸체(30)와 금속덮개(50)가 부착되도록 하면 내부공간(70)이 밀폐된다. 여기서, 금속덮개(50)는 내부공간에 수소나 H2O와 같이 불필요한 가스들을 제거하기 위하여 소정의 온도로 금속덮개(50)를 굽는 금속덮개 베이킹 단계(4)를 실시한 상태의 것을 사용한다.2 and 3C, when the wire bonding is completed, the sealing step 5 of the metal cover 50 is performed to seal the cavity 31 of the package body 30. As a means for bonding the package body 30 and the metal cover 50, a solder (Au80 / Sn20; 55) having a melting point of 280 ° C may be used. After mounting the metal cover 50 in the state that the solder 55 is applied in advance to the package body 30, by applying an ambient temperature of 280 ℃ or more so that the package body 30 and the metal cover 50 is attached The inner space 70 is closed. Here, the metal cover 50 is used in the state that the metal cover baking step (4) to bake the metal cover 50 at a predetermined temperature in order to remove unnecessary gases such as hydrogen or H 2 O in the inner space.

금속덮개 베이킹 단계(4)는 금속덮개(50)를 패키지 몸체(30)에 부착하기 전에 실시해주며, 금속덮개(50)에 붙어있는 솔더(55)의 녹는점보다는 낮은 온도에서 실시되도록 한다. 솔더(55)의 녹는점보다 더 높은 온도에서 금속덮개 베이킹 단계를 진행하면 금속덮개(50)에 미리 도포되어 있는 솔더(55)가 녹아버리기 때문이다. 솔더(55)의 녹는점이 280℃이기 때문에, 진공상태에서 금속덮개(50)를 약 200℃의 온도록 약 2시간동안 진행하는 것이 바람직하다.The metal lid baking step 4 is carried out before attaching the metal lid 50 to the package body 30 and is performed at a temperature lower than the melting point of the solder 55 attached to the metal lid 50. This is because when the metal cover baking step is performed at a temperature higher than the melting point of the solder 55, the solder 55 previously applied to the metal cover 50 melts. Since the melting point of the solder 55 is 280 ° C, it is preferable to proceed the metal cover 50 in a vacuum for about 2 hours at a temperature of about 200 ° C.

이상과 같은 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지(10)의 제조 방법은 종래에 사용되던 360℃ 이상의 용융온도를 갖는 실버 글래스가 아닌 200-340℃의 용융온도를 갖는 실버 글래스(25)를 사용하기 때문에 반도체 칩(20)을 부착시키기 위해 필요한 분위기 온도가 낮아진다. 그리고, 금속덮개(50)를 굽는 공정을 완료한 상태의 금속덮개(50)를 사용하기 때문에 금속덮개(50)의 부착 후에 발생될 수 있는 수소나 H2O의 양이 크게 감소된다. H2O의 발생 메카니즘을 참조하여 설명하기로 한다.The method of manufacturing the metal-cover encapsulated semiconductor chip package 10 according to the present invention as described above is a silver glass 25 having a melting temperature of 200-340 ℃ instead of a silver glass having a melting temperature of 360 ℃ or more conventionally used Because of the use, the ambient temperature required for attaching the semiconductor chip 20 is lowered. In addition, since the metal cover 50 of the state of completing the baking of the metal cover 50 is used, the amount of hydrogen or H 2 O that may be generated after the metal cover 50 is attached is greatly reduced. The generation mechanism of H 2 O will be described.

패키지 내부에 수분이 발생되는 메카니즘은 다음의 반응식과 같게 된다.The mechanism of generating water inside the package is shown in the following equation.

Figure 111999006269306-pat00001
Figure 111999006269306-pat00001

반응식 1에서와 같이 니켈과 산소가 결합하면 산화니켈이 형성되고, 이 산화니켈이 수소와 반응하면 H2O가 형성된다. 이와 같은 메카니즘에 의하여 금속덮개 봉지형 반도체 칩 패키지의 제조 공정에 적용하여 설명하면, 패키지 몸체의 캐버티 내부와 봉지 영역의 금 도금층 영역은 금 도금층의 하부의 장벽 물질인 니켈이 고온 공정하에서 확산되어 금 도금층 상부에서 산화니켈 형태의 산화물을 생성한다. 이 생성된 산화니켈이 금속덮개의 접착수단에서 배출되는 수소와 반응하여 H2O를 발생시킬 것이다. 그러나, 본 발명에서는 금 도금층 하부에 도금된 니켈의 확산을 최소화하기 위하여 200-340℃의 용융온도를 갖는 실버 글래스를 사용하고 있기 때문에 종래에 비하여 니켈의 확산을 크게 감소시킬 수 있다. 즉, 저온 경화가 이루어지기 되면 패키지의 캐버티와 봉지 영역의 금 도금층 부분의 니켈의 확산이 발생이 감소하여 산화니켈의 생성이 크게 감소된다.As in Scheme 1, nickel and oxygen combine to form nickel oxide, and when nickel oxide reacts with hydrogen, H 2 O is formed. As described above, the present invention is applied to the manufacturing process of the metal-encapsulated semiconductor chip package, and the inside of the cavity of the package body and the gold plating layer region of the encapsulation region are nickel which is a barrier material below the gold plating layer. Nickel oxide type oxide is formed on the gold plating layer. This produced nickel oxide will react with the hydrogen released from the bonding means of the metal cover to generate H 2 O. However, in the present invention, since silver glass having a melting temperature of 200-340 ° C. is used to minimize the diffusion of nickel plated under the gold plating layer, the diffusion of nickel may be greatly reduced as compared with the conventional art. That is, when the low temperature curing is performed, the diffusion of nickel in the cavity of the package and the portion of the gold plating layer in the encapsulation region is reduced, and the production of nickel oxide is greatly reduced.

또한, 금속덮개를 굽는 공정에 의하여 금속덮개에 미리 형성되어 있는 접착층에서 발생될 수 있는 수소나 H2O를 미리 형성시켜 금속덮개 접착 후에 수분의 발생요인을 사전에 제거하게 되는 것이다.In addition, hydrogen or H 2 O, which may be generated in the adhesive layer previously formed on the metal cover, may be previously formed by the process of baking the metal cover, thereby removing the cause of water generation after the metal cover is adhered in advance.

이상의 실시예에서 살펴본 바와 같이 본 발명은 금 도금층 하부에 도금된 니켈의 확산을 최소화하여 도금층 상부에서의 니켈산화막의 생성을 최소화하여 와이어 본딩 후에 진행되는 수소 클리닝 공정을 진행하지 않을 수 있으며 접착력이 향 상된다. 더우기, 금속덮개를 굽는 공정을 실시한 상태의 금속덮개를 사용할 경우에 조립 완료된 패키지의 내부 수분 함유량이 크게 감소되어 별도의 수소 클리닝 공정이 필요없게 된다.As described in the above embodiments, the present invention minimizes the diffusion of nickel plated on the bottom of the gold plating layer to minimize the generation of nickel oxide film on the top of the plating layer so that the hydrogen cleaning process may not be performed after wire bonding, and the adhesion strength is improved. It hurts. In addition, when the metal cover is used in a state in which the metal cover is baked, the internal moisture content of the assembled package is greatly reduced, so that a separate hydrogen cleaning process is not required.

이상과 같은 본 발명에 따른 금속덮개 봉지형 반도체 칩 패키지의 제조 방법에 따르면 수소 클리닝 공정을 생략할 수 있다. 따라서, 폭발의 위험성이 있는 수소 가스를 사용하지 않아도 되어 안전성 측면에서 유리한 생산라인 환경을 구축할 수 있으며, 하나의 공정을 생략할 수 있어 생산성 측면에서 유리한 이점이 있다.
According to the method for manufacturing a metal lid encapsulated semiconductor chip package according to the present invention as described above, the hydrogen cleaning process may be omitted. Therefore, it is not necessary to use the hydrogen gas of the risk of explosion can build an advantageous production line environment in terms of safety, one step can be omitted, there is an advantage in terms of productivity.

Claims (3)

상면으로부터 소정 깊이로 형성된 캐버티(cavity)와 상기 캐버티에 의해 패키지 몸체로부터 노출된 회로패턴을 가지는 세라믹 재질의 패키지 몸체의 바닥면에 반도체 칩을 실장하여 금속덮개로 봉지되는 금속덮개 봉지형 반도체 칩 패키지의 제조 방법으로서,A metal cover encapsulated semiconductor encapsulated with a metal cover by mounting a semiconductor chip on a bottom surface of a ceramic package body having a cavity formed to a predetermined depth from an upper surface and a circuit pattern exposed from the package body by the cavity. As a method of manufacturing a chip package, ⒜ 200-340℃ 경화용 실버 글래스를 캐버티에 의해 형성된 패키지 몸체의 바닥면에 도포하고 그 위에 반도체 칩을 패키지 몸체의 캐버티에 위치하도록 부착하는 칩 실장 단계, ⒝ 상기 실버 글래스를 경화시켜 반도체 칩을 고정시키는 단계, ⒞ 패키지 몸체의 캐버티에 노출된 회로패턴과 반도체 칩을 도전성 금속선으로 연결시키는 와이어 본딩 단계, 및 ⒟ 솔더 도금층이 형성되어 있는 상태에서 베이킹이 완료된 금속덮개를 솔더가 용융되는 분위기 온도를 인가하여 패키지 몸체에 부착하여 내부공간을 밀폐시키는 금속덮개 봉합 단계를 포함하는 것을 특징으로 하는 금속덮개 봉지형 반도체 칩 패키지 제조 방법.칩 a chip mounting step of applying a 200-340 ° C. hardening silver glass to the bottom surface of the package body formed by the cavity and attaching the semiconductor chip to the cavity of the package body thereon; ⒝ hardening the silver glass A step of fixing the chip, (c) bonding the circuit pattern exposed to the cavity of the package body and the semiconductor chip with a conductive metal wire, and (b) melting the solder on the metal cover which has been baked in the state where the solder plating layer is formed. A metal cover encapsulation type semiconductor chip package manufacturing method comprising the step of attaching to the package body by applying an ambient temperature to seal the inner space sealing. 삭제delete 제 1항에 있어서, 상기 금속덮개 베이킹 단계는 200℃에서 2시간 진행하는 것을 특징으로 하는 금속덮개 봉지형 반도체 칩 패키지 제조 방법.The method of claim 1, wherein the baking of the metal cover is performed at 200 ° C. for 2 hours.
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JPS636848A (en) * 1986-06-27 1988-01-12 Fujitsu Ltd Semiconductor device

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JPS636848A (en) * 1986-06-27 1988-01-12 Fujitsu Ltd Semiconductor device

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