KR100616311B1 - Transistor of semiconductor element and a method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, wherein a buffer layer, a first silicon doping layer, a first conductive layer, and a second silicon doping layer having a different doping concentration from the first silicon doping layer are provided on a semi-insulating substrate. An epitaxial substrate on which a second conductive layer is sequentially stacked, a source electrode and a drain electrode formed on both sides of the second conductive layer so as to penetrate to a predetermined depth of the first silicon doped layer to form an ohmic contact; A gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode and the source electrode and the drain electrode are electrically insulated by an insulating film. The upper portion of the gate electrode is formed by overlapping a predetermined portion on at least one of the source electrode and the drain electrode, Increasing the maximum voltage limit applied to the switch element due to the increase of the gate turn-on voltage, the breakdown voltage, and the decrease in the horizontal conduction component to increase the high power and low distortion characteristics and the isolation according to the improvement of the power transport capability of the switch device. You can expect the effect.

Semiconductor Devices, Insertion Loss, Gate Electrodes, Low Loss Switches, High Speed Switches

Description

Transistor of semiconductor element and a method for fabricating the same

1 is a schematic cross-sectional view illustrating a transistor of a semiconductor device according to an embodiment of the present invention.

2A and 2B are graphs illustrating output power and isolation characteristics according to input power in the transistor ON-state and the OFF-state of the semiconductor device according to the prior art and the embodiment of the present invention, respectively.

3 is a circuit diagram schematically illustrating a four single-pole-double-throw (SPDT) switch for comparing the superiority of transistors of a semiconductor device according to an exemplary embodiment of the present invention.

4A and 4B are graphs showing output power, isolation, and insertion loss characteristics according to input power in an SPDT circuit using a transistor of a semiconductor device according to the prior art and the present invention, respectively.

*** Explanation of symbols for the main parts of the drawing ***

10: semi-insulating substrate, 20: buffer layer,

21: AlGaAs / GaAs superlattice buffer layer, 23: AlGaAs buffer layer,

30: first silicon doped layer, 40: first conductive layer,

41: first spacer, 43: channel layer,

45: second spacer, 50: second silicon doped layer,

60: second conductive layer, 61: schottky contact layer,

63: cap layer, 70: source electrode,

80: drain electrode, 90: gate electrode,

100: first insulating film layer, 110: second insulating film layer,

120: metal pattern

The present invention relates to a compound semiconductor switch device which is a key element of a compound semiconductor switch MMIC (Microwave Monolithic Integrated Circuit) used in the control of a high power high frequency signal, and a method of manufacturing the same. The present invention relates to a transistor of a semiconductor device suitable for designing and manufacturing a high power low distortion high frequency control circuit together with a switching speed, and a method of manufacturing the same.

In general, a mobile communication device such as a cellular phone or a wireless LAN often uses microwaves in the GHz band, and a switch element for switching such a high frequency signal using an antenna switching circuit or a transmission / reception switching circuit is used. There are many cases.

These switch elements are high electron mobility transistors, which are compound semiconductor transistors, because they have good transmission characteristics, low current consumption, and driving voltage characteristics in high frequency bands, simple bias circuits, and easy implementation and integration of multiple ports. Field Effect Transistors (FETs) such as Transistors, HEMTs, or Metal-Semiconductor Field Effect Transistors (MESFETs) are mainly used.

In addition, high frequency switch circuits require insertion loss to be as small as possible, and to improve isolation and switching speed, and particularly high power with excellent linearity for radio wave control circuits for cellular or analog terminals. The design of the switch element is very important.

In the prior art, in order to reduce the insertion loss, a method of reducing the resistance of the channel region was selected by designing the impurity concentration or the width of the transistor channel used in the circuit as large as possible.

However, there is a problem that the capacitance caused by the Schottky contact formed between the gate electrode and the channel region is increased, and the high frequency input signal leaks from the leakage, thereby degrading the isolation.

In order to solve this problem, conventionally, there is a method of improving isolation by installing a shunt transistor in a circuit design process, but it causes another problem that the cost increases due to the large chip size.

Therefore, in order to fabricate a high power high frequency control circuit with improved power handling capability using a low power switch device, 1) an impedance transformation technique, 2) a stacked FETs method, and 3) Using circuit design techniques such as LC resonant circuit technique, or 4) squeezed-gate FET structure, 5) two kinds of pinch-off voltage FET structure, and 5) multigate structure. The technique of changing the device structure is mainly used.

However, when using the circuit design technique, the transmission line of the 4 / λ transformer, the large number of FETs used, and the inductor or capacitor added to the periphery of the switch element increase the chip size, which causes another cost increase. In case of using the conventional device restructuring technique, the manufacturing cost of the chip increases like the circuit design technique due to the additional mask process and the increase of the source-drain spacing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to optimize the structure of the epi substrate so that the insertion loss in the ON-state is reduced and the isolation in the OFF-state is increased. A transistor of a device and a method of manufacturing the same are provided.

Another object of the present invention is to improve a gate-drain breakdown voltage characteristic to allow a larger RF voltage swing during a switch operation, and to provide a transistor of a semiconductor device capable of low voltage operation and a method of manufacturing the same.

It is still another object of the present invention to provide a transistor of a semiconductor device having excellent power characteristics and distortion characteristics, and a method of manufacturing the same, by reducing an effective gate voltage, which is a positive value induced by an RF swing to a gate electrode even when an applied high frequency signal is high. It is.

It is still another object of the present invention to provide a transistor of a semiconductor device capable of designing and manufacturing a compact and economical circuit that reduces the increase in chip size by adding a circuit composed of an inductor and a capacitor around a transistor in manufacturing a high power switch circuit. It is to provide a method of manufacturing the same.

In order to achieve the above object, a first aspect of the present invention provides a second silicon doped layer having a doping concentration different from that of the buffer layer, the first silicon doped layer, the first conductive layer, and the first silicon doped layer on a semi-insulated substrate. And an epitaxial substrate on which the second conductive layer is sequentially stacked; A source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate to a predetermined depth of the first silicon doped layer to form an ohmic contact; And a gate electrode formed on a second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode is electrically connected to the source electrode and the drain electrode by an insulating film. The semiconductor device is insulated from each other, and an upper portion of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode.

Here, the upper portion of the gate electrode is preferably made of a 'b' shape so as to overlap a predetermined portion of the source electrode.

Preferably, the gate electrode has a gamma (Γ) shape such that an upper portion of the gate electrode is overlapped with the drain electrode.

Preferably, the gate electrode has a 'T' shape such that an upper portion of the gate electrode overlaps a predetermined portion of the source electrode and the drain electrode, respectively.

According to a second aspect of the present invention, (a) a buffer layer, a first silicon doped layer, a first conductive layer, a second silicon doped layer and a second conductive layer having a different doping concentration from the first silicon doped layer are provided on the semi-insulated substrate. Stacking the layers sequentially; (b) forming a metal thin film on the second conductive layer to form a source electrode and a drain electrode for forming an ohmic contact to penetrate to a predetermined depth of the first silicon doped layer; (c) etching a portion of the second conductive layer to a predetermined depth; And (d) forming a first insulating film to expose a predetermined region of the second conductive layer etched on the entire upper surface of the resultant product. (e) forming a gate electrode on the exposed second conductive layer, wherein an upper portion of the gate electrode overlaps at least one of the source electrode and the drain electrode; And (f) forming a second insulating film on the entire upper surface of the resultant, and then removing the first and second insulating films so that predetermined regions of the source and drain electrodes are exposed, and on the exposed source and drain electrodes. It is to provide a transistor manufacturing method of a semiconductor device comprising the step of forming a predetermined metal pattern.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms and should not be construed that the scope of the present invention is limited by the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

FIG. 1 is a schematic cross-sectional view illustrating a transistor of a semiconductor device according to an embodiment of the present invention. An average doping concentration of a channel layer is increased to reduce an insertion loss in an on-state, and is turned off. The epistructure is optimized to reduce the channel layer leakage current component while increasing the gate breakdown and turn-on voltages to increase the isolation of the -state.

Referring to FIG. 1, a transistor of a semiconductor device according to an embodiment of the present invention, that is, a high power high frequency switch device, may include a buffer layer 20 and a first silicon doping layer (Si planar doping) on a GaAs semi-insulating substrate 10. 30), the first conductive layer 40, the second planar doping layer 50 having a different doping concentration from the first silicon doping layer 30, and the second conductive layer 60 are sequentially Stacked epitaxial substrates.

In addition, a source electrode 70 and a drain electrode 80 are formed on both sides of the second conductive layer 60 so as to penetrate to a predetermined depth of the first silicon doped layer 30 to form an ohmic contact. And a gate electrode 90 formed on the second conductive layer 60 between the source electrode 70 and the drain electrode 80 to form a contact with the second conductive layer 60.

In addition, a silicon nitride (SiNx) dielectric, that is, a first insulating layer 100 and a second insulating layer for electrically insulating the gate electrode 90, the source electrode 70, and the drain electrode 80 from each other. And a predetermined metal pattern 120 formed on the source electrode 70 and the drain electrode 80, respectively.

Here, the buffer layer 20 is formed on the semi-insulating substrate 10, the AlGaAs / GaAs superlattice buffer layer 21 and the AlGaAs / GaAs second to prevent leakage current during epitaxial growth An AlGaAs buffer layer (i-AlGaAs) 23 formed of undoped AlGaAs on the lattice buffer layer 21 is formed.

The AlGaAs / GaAs superlattice buffer layer 21 is preferably formed by repeating an AlGaAs layer having a thickness of about 30 μs to 50 μs and a GaAs layer having a thickness of about 30 μs to 50 μs by about 30 to 50 cycles.

In addition, in order to increase the quality of crystals grown in the AlGaAs layer and the channel layer carrier confinement capability in the AlGaAs / GaAs superlattice buffer layer 21, the composition ratio of crystalline Al is smaller than the composition ratio of Ga, for example, about It is preferable that it is contained in 0.3 mol ratio or less.

The first conductive layer 40 may be formed of an i-AlGaAs spacer 41 formed of undoped AlGaAs on the first silicon doped layer 30 and an upper portion of the first spacer 41. A channel layer (undoped InGaAs) 43 formed of undoped InGaAs, and a second spacer (i-AlGaAs spacer 45) formed of undoped AlGaAs on top of the channel layer 43.

In this case, the first spacer 41 is formed in a thickness range of about 1 nm to 5 nm, the channel layer 43 is formed in a thickness range of 10 nm to 20 nm, and the second spacer 45 is It is preferably formed in a thickness range of about 2 nm to 10 nm.

In addition, the composition ratio of crystalline Al grown to increase the quality of crystals grown in the AlGaAs layer and the channel layer carrier confinement capability in the first spacer 41 and the second spacer 45 is Ga. It is preferred to be formed smaller, for example, in an amount of about 0.3 molar ratio or less.

In addition, the composition ratio of the crystalline In grown to increase the quality of the crystal grown in the channel layer 43 and the channel layer carrier confinement ability is formed to be smaller than the composition ratio of Ga, for example, about 0.25 molar ratio or less. This is preferable.

The second conductive layer 60 is an undoped AlGaAs 61 formed of undoped AlGaAs on top of the second silicon doped layer 50 and an upper portion of the Schottky contact layer 61. It is made of a cap layer (i-GaAs) 63 formed of undoped GaAs.

At this time, in order to increase the quality of crystals grown in the AlGaAs layer and the channel layer carrier confinement capability of the Schottky contact layer 61, the composition ratio of Al of crystalline Al is smaller than the composition ratio of Ga, for example, about 0.3 molar ratio. It is preferable to be contained and formed below.

In addition, the Schottky contact layer 61 and the cap layer 63 is preferably formed in a thickness range of about 20nm to 50nm.

Meanwhile, the source electrode 70 and the drain electrode 80 forming the ohmic contact in the epitaxial substrate structure are deeply formed to the first silicon doped layer 30 by ohmic heat treatment. It is omitted for convenience. In addition, a gate electrode 90 is formed between the source electrode 70 and the drain electrode 80 to form the schottky contact layer 61 and the schottky contact.

Here, the gate electrode 90 is preferably formed in the undoped AlGaAs Schottky contact layer 61 after etching the undoped GaAs cap layer 63.

The undoped AlGaAs Schottky contact layer 61 may improve the linearity of the switch circuit by reducing the gate-drain breakdown voltage and the gate turn-on voltage, and may reduce parallel conduction.

In addition, the gate electrode 90 is preferably located at an intermediate distance between the source electrode 70 and the drain electrode 80 in terms of input / output characteristics of the switch element. That is, the distance between the gate electrode 90 and the source electrode 70 is preferably equal to the distance between the gate electrode 90 and the drain electrode 80.

On the other hand, the gate electrode 90 has an inverse gamma shape, that is, a '-' shape, so that an embedded capacitor Cgs is formed between the source electrode 70 and the head of the gate electrode 90, that is, an upper portion thereof. It is preferably made of. The embedded capacitor Cgs may be formed of a metal-insulator-metal (MIM) structure including the gate electrode 90, the first and second insulating layers 100 and 110, and the source electrode 70. In this case, the dielectric constant (capacitance) may be calculated from the overlapping area, and a value necessary in the design process may be used.

In addition, the gate electrode 90 may have a gamma (Γ) shape such that an embedded capacitor Cgd is formed between the drain electrode 80 and the upper portion of the gate electrode 90. Cgd) may be formed in a MIM structure including the gate electrode 90, the first and second insulating layers 100 and 110, and the drain electrode 80.

In addition, the shape of the gate electrode 90 has a tee (T) such that internal capacitors Cgs and Cgd are formed between an upper portion of the gate electrode 90 and both sides of the source electrode 70 and the drain electrode 80. It may be made in the shape of a).

As described above, in the transistor of the semiconductor device according to the embodiment of the present invention, that is, the high frequency switch device, the reduction of the insertion loss in the ON-state is caused by the first silicon doping layer 30 and the second silicon. In addition to the increase in the silicon (Si) concentration of the doped layer 50 can be implemented by the reduction in contact resistance caused by deeply forming the ohmic contact of the source-drain.

On the other hand, in order to reduce the substrate leakage current component of the switch element in the OFF state and to increase the switching speed of the switch circuit, the channel layer depth is controlled by the control voltage applied to the gate electrode 90 in the OFF state. Since the strength of the electric field distributed in the direction becomes weaker, this should be taken into account when designing the doping concentration of the channel layer.

Therefore, the doping concentration of the first silicon doped layer 30 in the deep position from the Schottky contact surface must be lower than that of the second silicon doped layer 50 in the shallow position so that the depletion region of the channel can be made faster for the same gate voltage. The AlGaAs / GaAs superlattice buffer layer 21 can be extended to increase the switching speed and reduce the board leakage current, thereby improving the isolation characteristics of the switch circuit.

The concentration ratio of the second silicon doped layer 50 and the first silicon doped layer 30 was calculated from the depth of the channel layer depleted by the electric field of the gate electrode 90. As a result, the doping concentration of the second silicon doped layer 50 should be about 4 times or more than the doping concentration of the first silicon doped layer 30, and the total doping concentration is considered in consideration of the reduction of ON-state insertion loss. Determine the concentration.

That is, in the high frequency switch device according to the present invention having the structure as described above, in the epi substrate having the double shaping structure, that is, the first and second silicon doped layers 30 and 50, the second silicon doped layer as an upper surface The doping concentration at 50 is designed to be larger than the doping concentration at the first silicon doped layer 30, which is the lower surface, preferably about four times or more. Therefore, by controlling the expansion speed of the depletion layer by using the strength of the electric field of the gate electrode 90 according to the channel depth, the isolation characteristic by the reduction of the substrate leakage current component can be improved and the switching speed can also be improved.

In the manufacturing method of the switch device according to the prior art, a highly doped cap layer is typically used to reduce ohmic contact resistance, but such a structure has a problem of surface leakage between gate-source or gate-drain, so that the etching is extensive. The problem was that additional processes such as wide recesses were added.

However, in the present invention, the source electrode 70 and the drain electrode 80 having the low contact resistance can be formed as well as the source-gate using the undoped GaAs cap layer 63 by using an optimized rapid heat treatment method. And the breakdown voltage between the gate and the drain and the gate turn-on voltage may be increased to improve power characteristics.

It can be seen that this structural feature is particularly excellent in the off-state. In general, the isolation characteristic of a switch circuit using a field effect transistor is deteriorated with an increase in the voltage applied to the gate electrode (or a decrease in operating voltage or low voltage operation) in the off-state. This is because the control voltage increases positively.

As such, the second silicon doped layer 50 preferably has a greater doping concentration (about 4 times or more) than the first silicon doped layer 30. For example, the doping concentration of the first silicon doped layer 30 is about 0.5 × 10 ¹² cm ^{−2 to} 2.0 × 10 ¹² cm ⁻² , and the doping concentration of the second silicon doped layer 50 is about 2 × 10. ¹² cm ^{−2 to} 8 × 10 ¹² cm ⁻² .

On the other hand, the gate breakdown voltage and the turn-on voltage by providing the undoped AlGaAs Schottky contact layer 61 and the undoped GaAs cap layer 63 for the optimization of the epi substrate structure. Properties can be improved. This characteristic improves the distortion characteristic along with the power characteristic by increasing the resistance to the effective voltage induced in the gate by the voltage swing when transmitting a high frequency high power.

Hereinafter, a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention having the above-described configuration will be described in detail.

Referring to FIG. 1, an AlGaAs buffer layer 23 formed of an AlGaAs / GaAs superlattice buffer layer 21, which is a buffer layer 20, and an undoped AlGaAs on a GaAs semi-insulating substrate 10, a first silicon doped layer 30, A first spacer 41 formed of undoped AlGaAs, a first conductive layer 40, a channel layer 43 formed of undoped InGaAs, a second spacer 45 formed of undoped AlGaAs, and the first silicon doped layer ( A second silicon doped layer 50 having a doping concentration different from 30), a Schottky contact layer 61 formed of undoped AlGaAs, which is the second conductive layer 60, and a cap layer 63 formed of undoped GaAs, in sequence. Laminated.

In this case, each of the first silicon doped layer 30 and the second silicon doped layer 50 has a silicon (Si) impurity of about 0.5 × 10 ¹² cm ^{-2 to} 2.0 × 10 by planar doping. ^It is preferable to contain and form in the doping concentration range of ¹² cm <^-2> , 2 * 10 <^12> cm <^-2> -8 * 10 <^12> cm <^-2> .

Next, a metal thin film such as AuGe / Ni / Au is formed on the undoped GaAs cap layer 63 and heat-treated by Rapid Thermal Anneal (RTA) to form a source for ohmic contact. The electrode 70 and the drain electrode 80 are formed.

On the other hand, in the method of manufacturing a switch device according to the prior art, in order to lower ohmic contact resistance, a conventionally doped cap layer is used. However, in the present invention, the metal thin film is alloyed with the semiconductor substrate by heat treatment according to an optimized heat treatment time-temperature profile. In order to penetrate deeply to the first silicon doped layer 30, the source electrode 70 and the drain electrode having low ohmic contact resistance despite the undoped GaAs cap layer 63 unlike the prior art. 80 can be formed as well as the breakdown voltage can be increased to improve power characteristics.

After the ohmic contact is formed, a shape reversal pattern (not shown) is formed on the undoped GaAs cap layer 63 using, for example, a photoresist or the like, and then the gate contact process is performed using a gate recess process. The undoped GaAs cap layer 63 is first etched to expose a portion of 61.

Next, for example, the first insulating layer 100 is deposited using silicon nitride (Si ₃ N ₄ ), and then, for example, a 0.5 micron gate pattern is formed using a photoresist or the like. For example, after removing the silicon nitride thin film by using reactive ion etching (RIE), a pattern is formed by using a shape inversion process. The exposed undoped AlGaAs Schottky contact layer 61 removes about 5 nm of surface oxide to improve the Schottky contact property, and then forms a Ti / Pt / Au material to form the gate electrode 90. Deposit.

Thereafter, a second insulating film layer 110 is formed on the entire upper surface of the resultant material with the same material as that of the first insulating film layer 100, and then, the first and second upper portions of the source electrode 70 and the drain electrode 80 are formed. 2, the insulating film layer 110 is removed, and the metal pattern 120 for the source and drain electrodes plated by, for example, an electroplating method is formed on each of them, thereby completing the fabrication.

In general, the presence of a gate leakage current when the switch circuit is operated causes a reduction in the gate effective control voltage, which is the on-voltage and off-voltage itself during the RF full cycle at high power levels. Has a problem in that it is not effective as a switch and increases the operating voltage due to the nonlinear characteristic of the switch. However, the improved gate leakage current characteristics and the increase of the turn-on voltage and the breakdown voltage are such a problem. Eliminating the problem, it is possible to manufacture linear high power high frequency switch elements.

The gate electrode 90 is then formed between the source electrode 70 and the drain electrode 80 by, for example, a lift-off method. In addition, in terms of input / output characteristics of the switch element, the distance between the gate electrode 90 and the source electrode 70 is preferably equal to the distance between the gate electrode 90 and the drain electrode 80. On the other hand, as described above, the gate electrode 90 is preferably formed in the shape of any one of the letter 'a', gamma (Γ) or tee (T).

The invention will be explained in more detail through the following non-limiting experimental examples. In addition, since the content which is not described here can be deduced technically enough by those skilled in the art, the description is abbreviate | omitted.

Experimental Example 1

2A and 2B are graphs illustrating output power and isolation characteristics according to input power in the transistor ON-state and the OFF-state of the semiconductor device according to the prior art and the embodiment of the present invention, respectively. .

Referring to FIG. 2A, a transistor of a semiconductor device, that is, a switch device according to the related art is manufactured, and the ON-state (-○-) and the OFF-state ( -□-) shows the characteristic change of output power.

The fabricated switch element had a width of about 1.2 mm and a unit gate width of about 150 microns. The power handling capability of the switch is defined as the input power of which the isolation of the OFF-state is poor. In FIG. 2A, the switch has a power of about 23 μm. This value is easily seen from the change in isolation (-Δ-) expressed as the difference between the output power of the ON- and OFF-states.

Referring to FIG. 2B, a switch device having a gate electrode 90 having an inverse gamma-type, ie '-' shape according to an embodiment of the present invention is fabricated and turned on according to input power at an operating frequency of about 2.4 GHz. It shows the characteristic change of output power in) -state (-●-) and OFF-state (-■-). In the case of the present invention, the power transport capacity is about 25 mW, and this value can be easily seen from the change in isolation (-▲-) expressed as the difference between the output power of the on-state and the off-state. .

That is, in the case of the switch element having a '-' shaped gate electrode 90 according to an embodiment of the present invention, it can be seen that the power transport capacity is improved by about 2 비 compared to the conventional gate structure (rectangular). have. This improvement in power transfer capability can be seen more prominent when fabricating the switch circuit as shown in FIG. 3 using the switch element according to an embodiment of the present invention.

Experimental Example 2

FIG. 3 is a circuit diagram schematically illustrating a four single-pole-double-throw (SPDT) switch for comparing the superiority of transistors of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, two series transistors (NFET ₁₂ and NFET ₂₁ ) having a gate width of about 1.2 mm and eight shunt transistors (OFET ₁₁ and OFET ₂₂ ) having about 0.3 mm are formed.

The superiority of the present invention is that eight transistors coupled by shunt among these transistors have a gate electrode structure of the prior art, except that two (NFET ₁₂ , NFET ₂₁ ) connected in series have a gate electrode structure of the prior art. For example, the case where the gate electrode 90 has a '-' shape was evaluated by comparing the power characteristics.

4A and 4B are graphs illustrating output power, isolation, and insertion loss characteristics according to input power in an SPDT circuit using a transistor of a conventional device and a semiconductor device according to an embodiment of the present invention, respectively. An SPDT switch circuit (MMIC) device of FIG. 3 is manufactured by using a switch device according to an embodiment of the present invention, and the output power of ON-state and OFF-state according to input power at an operating frequency of about 2.4 GHz is measured. Show the characteristics of each.

In FIG. 4A,-○-is the output power in the ON-state according to the conventional comparative example,-□-is the output power in the OFF-state, and-△-is the ON-state. The difference in output power in the OFF state is the isolation between the two throws in the SPDT, and-◇-is the difference between the output power and input power in the ON state and is eventually RF The amount of insertion loss of a signal.

The power handling capability of the switch circuit is determined by the maximum current limit of the transistor in the ON state, and the maximum voltage limit applied to the device in the OFF state. maximum voltage limit, but is substantially limited because loss of isolation occurs in the OFF-state rather than the compression of the RF signal in the ON-state.

Thus, the power transport capability of the switch circuit is defined as the input power value at which the off-state isolation is about 1 dB worse. The input power of which the isolation or insertion loss characteristic is reduced by about 1 dB is about 26 dB, which is the power carrying capacity of the SPDT switch circuit according to the conventional comparative example.

In Fig. 4b,-●-is the output power of the ON-state,-■-is the output power of the OFF-state, and-▲-is ON according to an embodiment of the present invention. The difference between the output power of the state and the OFF state is the isolation between the two paths in the SPDT, and the difference of the output power and input power of the ON state is the result of the RF signal. The amount of insertion loss. As in FIG. 4A, the input power of which the isolation and insertion loss characteristics are reduced by about 1 dB is about 30 mA, which represents the power driving capability of the SPDT switch circuit according to an embodiment of the present invention. It can be seen that the power transport capacity of about 4 kW is improved compared to the conventional comparative example.

This data suppresses an increase in output power when the gate electrode 90 structure of the switch element according to the exemplary embodiment of the present invention is in an OFF state, which means that the source electrode 70 and the gate of the '-' shape are shaped. The increase in the capacitance component Cgs by the capacitor embedded between the electrodes 90 implies that the effective voltage applied to the gate electrode 90 is reduced, resulting in a switch circuit having excellent power and distortion characteristics. do.

Although a preferred embodiment of a transistor and a method of manufacturing the semiconductor device according to the present invention described above have been described, the present invention is not limited to this, but the scope of the claims and the detailed description of the invention and the accompanying drawings in various ways It is possible to carry out modifications and this also belongs to the present invention.

According to the transistor of the semiconductor device of the present invention as described above and the method of manufacturing the same, in the case of a switch device obtained from an optimized epi substrate having a double shaping structure, the expansion speed of the depletion region according to the channel depth (the slope of the transconductance Gains by varying the rate of change, i.e. increased isolation and increased switching speed, as well as the advantage of forming Schottky gate contacts formed in the undoped AlGaAs layer, i.e., increased gate turn-on voltage, breakdown Increasing the voltage and decreasing the horizontal conductance component increases the maximum voltage limit applied to the switch element, which can be expected to increase the high power and low distortion characteristics and isolation in the event of an improvement in the power transport capability of the switch device. .

According to the present invention, when designing a switch circuit (MMIC) using a switch element having a built-in capacitor, a separate 4 / λ transformer transmission line, an inductor, or a capacitor for improving power transmission capability is not used near the switch element. The chip size can be reduced, thereby reducing the production cost by improving the yield and directness of the switch circuit manufacturing process.

Claims (15)

An epitaxial substrate in which a buffer layer, a first silicon doped layer, a first conductive layer, a second silicon doped layer having a different doping concentration from the first silicon doped layer, and a second conductive layer are sequentially stacked on the semi-insulated substrate; A source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate to a predetermined depth of the first silicon doped layer to form an ohmic contact; And A gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, An insulating film is electrically insulated between the gate electrode, the source electrode, and the drain electrode, and an upper portion of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. transistor. The transistor of claim 1, wherein an upper portion of the gate electrode has a '-' shape so as to overlap a predetermined portion with the source electrode. The transistor of claim 1, wherein the upper portion of the gate electrode has a gamma (Γ) shape so as to overlap a predetermined portion with the drain electrode. The semiconductor device transistor of claim 1, wherein an upper portion of the gate electrode has a 'T' shape so as to overlap a predetermined portion with the source electrode and the drain electrode, respectively. The method of claim 1, wherein the buffer layer, An AlGaAs / GaAs superlattice buffer layer formed on the semi-insulating substrate to prevent leakage current during epitaxial growth; And And an AlGaAs buffer layer formed of undoped AlGaAs on top of the AlGaAs / GaAs superlattice buffer layer. The method of claim 1, wherein the first conductive layer, A first spacer formed of undoped AlGaAs on the first silicon doped layer; A channel layer formed of undoped InGaAs on the first spacer; And And a second spacer formed of undoped AlGaAs on the channel layer. The method of claim 1, wherein the second conductive layer, A schottky contact layer formed of undoped AlGaAs on the second silicon doped layer; And And a cap layer formed of undoped GaAs on the Schottky contact layer. (a) sequentially depositing a buffer layer, a first silicon doped layer, a first conductive layer, a second silicon doped layer and a second conductive layer having a different doping concentration from the first silicon doped layer on the semi-insulated substrate; (b) forming a metal thin film on the second conductive layer to form a source electrode and a drain electrode for forming an ohmic contact to penetrate to a predetermined depth of the first silicon doped layer; (c) etching a portion of the second conductive layer to a predetermined depth; And (d) forming a first insulating film to expose a predetermined region of the second conductive layer etched on the entire upper surface of the resultant product; (e) forming a gate electrode on the exposed second conductive layer, wherein an upper portion of the gate electrode overlaps at least one of the source electrode and the drain electrode; And (f) forming a second insulating film on the entire upper surface of the resultant, and then removing the first and second insulating films so that predetermined regions of the source and drain electrodes are exposed, and predetermined on the exposed source and drain electrodes. Forming a metal pattern of a transistor manufacturing method comprising a semiconductor device. The method of claim 8, wherein the buffer layer in the step (a), Forming an AlGaAs / GaAs superlattice buffer layer on the semi-insulating substrate to prevent leakage current during epitaxial growth; And And forming an AlGaAs buffer layer with undoped AlGaAs on top of the AlGaAs / GaAs superlattice buffer layer. The method of claim 8, wherein in the step (a), the first conductive layer comprises: forming a first spacer with undoped AlGaAs on top of the first silicon doped layer, and undoping on top of the first spacer. Forming a channel layer with InGaAs, and forming a second spacer with undoped AlGaAs on top of the channel layer, The second conductive layer includes forming a schottky contact layer with undoped AlGaAs on top of the second silicon doped layer, and forming a cap layer with undoped GaAs on top of the schottky contact layer. A transistor manufacturing method of a semiconductor device, characterized in that made. The method of claim 8, wherein in the step (e), an upper portion of the gate electrode is formed to have a '-' shape so as to overlap a predetermined portion with the source electrode. 10. The method of claim 8, wherein in the step (e), an upper portion of the gate electrode is formed in a gamma shape to overlap a portion of the drain electrode. The semiconductor device transistor of claim 8, wherein in the step (e), an upper portion of the gate electrode is formed in a 'T' shape so as to overlap a predetermined portion with the source electrode and the drain electrode, respectively. Way. 9. The method of claim 8, wherein the second silicon doped layer is formed at a doping concentration of at least four times that of the first silicon doped layer. 15. The method of claim 14, wherein the doping concentration of the first silicon doped layer is 0.5 × 10 ¹² cm ^{-2 to} 2.0 × 10 ¹² cm ^-2 , the doping concentration of the second silicon doped layer is 2 × 10 ¹² cm ^-2. A method of manufacturing a transistor of a semiconductor device, characterized in that implemented in the ~ 8 × 10 ¹² cm ^-2 .

Images