KR100615401B1 - Deterministic test pattern generating apparatus using phase shifter - Google Patents

Abstract

In the case of logic BIST applying a deterministic test pattern, a deterministic test pattern is applied after applying a pseudorandom test pattern to some extent. In this case, both the pseudorandom BIST and the deterministic BIST must be equipped with hardware. Phase shifters are typically hardware used in almost all pseudorandom BISTs. Therefore, using phase shifters in deterministic BIST is an area efficient method because they share the same functional blocks. In addition, since the deterministic pattern generation hardware proposed in the present invention uses the window characteristics of the M sequence, unlike the conventional method, it is possible to generate all the deterministic test patterns regardless of the current LFSR pattern. Therefore, unlike the existing method, it is possible to generate the required pattern in a short time.

BIST, Pseudorandom Test Pattern, Phase Shift, Scanning Sequence

Description

Deterministic test pattern generating apparatus using phase shifter

1A and B are block diagrams of an apparatus for generating a deterministic test pattern in a conventional multiple scanning sequence environment.

FIG. 2 is an exemplary diagram for describing a pattern output from the LFSR of FIG. 1. FIG.

3 is a flowchart of a synthesis algorithm of a phase shifter according to the present invention;

4 to 6 are each step result obtained by performing the algorithm of FIG.

7 is a block diagram of an apparatus for generating a deterministic test pattern according to the present invention.

8 is a block diagram of a device for generating a deterministic test pattern for one scan string in the apparatus according to the present invention.

The present invention relates to an apparatus for generating a test pattern for deterministic BIST for a circuit having multiple scan chains.

Built-In Self Test (BIST), one of the "Design For Testability (DFT) Techniques", is designed to logic the functional blocks needed for the test and embed them inside the chip. It is an effective technique that can greatly reduce the test cost by reducing test dependence by testers.

In order for an embedded self-test to be economically viable, several design requirements must be met, including the overhead of the test logic, the power consumed during the test, the final fault coverage, For example, test time.

Among them, the failure detection rate and the test time are closely related. In other words, the higher the number of test patterns, the higher the failure detection rate, but require a relatively long test time. On the contrary, when a small number of test patterns are applied, only a short test time is required, but the failure detection rate is relatively high. This causes a problem of being lowered.

The built-in self-testing technique solves this problem by applying a deterministic test pattern. In other words, ATPG (Automatic Test Pattern Generation) program is used to generate a minimum test pattern that can achieve a high failure detection rate in advance, and the hardware capable of generating this test pattern is designed as a built-in self test pattern generator. The goal of deterministic BIST is to achieve high failure detection rates with only the test length.

A representative prior art of deterministic BIST for circuits with multiple scan chains compares the output of LFSR, which produces a pseudorandom pattern, with the deterministic test pattern of each scan sequence, as shown in Figures 1a and b. We then use a method of repositioning the possible connections between the output of the LFSR and each scan sequence per test pattern (this is called "deterministic BIST using reconfigurable interconnection").

For example: Assume that the circuit under test has four scan strings, and each scan string is composed of four scan cells. Also assume that the deterministic test pattern obtained through ATPG for this circuit is shown in Table 1.

Test Pattern 1 (C1) Test Pattern 2 (C2) Test Pattern 3 (C3) Test Pattern 4 (C4) Scan fever 1 00xx 0xxx xx11 xx11 Scan fever 2 1xx0 xx1x x10x 1xxx Scan fever 3 10xx 01xx x1x0 01xx Scan fever 4 x0xx 11xx 10xx x001

If you use an LFSR with a characteristic polynomial of x ⁴ + x ³ +1 and the initial value is 0001 (x4 x3 x2 x1), then the LFSR generates a pseudorandom pattern in the order shown in Figure 2. do.

Briefly describing a deterministic BIST technique in a multi-scanning environment, an interconnection network (FIG. 1B) may be used to connect an LFSR output that satisfies a deterministic pattern to a corresponding scan string. ). The process is as follows.

First, as an initialization process, all LFSR outputs are configured as outputs of LFSRs that can be connected to each scan string. In other words,

Conn ₁ ⁽¹⁾ = {1, 2, 3, 4},

Conn ₂ ⁽¹⁾ = {1, 2, 3, 4},

Conn ₃ ⁽¹⁾ = {1, 2, 3, 4},

Conn ₄ ⁽¹⁾ = {1, 2, 3, 4}. Here, ^{i of} Conn _j ⁽ⁱ⁾ is the number of BIST configuration, j is the number of scanning sequence (number).

Next, find out all the interconnection configurations that can generate the deterministic pattern while the LFSR generates the pseudorandom pattern of P1 among the previous Conn _j ⁽ⁱ⁾ . In this case, a deterministic pattern of c1 may be generated in the following interconnection arrangement during the interval of P1.

P1: c1

Conn ₁ ⁽¹⁾ = {1, 4},

Conn ₂ ⁽¹⁾ = {2},

Conn ₃ ⁽¹⁾ = {2},

Conn ₄ ⁽¹⁾ = {1, 4}

Subsequently, c3 can be generated during the LFSR pattern generation process of P2 during the Conn _j ⁽ⁱ⁾ of the previous step, and the result is as follows.

P2: c3

Conn ₁ ⁽¹⁾ = {4},

Conn ₂ ⁽¹⁾ = {2},

Conn ₃ ⁽¹⁾ = {2},

Conn ₄ ⁽¹⁾ = {1, 4}

Among the Conn _j ^{(i) thus} far, there is no deterministic pattern that can be generated by interconnection arrangement in the LFSR pattern generation process of P3. Next, during the generation of the LFSR pattern of P4, a deterministic test pattern of C2 can be generated, and the result is as follows.

P4: c2

Conn ₁ ⁽¹⁾ = {4},

Conn ₂ ⁽¹⁾ = {2},

Conn ₃ ⁽¹⁾ = {2},

Conn ₄ ⁽¹⁾ = {1, 4}

This process is repeated until all deterministic test patterns can be generated.

The core of the prior art for generating deterministic test patterns in a multiscanning environment is the interconnection between the LFSR and the scanning sequence so that each output of the LFSR generating a pseudorandom pattern can cover the deterministic test patterns required in the scan sequence. Is in connecting.

However, a problem with this method is that, in some cases, the length of the test pattern for obtaining a constant failure detection rate can be very long. This can be seen in the example above. In the above example, the deterministic test patterns of C1 and C3 can be generated in the P1 and P2 time intervals of the LFSR, but the deterministic test patterns cannot be covered in the P3 time interval. This is the interconnection configuration of Conn _j ^{(i) where} the search space is possible up to the output time interval of the previous LFSR when obtaining a deterministic test pattern that can be covered in the output time interval of the current LFSR. It is due to being limited. The output time interval of the LFSR, which does not cover any deterministic test patterns, will increase even more as Conn _j ⁽ⁱ⁾ decreases in size over time.

Conventionally, a parameter called "maxskippattern" has been set for this problem. That is, if the new deterministic test pattern cannot be covered during the number of LFSR output intervals set by "maxskippattern", the current interconnection arrangement is terminated and the new interconnection arrangement allows the remaining deterministic test pattern to be covered. Each time a new interconnect layout is set, Conn _j ⁽ⁱ⁾ is initialized with the output of all LFSRs. In other words, in the example above, Conn _j ⁽ⁱ⁾ = {1, 2, 3, 4}. In this case, however, the integer set by "maxskippattern" is still the upper limit of the LFSR time interval which does not cover the deterministic test pattern continuously in the current interconnection arrangement.

In order to solve this problem, we concluded that deterministic BIST, which can achieve high failure detection rate in a short test time in a multi-scanning environment, is possible by using a reconfigurable phase shifter. . Accordingly, an object of the present invention is to provide a deterministic test pattern generation apparatus using the principle of phase shifter based on M sequence as hardware for generating a deterministic test pattern.

1. Theoretical Background

(1) Properties of M Sequence

In order to generate a deterministic test pattern in multiple scan sequences, the hardware proposed in the present invention utilizes the following two properties ("transition and additional properties" and "window properties") of an M sequence. M-sequence means a sequence in which the number of patterns in one cycle generated by n-state LFSR is 2 ⁿ -1, and occurs when the characteristic polynomial of LFSR is "primitive". do.

Shift-and-Add property: a is not 0, assuming that any M sequence of length M = 2 ^m -1 is B and the bit that is a bit shifted from B to B _a If not M, the bit sum B xOR B _a is B _b transitioned back from B. [In English, let B be any M-sequence of length M = 2 ^m -1, and B _a a-bit shift of B. If a is neither 0 nor a multiple of M, then the bitwise sum B xOR B _a is another shift B _b of B.]

Window property: Assume that a window of width w moves along an M sequence of length 2 ^m −1. At this time, if w = m, all m groups are displayed once except that m-tuples of which all are "0" do not appear. More generally, w = mi (0 ≦ i ≦ m−1) causes all remaining w groups to appear 2 ⁱ times except that w-tuples of all “0s” appear 2 ⁱ −1 times. do. [In English, it is as follows: Assume a window of width w is slid along an M-sequence of length 2 ^m -1. If w = m, every m-tuple is seen once, except the all-zero m-tuple which is not seen. More generally, if w = mi, 0≤i≤m-1, every w-tuple is seen 2 ⁱ times, except the all-zero w-tuple which is seen 2 ⁱ -1 times.]

That is, the window characteristic is 2 except for the case where all the windows are zero when the M sequence of the n-stage LFSR is assumed to be a window having a length of n. it can produce ⁿ -1 different sequences. For example, in the LFSR having three stages as shown in FIG. 9, seven 3-bit sequences can be generated according to the M sequence. The present invention uses the window characteristic to find all the windows that match the deterministic test pattern in the M sequence based on the current LFSR state and calculate how much phase shift is required to make this window.

The deterministic test here because it is guaranteed that all bit sequences must be present by the window characteristic except that all deterministic test patterns can be made regardless of the current LFSR state. There is at least one window that matches the pattern.

(2) Phase shifter

The phase shifter is a circuit block using the transition and additional characteristics of the M sequence. In the test, when each output sequence of the LFSR is directly applied to the scan path, there is a high correlation between adjacent scan string patterns, thereby reducing the failure detection rate. To alleviate this problem, we use a phase shifter. A typical phase shifter is implemented as an XOR tree between LFSR and CUT (Circuit Under Test). So far known methods of designing phase shifters include the use of the transition matrix of LFSR and the use of simulation. The method of designing a phase shifter using the variance matrix of the LFSR has a drawback in that it takes a long time because a continuous matrix operation is required. On the other hand, the method of designing a phase shifter using simulation has the advantage that the phase shifter can be designed quickly using a logic simulator. The procedure for designing the phase shifter by simulation is as follows.

 1) Determining a dual LFSR

 2) Initialize the dual LFSR to the value of 10 ... 00

3) with respect to the dual LFSR 2 -1 ^n-k clock cycle simulation (Simulate the dual LFSR for 2 -1 ^n-k clock cycles)

 4) Read the resulting content of the dual LFSR: where "1" indicates the position that should be included in the phase shifter structure to obtain a sequence shifted by the number of bits of k (Read the resulting content of the dual LFSR: the locations of 1s will point out positions that should be included in a phase shifter structures to obtain a sequence shifted down by k bits).

2. Description of the Invention

The present invention is based on a "reconfigurable phase shifter" that varies the placement of the phase shifter between the LFSR and the CUT depending on the test pattern to be applied to multiple scan sequences.

(1) Synthesis Algorithm of Relocatable Phase Shifter

First, Fig. 3 shows an algorithm for synthesizing a repositionable phase shifter according to the present invention. Each step of the algorithm means:

Pattern ordering: Reordering of deterministic test patterns by ATPG. The order of the request is that the "don't-care value (x)" in a pattern comes first. This is to increase the probability that multiple test patterns can share a tap configuration.

Set i = 1: i is a character that traces the number of tap configurations.

TapConn _i ^(j) Initialization: TapConn _i ^(j) is a set with phase shifting numbers possible in the current step. I is a configuration number and j is a scanning sequence number. In the initialization process, TapConn _i ^(j) is initialized to a set of {1, 2, ...., 2 ⁿ -1} in case of n-stage LFSR.

Update (Update) of TapTable Table: TapTable is a table that stores the generation pattern related to the phase shift number at the present stage. The original table is generated by a phase shifter generation algorithm using existing simulations. This table is updated whenever a deterministic test pattern is embedded with a relocatable phase shifter. When the update rule is n-stage LFSR, only the pattern column is cyclically shifted upward while the shift column is fixed. (See example)

The current tap connection TapConn _i ^(j) under finding the test cube C * of T _D is in the range of the phase shift pattern, along with the current TapTable (Find a test cube c * in T _D that is covered by phase shifted pattern with current TapTable under the current tap connection TapConn _i ^(j) ): T _D means a set of deterministic test patterns by ATPG. Therefore, this step checks whether the pattern of the TapTable matching the phase shift number of the current TapConn _i ^(j) is compatible with the test pattern of T _D.

^{_{T D .TapConn i (j) =}} TapConn i (j) - removal of the test cube, which is found in C * U (Remove the test cube C * found from T D .TapConn i (j) = TapConn i (j) - U ) U is the set of phase shifts that do not cover the deterministic test pattern. Therefore, this process means to remove the phase shift number that does not cover the current deterministic test pattern in TapConn _i ^(j) .

Update the UTCS ^(j) table : UTCS ^(j) means the result of ORing the tap positions corresponding to TapConn _i ^(j) obtained up to the present stage by bit unit for each scan string. The process of updating UTCS (J) is performed until there are no more deterministic test patterns that satisfy the current tab layout. This is the process of selecting the minimum number of 1s as a result of OR as a criterion for selecting one of two or more phase shifts remaining in the current tap arrangement in each scan sequence (see example).

Cube left in T _D Sikkim matching test cubes remaining, the test pattern for the current layout _{(Match the remaining cubes in T D} to the test patterns for the current configuration): remain before the finish of the current tab placement process The process of removing a pattern that is already covered among deterministic test patterns.

<Example>

Hereinafter, an example of actually performing the above algorithm for improving understanding of the method according to the present invention will be described. The targets are as follows.

T _D = {{1xx10x, 1x10xx, x1xx01}, {1x110x, 10xx11, 0101xx}, {0x1x0x, x1xxxx, x1xx0x}} (see Table 2)

LFSR: For 6-stage LFSRs using a characteristic polynomial of x ⁶ + x + 1

Circuit under test: 3 scan columns with 6 scan cells per scan string

Scan fever 1 Scan fever 2 Scan fever 3 Pattern 1 1xx10x 1x10xx x1xx01 Pattern 2 1x110x 10xx11 0101xx Pattern 3 0x1x0x x1xxxx x1xx0x

1) Pattern Ordering-Table 3 shows the ordering in order of the number of x.

Scan fever 1 Scan fever 2 Scan fever 3 Pattern 1 0x1x0x x1xxxx x1xx0x Pattern 2 1xx10x 1x10xx x1xx01 Pattern 3 1x110x 10xx11 0101xx

2) i = 1

3) TapConn _i ^(J) initialization

TapConn ₁ ⁽¹⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽²⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽³⁾ = {1, 2, 3, ...., 63}

4) Update TapTable Table

By performing the phase shifter generation algorithm by simulation, the result as shown in FIG. 4 can be obtained. "Phase shift number" of each column of the table shown in FIG. 4 means a phase shift number, "pattern" means a pattern, and "tap position" means a tap position.

5) Find the test cube C * of T _{D in} the range of the phase shifted pattern with the current TapTable under the current tap connection TapConn _i ^(j).

6) T _D .TapConn _i ^(j) = TapConn _i ^(j) -removes the test cube C * found in U

The current TapConn _i ^(j) is

TapConn ₁ ⁽¹⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽²⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽³⁾ = {1, 2, 3, ...., 63}. Except for the number of transitions that do not cover pattern 1, the following TapConn _i ^(j) can be obtained.

TapConn ₁ ⁽¹⁾ = {10, 13, 17, 26, 30, 49, 50, 55}

TapConn ₁ ⁽²⁾ = {1, 2, 3, 4, 6, 8, 10, 11, 14, 15, 17, 18, 19, 21, 22, 24, 27, 30, 31, 32, 36, 38 , 39, 40, 41, 44, 46, 50, 51, 56, 62, 63}

TapConn ₁ ⁽³⁾ = {2, 4, 6, 10, 17, 22, 30, 31, 32, 39, 40, 44, 46, 50, 51, 56}

7) Updating TapTable Table

Previously, since the pattern to be covered was found, the TapTable table is updated (see Fig. 5). The update rule is as described above. FIG. 5 is a phase shift table for generating a second pattern when 011111 becomes a value of LFSR after changing the initial value of LFSR to 100000. FIG.

8) Find the test cube C * of T _{D in} the range of the phase shifted pattern with the current TapTable under the current tap connection TapConn _i ^(j).

9) T _D .TapConn _i ^(j) = TapConn _i ^(j) -removes the test cube C * found in U

The number of phase shifts of TapConn _i ^(j) covering the pattern 2 is as follows.

chain1 = {3, 16, 19, 33, 36, 59, 61, 62}

chain2 = {1, 12, 17, 25, 34, 39, 60, 62}

chain3 = {4, 11, 26, 34, 40, 59, 61, 63}

The intersection with the current TapConn _i ^(j) is as follows.

TapConn ₁ ⁽¹⁾ = {}

TapConn ₁ ⁽²⁾ = {1, 17, 39, 62}

TapConn ₁ ⁽³⁾ = {4, 40}. Since TapConn ₁ ⁽¹⁾ is the empty set, pattern 2 is not embedable in the current tap layout. Therefore, pattern 3 is examined without updating TapConn _i ^(j) and TapTable. The number of phase shifts of each scan string of the pattern 3 is as follows.

Chain1 = {6, 9, 13, 22}

Chain2 = {1, 22, 31, 41}

Chain3 = {2, 30, 38, 63}

The intersection with the current TapConn _i ^(j) is

TapConn ₁ ⁽¹⁾ = {13}

TapConn ₁ ⁽²⁾ = {1, 22, 31, 41}

TapConn ₁ ⁽³⁾ = {2, 30}

10) Updating UTCS ^(j) Tables

Update UTCS ^(j) because there are no more matching patterns for the current tab layout. The result of the update process of UTCS ^(j) is the current TapConn _i ^(j) if present can cheonyi more than one phase the standards for selecting one of them and the existing ^{"UTCS (j) OR (tap} positon)" Choose the minimum number of ones. UTCS is currently initialized.

UTCS ⁽¹⁾ = {001011}

UTCS ⁽²⁾ :

If TapConn ₁ ⁽²⁾ is 1: {100001}

If TapConn ₁ ⁽²⁾ is 22: {101110}

If TapConn ₁ ⁽²⁾ is 31: {100100}

If TapConn ₁ ⁽²⁾ is 41: {101011}

If TapConn ₁ ⁽²⁾ is 1 and 31, select {100001} because the number of 1s is the minimum of 2 (the random of the two)

UTCS ⁽³⁾ :

If TapConn ₁ ⁽³⁾ is 2: {100011}

If TapConn ₁ ⁽³⁾ is 30: {010010}

If TapConn ₁ ⁽³⁾ is 30, select {010010} because the number of 1s is the minimum of 2.

11) i = 2

12) Initialize TapConn _i ^(J)

TapConn ₂ ⁽¹⁾ = {1, 2, 3, ...., 63}

TapConn ₂ ⁽²⁾ = {1, 2, 3, ...., 63}

TapConn ₂ ⁽³⁾ = {1, 2, 3, ...., 63}

13) Updating the TapTable Table

Update the TapTable table. A phase shift table for generating a third pattern when 110101 becomes a value of LFSR after generating the second pattern (see FIG. 6).

14) Find the test cube C * of T _{D in} the range of the phase shifted pattern with the current TapTable under the current tap connection TapConn _i ^(j) .

15) T _D .TapConn _i ^(j) = TapConn _i ^(j) -Remove the test cube C * found in U.

The only remaining deterministic test pattern is pattern 2, so check for pattern 2.

The current TapConn _i ^(j) is

TapConn ₁ ⁽¹⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽²⁾ = {1, 2, 3, ...., 63}

TapConn ₁ ⁽³⁾ = {1, 2, 3, ...., 63}. Except for the number of transitions that do not cover pattern 2, the following TapConn _i ^(j) can be obtained.

TapConn ₂ ⁽¹⁾ = {8, 10, 13, 27, 30, 53, 55, 60}

TapConn ₂ ⁽²⁾ = {1, 6, 11, 19, 28, 33, 54, 56, 58}

TapConn ₂ ⁽³⁾ = {5, 20, 28, 34, 53, 55, 57, 61}

16) Update UTCS ^(j) Table

Next, update the UTCS ^(j) table because there are no more patterns that the current TapConn _i ^(j) can cover.

This time, since UTCS ^(J) is not in the initial state, select the minimum number of results 1 of UTCS ^(J) OR {tap position}.

UTCS ⁽¹⁾

When TapConn ₂ ⁽¹⁾ is 8: UTCS ⁽¹⁾ = {001011} OR {011101} = {011111}

When TapConn ₂ ⁽¹⁾ is 10: UTCS ⁽¹⁾ = {001011} OR {010101} = {011111}

When TapConn ₂ ⁽¹⁾ is 13: UTCS ⁽¹⁾ = {001011} OR {001011} = {001011}

...

... choose the lowest one

UTCS ⁽²⁾

When TapConn ₂ ⁽²⁾ is 1: UTCS ⁽²⁾ = {100001} OR {100001} = {100001}

...

...

... choose the lowest one

UTCS ⁽³⁾

When TapConn ₂ ⁽³⁾ is 5: UTCS ⁽³⁾ = {010010} OR {111111} = {111111}

When TapConn ₂ ⁽³⁾ is 20: UTCS ⁽³⁾ = {010010} OR {111011} = {111011}

...

...

...

When TapConn ₂ ⁽³⁾ is 61: UTCS ⁽³⁾ = {010010} OR {001000} = {011010}

... choose the lowest one

17) Closed because there are no more deterministic test patterns

Through the above algorithm, two tap configurations were obtained to generate three deterministic test patterns as repositionable phase shifters. the results are as follow.

When Configuration 1 (i = 1) (Pattern 1, Pattern 3 Cover)

TapConn ₁ ⁽¹⁾ = {13}

TapConn ₁ ⁽²⁾ = {1}

TapConn ₁ ⁽³⁾ = {30}

When Configuration 2 (i = 2) (Pattern 2 Cover)

TapConn ₁ ⁽¹⁾ = {13}

TapConn ₁ ⁽²⁾ = {1}

TapConn ₁ ⁽³⁾ = {61}

UTCS (j):

UTCS (1): {001011}

UTCS (2): {100001}

UTCS (3): {011010}

(2) Deterministic test pattern generation hardware

The deterministic test pattern generation hardware of the present invention utilizes the results of the relocatable phase shifter synthesis algorithm. For example, if the result of the previous algorithm is as follows, BIST logic hardware can generate as follows.

<Algorithm execution result>

① Total number of taps: 5

② configuration

Configuration 1:

Deterministic pattern to cover:

   Pattern 1, Pattern 4, Pattern 5, Pattern 8 (4 total)

Tap position

TapConn ₁ ⁽¹⁾ = {001001}

TapConn ₁ ⁽²⁾ = {010000}

TapConn ₁ ⁽³⁾ = {000001}

Configuration 2:

Deterministic pattern to cover:

   Pattern 2, Pattern 3, Pattern 11, Pattern 14, Pattern 19 (5 in total)

Tap position

TapConn ₂ ⁽¹⁾ = {001000}

TapConn ₂ ⁽²⁾ = {011000}

TapConn ₂ ⁽³⁾ = {001001}

Configuration 3:

Deterministic pattern to cover:

   Pattern 6, Pattern 10, Pattern 15 (3 in total)

Tap position

TapConn ₃ ⁽¹⁾ = {100001}

TapConn ₃ ⁽²⁾ = {010001}

TapConn ₃ ⁽³⁾ = {100001}

Configuration 4:

Deterministic pattern to cover:

    Pattern 7, Pattern 12, Pattern 16, Pattern 20 (4 in total)

Tap position

TapConn ₄ ⁽¹⁾ = {001001}

TapConn ₄ ⁽²⁾ = {010000}

TapConn ₄ ⁽³⁾ = {000001}

Configuration 5:

Deterministic pattern to cover:

   Pattern 9, Pattern 13, Pattern 17, Pattern 18 (4 in total)

Tap position

TapConn ₅ ⁽¹⁾ = {101001}

TapConn ₅ ⁽²⁾ = {010001}

TapConn ₅ ⁽³⁾ = {001001}

③ UTCS

UTCS (1): {101001}

UTCS (2): {011001}

UTCS (3): {101001}

<Hardware configuration>

Hardware of the test pattern generating apparatus according to the present invention is shown in FIG. Each block of Fig. 7 is implemented as follows.

1) Stored control bits: implemented as memory. This memory stores the number of deterministic test patterns covered by each tab layout. In this case, the values 4, 5, 3, 4, and 4 are stored in order.

2) Pattern counter: A counter that receives the stored values of the saved control bit block one by one and counts them from the back. That is, when receiving a value of 4 from the stored control bit block, the pattern applied to the scanning string is counted in the order of 4, 3, 2, and 1. If the count value is 1, the next stored control bit value is loaded.

3) Configuration counter: A counter that traces the current tab placement order. That is, starting from the initial value 1, the value of the pattern counter is increased by 1 each time the value passes by 1.

4) Decoder & Reconfigurable Phase Shifter (Decoder & Reconfigurable Phase Shifter): Configures a phase shifting network according to the value of the placement counter. The decoder determines the input signal of the XOR gate according to TapConn _i ^(j) , and the relocatable phase shifter receives the signal to form the actual phase shifter.

For example, in the configuration as described above, the decoder and the phase shifter repositionable for the scan sequence 1 may be configured as follows.

Decoder:

Input: 001 Output: 011

Input: 010 Output: 010

Input: 011 Output: 101

Input: 100 Output: 011

Input: 101 Output: 111 combinational logic

(Where type is output, the output value of TapConn _i ⁽¹⁾ corresponding to the position of one of UTCS ⁽¹⁾ of the batch counters)

Relocatable phase shifter:

The relocatable phase shifter is a network of XOR gates and is configured by UTCS ^(j) . For example, in the case of UTCS ⁽¹⁾ : {101001}, the position where 1 exists indicates the output position of the LFSR to be the input of the XOR gate. The output of the decoder is also the input of the XOR gate. The final output of the XOR tree is provided as a scan chain.

In general, in the case of logic BIST applying a deterministic test pattern, a deterministic test pattern is applied after applying some pseudorandom test pattern. In this case, both the pseudorandom BIST and the deterministic BIST must be equipped with hardware. Phase shifters are typically hardware used in almost all pseudorandom BISTs. Therefore, using phase shifters in deterministic BIST is an area efficient method because they share the same functional blocks. In addition, since the deterministic pattern generation hardware proposed in the present invention uses the window characteristics of the M sequence, unlike the conventional method, it is possible to generate all the deterministic test patterns regardless of the current LFSR pattern. Therefore, unlike the existing method, it is possible to generate the required pattern in a short time, and thus it is expected to greatly reduce the cost of the test.

Claims (5)

In the deterministic BIST test pattern generation device for a circuit having multiple scan chains, Control bit storage means for storing the number of deterministic test patterns covered by the tab arrangement, A pattern counter means for receiving the stored values of the control bit storage means one by one and counting backwards; A batch counter means for tracing the current tap arrangement order and incrementing by one each time the value of the pattern counter passes one, A decoder for constructing a phase shift network according to the value of the batch counter means and for determining an input signal of the XOR gate according to TapConn _i ^(j); An apparatus for generating a deterministic test pattern using a phase shifter, the phase shifter comprising a repositionable phase shifter that receives the signal and arranges an actual phase shifter. The apparatus of claim 1, wherein the phase shifter is synthesized by the following steps. A pattern request step of re-requesting deterministic test patterns by ATPG, Setting the number i of tab layouts to 1, A TapConn _i ^(j) initialization step that initializes TapConn _i ^(j) , the set with the possible number of phase shifts in the current step, where i is the number of batches and j is the number of scan sequences, Updating the TapTable, which is a table that stores the generation pattern related to the phase shift number in the current step, Checking whether the pattern of the TapTable matching the phase shift number of the current TapConn _i ^(j) is compatible with the test pattern of T _D , Removing the phase shift number that does not cover the current deterministic test pattern in TapConn _i ^(j) up to the previous step, Updating the UTCS ^(j) table, which is the result of bitwise ORing the tap positions corresponding to TapConn _i ^(j) obtained by the current step, for each scan string, where this step of updating UTCS ^(j) is performed on the current tab. Until there are no more deterministic test patterns that satisfy the batch, Removing the pattern already covered among the remaining deterministic test patterns before finishing the current tab placement process. The deterministic test pattern using a phase shifter according to claim 2, wherein the request order in the pattern requesting step is performed so that the order of the "don't-care value (x)" in one pattern comes first. Generating device. The method of claim 2, wherein in the TapConn _i ^(j) initialization step, TapConn _i ^(j) is a deterministic test pattern generating device using a phase shifter, characterized in that the n-step LFSR is initialized to a set of {1, 2, ...., 2 ⁿ -1}. The method of claim 2, wherein the updating of the TapTable, which is a table storing a generation pattern related to the phase shift number, The table is initially generated by a phase shifter generation algorithm using an existing simulation, and the table is updated whenever a deterministic test pattern is embedded with a relocatable phase shifter. Pattern generator.

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