KR100605605B1 - Semiconductor memory device with delay locked loop - Google Patents

Abstract

The present invention is to provide a semiconductor memory device having a delay fixed loop that can softly adjust the delay amount of the delay clock of the delay lock loop, the present invention is to provide a delay control signal in response to the test mode signal Delay amount control signal generation means for generating; And a delay locked loop for adjusting and outputting a delay amount of the output DLL delay signal according to the delay amount control signal.

Replica, Delayed Model, Phase Mixer, Test, Adjust

Description

Semiconductor memory device having a delay locked loop {SEMICONDUCTOR MEMORY DEVICE WITH DELAY LOCKED LOOP}             

1 is a block diagram of a register control delay lock loop of a DDR SDRAM according to the prior art.

2 is a block diagram of a DDR SDRAM having a test mode for adjusting a delay amount of a delay lock loop according to an embodiment of the present invention.

3 is an internal circuit diagram of an additional delay unit of FIG. 2;

4 is an internal circuit diagram of the clock inverter of FIG.

* Explanation of symbols for the main parts of the drawings

100: delay amount control signal generation unit

200: delay lock loop

240: additional delay unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a delay locked loop (DLL), and more particularly, a semiconductor memory having a delay locked loop having a test mode for adjusting a delay amount of a delay locked loop. It relates to an element.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) is caused by an internal circuit, and a delay locked loop is used to compensate for this time delay so that the internal clock has the same phase as the external clock. Is being used.

The delay between the output data and the external clock is called tAC. That is, it means a time difference between the time point at which the data is expected to be output and the time point at which the actual data is output.

On the other hand, delay locked loops have the advantage of being less affected by noise than conventional phase locked loops (PLL), which are widely used in synchronous semiconductor memories including DDR double data rate synchronous DRAM (SDRAM). Among them, a register controlled delay locked loop (register controlled DLL) is most commonly used.

1 is a block diagram of a register control delay lock loop of a DDR SDRAM according to the prior art (see Korean Patent Publication No. 10-2003-0002130).

Referring to FIG. 1, a delay locked loop according to the related art may include a first clock buffer for generating an internal clock fall_clk synchronized to a falling edge of an external clock clk using an inverted external clock / clk as an input. 11) a second clock buffer 12 for generating an internal clock rise_clk synchronized with the rising edge of the external clock clk with the external clock clk as an input, and a rising edge of the external clock clk. A clock divider 13 for dividing an internal clock (rise_clk) synchronized to 1 / n (n is a positive integer, typically n = 8) to output a delay monitoring clock (dly_in) and a reference clock (ref). And a first delay line 14 having an internal clock fall_clk synchronized to the falling edge of the external clock clk and an internal clock rise_clk synchronized to the rising edge of the external clock clk. The second delay line 15 to be input, the third delay line 16 to which the delay monitoring clock dly_in is input, and the first and second A shift register 17 for determining the delay amount of the three delay lines 14, 15, and 16, and a first for driving the output ifclk of the first delay line 14 to generate the DLL clock fclk_dll. The output of the second DLL driver 21 and the third delay line 16 for driving the DLL driver 20, the output irclk of the second delay line 15 to generate the DLL clock rclk_dll. A delay model 22 configured as an input such that the clock passes through the same delay condition as the actual clock path, and a phase comparator 19 for comparing the phase of the output fbclk and the reference clock ref of the delay model 22. And a shift controller 18 for outputting shift control signals SR and SL for controlling the shift direction of the shift register 17 in response to the control signal ctrl output from the phase comparator 19.

First, the first clock buffer 11 receives the falling edge of the external clock clk to generate a synchronized internal clock fall_clk, and the second clock buffer 12 receives the rising edge of the external clock clk and receives the internal clock. Generate a clock (rise_clk). The clock divider 13 divides the internal clock rise_clk synchronized to the rising edge of the external clock clk by 1 / n to generate a clock (ref, dly_in) that is synchronized with the external clock clk once every nth clock. . Since the reference clock ref and the delay monitoring clock dly_in are signals obtained by dividing the internal clock rise_clk synchronized to the rising edge of the external clock clk, the pulse width is equal to the period tCK of the external clock clk. Has The reference clock ref and the delay monitoring clock dly_in have opposite phases.

In the initial operation, the delay monitoring clock dly_in is output through only one unit delay element of the third delay line 16 of the delay monitor 10, which is delayed while passing through the delay model 22 and fed back. It is output by the clock fbclk. Here, the feedback clock fbclk is delayed by the delay time of the delay model 22 compared with the output clock of the third delay line 16.

Meanwhile, the phase comparator 19 compares the rising edge of the reference clock ref with the rising edge of the feedback clock fbclk to generate a control signal ctrl, and the shift controller 18 responds to the control signal ctrl. To output shift control signals SR and SL for controlling the shift direction of the shift register 17. The shift register 17 determines the delay amounts of the first, second and third delay lines 14, 15, and 16 in response to the shift control signals SR and SL. At this time, if a shift right (SR) is inputted, the register is moved to the right, and if a shift left (SL) is inputted, the register is moved to the left. Subsequently, the delay lock is performed at the moment when the two clocks have the minimum jitter while comparing the delayed-controlled feedback clock fbclk and the reference clock ref. In this case, the DLL clock (fclk_dll, rclk_dll has the same phase as the external clock clk output from the first and second DLL drivers 20 and 21.

The semiconductor memory device having a delay locked loop according to the related art is subjected to a decapsulation process of removing a package of a memory when analyzing the cause of the failure of the delay locked loop and delayed through a focused in beam (FIB). It is expensive and time-consuming to experiment with varying the delay of the model.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a semiconductor memory device having a delay locked loop that can softly adjust the delay amount of the delay clock of the delay locked loop. .

According to an aspect of the present invention, there is provided a semiconductor memory device comprising: delay amount control signal generation means for generating a delay amount control signal in response to a test mode signal; And a delay lock loop for adjusting and outputting a delay amount of the output DLL delay signal according to the delay amount control signal.

Preferably, the delay amount control signal generating means activates a corresponding signal by counting an active number of the test-pulse signal and a test-pulse signal generating unit generating a test-pulse signal proportional to the number of application of the test mode signal. And a decoding unit for decoding the output signal of the pulse-counting unit and activating the delay amount control signal corresponding to the corresponding number.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a block diagram of a DDR SDRAM having a test mode for adjusting a delay amount of a delay lock loop according to an embodiment of the present invention.

Referring to FIG. 2, a semiconductor memory device according to an embodiment of the present invention may include a delay amount control signal generator for generating a delay amount control signal sw <0: n> in response to a test mode signal tm_mrs. 100 and a delay locked loop 200 which adjusts and outputs a delay amount of the output DLL delay signals fclk_dll and rclk_dll according to the delay amount adjustment signals sw <0: n>.

In addition, the delay control signal generator 100 may generate a test-pulse signal tm_pls in proportion to the number of times the test mode signal tm_mrs is applied, and a test-pulse signal tm_pls. Pulse counting unit 140 for activating the corresponding signal by counting the number of times of active and the output signal (tm_dly <0: n>) of the pulse counting unit 140, And a decoding unit 160 for activating the delay amount control signals sw <0: n>.

Next, the operation of the delay control signal generator 100 will be described.

First, when the test mode signal tm_mrs is applied through the setting of the MRS (Mode Register Set), the test-pulse signal generation unit 120 has a test-pulse signal having a pulse corresponding to the number of times the test mode signal tm_mrs is applied. Create (tm_pls). That is, when the number of times the test mode signal tm_mrs is applied is twice, the test-pulse signal generator 120 outputs a test-pulse signal tm_pls having two pulses.

Subsequently, the pulse counting unit 140 counts a pulse of the test-pulse signal tm_pls and activates the corresponding output signal tm_dly <0: n>. As described above, the test-pulse signal tm_pls is In the case of two pulses, the output signal tm_dly <1> is activated. In addition, when the test-pulse signal tm_pls has four pulses, the output signal tm_dly <3> is activated.

Subsequently, the decoding unit 160 decodes the output signal tm_dly <0: n> to activate the corresponding delay amount control signals sw <0: n>. That is, when the output signal tm_dly <1> of the pulse counting unit 140 is activated, the decoding unit 160 activates the delay amount control signals sw <0: 1> corresponding to the corresponding number, and also counts the pulses. When the output signal tm_dly <3> of the unit 140 is activated, the decoding unit 160 activates the delay amount control signal sw <0: 3>.

Meanwhile, the delay locked loop 200 adjusts the delay amount of the replica-clock (clk_rpl) of the delay model 220 in response to the delay amount control signal sw <0: n> and outputs it to the feedback clock fbclk. It further comprises an additional delay unit 240 for.

The additional delay unit 240 is implemented as a phase mixer, which will be described in detail with reference to the accompanying drawings.

3 is an internal circuit diagram of the additional delay unit 240 of FIG. 2.

Referring to FIG. 3, the additional delay unit 240 adjusts the delay amount of the inverter chain 242 to delay the replica-clock clk_rpl, and the delay amount of the replica-clock clk_rpl and the delay amount control signal sw <0: n. > And the delay amount of the first delay unit 244 for adjusting and outputting the delay amount adjustment signal swb <0: n> and the inverter chain 242 output signal according to the inverse delay amount adjustment signal swb <0: n>. <0: n> and the second delay unit 246 and the first and second delay units 244 and 246 for adjusting and outputting the signal according to the inverted delay control signal sw <0: n>. The output node is a common output node, and includes an inverter I3 for inverting the signal clk_sum of the common output node and outputting the inverted signal to the feedback clock fbclk.

The first delay unit 244 is activated when the corresponding delay amount control signal sw <0: n> is activated, and a plurality of clock inverters INV_CLK_0, INV_CLK_1, ..., INV_CLK_N for inverting and outputting the replica-clock clk_rpl. The second delay unit 246 is activated when the corresponding delay amount control signal sw <0: n> is inactivated, and a plurality of clock inverters for inverting and outputting the output signal of the inverter chain 242 ( INV_CLK_N + 1, INV_CLK_N + 2, ..., INV_CLK_M).

As described above, the clock inverters INV_CLK_0, INV_CLK_1, ..., INV_CLK_N in the first delay unit 244 are in the second delay unit 246 when the corresponding delay amount control signals sw <0: n> are activated. Since the clock inverters INV_CLK_N + 1, INV_CLK_N + 2, ..., INV_CLK_M invert the output signals when the corresponding signals sw <0: n> are inactivated, the first and second delay units 244 and 246 are outputted. The total amount of delays is constant.

For reference, the inverted delay amount adjustment signals swb <0: n> are obtained by inverting the delay amount adjustment signals sw <0: n> through a plurality of inverters I4, I5, ..., I_M. It is a signal. In addition, the inverter chain 242 is implemented through two inverters I1 and I2 connected in series.

FIG. 4 is an internal circuit diagram of the clock inverter INV_CLK of FIG. 3.

Referring to FIG. 4, the clock inverter INV_CLK has an input signal IN as a gate input, a PMOS transistor PM1 having its source terminal connected to a power supply voltage VDD, and a gate input of an inverted selection signal SELB. NMOS having a PMOS transistor (PM2) having a source-drain path between the drain terminal and the output node of the PMOS transistor (PM1), the input signal (IN) as a gate input, and its source terminal connected to the power supply voltage VSS. A transistor NM2 and an NMOS transistor NM1 having a select signal SEL as its gate input and having a drain-source path between the drain terminal and the output node of the NMOS transistor NM2 are provided.

On the other hand, the first delay unit 244 delays the delay amount control signal sw with the selection signal SEL of each clock inverter, and the second delay unit 246 is the delay inverted with the selection signal SEL of each clock inverter. Since the amount control signal swb is applied, the clock inverter in the first delay unit 244, as described above, is activated in the second delay unit 246 when the delay amount control signal sw <0: n> is activated. The clock inverter is activated when the delay amount control signals sw <0: n> are deactivated.

2 to 4, the operation of the semiconductor memory device in the test mode for adjusting the delay amount of the DLL delay signals fclk_dll and rclk_dll of the delay locked loop according to an embodiment of the present invention will be described.

First, when the test mode signal tm_mrs is applied through the setting of the MRS, the delay amount control signal generation unit 100 has a number of delay amount control signals sw <0 proportional to the number of applied test mode signals tm_mrs. : n>)

Subsequently, the additional delay unit 240 adjusts the delay amount of the replica-clock clk_rpl, which is an output clock of the delay model 220 configured so that the clock passes through the same delay condition as the actual clock path, and delay delay control signal sw <0. Respond to: n>) and output to feedback-clock (fbclk).

That is, the clock inverters INV_CLK in the first and second delay units 244 and 246 are activated according to whether the corresponding delay amount control signals sw <0: n> are activated to delay and invert the input signal IN. The delay amount of the feedback clock clock fbclk is adjusted according to the number of active clock inverters INV_CLK. For example, when the delay amount adjustment signal sw <0: 1> is activated, the clock inverters INV_CLK_0 and INV_CLK_1 in the first delay unit 244 are activated, and the clock inverters INV_CLK_N + 3 in the second delay unit 246 are activated. INV_CLK_M is activated to invert and delay the input signal IN. As described above, since the driving force of the first and second delay units 244 and 246 varies according to the number of clock inverters active in the first and second delay units 244 and 246, the feedback clock fbclk has The amount of delay is different.

For reference, the input clock of the second delay unit 246 is the output clock of the inverter chain 242, and the two inverters I1, 1, compared to the replica-clock clk_rpl which is the input clock of the first delay unit 244. This signal is delayed by the delay amount of I2). Therefore, the first and second delay units 244 and 246 may adjust the amount of delay between the replica clock (clk_rpl) and the output clock of the inverter chain 242 by N equals through the internal clock inverter.

Using such a phase mixer, the DLL delay signals fclk_dll and rclk_dll of the delay locked loop 200 can be finely adjusted.

The semiconductor memory device having a delay locked loop according to the present invention includes a phase mixer implemented as an inverter capable of adjusting the driving force in the delay locked loop, and enters the test mode through the setting of the MRS to adjust the driving force of the inverter. In this case, the delay amount of the DLL delay signal, which is an output signal of the delay lock loop, is softly adjusted. Therefore, the de-encapsulation and FIB processes that are conventionally performed for the failure analysis of the delayed fixed loop are not required, thereby reducing test time and cost.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above includes a phase mixer implemented as an inverter capable of adjusting the driving force in the test mode in the delay lock loop, and softly adjusts the delay amount of the output signal of the delay lock loop, thereby causing time and You can save money.

Claims (12)

delete Delay amount adjustment signal generating means for generating a delay amount adjustment signal in response to the test mode signal; And And a delay locked loop for adjusting and outputting a delay amount of the output DLL delay signal according to the delay amount control signal. The delay amount control signal generating means, A test-pulse signal generator for generating a test-pulse signal proportional to the number of times of application of the test mode signal; A pulse-counting unit for counting the number of active times of the test-pulse signal to activate a corresponding signal; Decoding unit for decoding the output signal of the pulse-counting unit to activate the delay amount control signal of the corresponding number A semiconductor memory device comprising: a. The method of claim 2, The delay lock loop, And an additional delay unit configured to adjust a delay amount of the replica-clock of the delay model and output the feedback clock in response to the delay amount control signal. The method of claim 3, The additional delay unit, And a phase mixer implemented as an inverter capable of adjusting a driving force according to the delay amount control signal. The method of claim 4, wherein The additional delay unit, An inverter chain for delaying the replica clock; A first delay unit for adjusting and outputting the delay amount of the replica clock according to the delay amount control signal and the inverted delay amount control signal; A second delay unit for adjusting and outputting a delay amount of the inverter chain output signal according to the delay amount control signal and an inverted delay amount control signal; The output nodes of the first and second delay units are common output nodes, and an inverter for inverting a signal of the common output node and outputting the inverted signal to the feedback clock. A semiconductor memory device comprising: a. The method of claim 5, The first delay unit includes a plurality of clock inverters that are activated when the corresponding delay amount control signal is activated to invert and output the replica clock. And the second delay unit includes a plurality of clock inverters that are activated when the corresponding delay amount control signal is inactivated and inverts and outputs an output signal of the inverter chain. The method of claim 6, And the sum of the delay amounts of the first and second delay units is constant. The method of claim 7, wherein And the inverted delay amount control signal is a signal output by inverting the delay amount control signal through a plurality of inverters. The method of claim 8, The inverter chain is a semiconductor memory device, characterized in that implemented by two inverters connected in series. The method of claim 6, The clock inverter, A first PMOS transistor having an input signal as a gate input and having its source terminal connected to the first power supply voltage; A second PMOS transistor having an inverted selection signal as a gate input and having a source-drain path between a drain terminal and an output node of the first PMOS transistor; A first NMOS transistor having its input signal as a gate input and having its source terminal coupled to a second power supply voltage; And a second NMOS transistor having a selection signal as its gate input and having a drain-source path between the drain terminal of the first NMOS transistor and the output node. The method of claim 10, And a plurality of clock inverters in the first delay unit receive the delay amount control signal as a selection signal and the inverted delay amount control signal as an inverted selection signal. The method of claim 11, And a plurality of clock inverters in the second delay unit receive the inverted delay amount control signal as a selection signal and the delay amount control signal as the inverted selection signal.

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