KR100603593B1 - Ultra-low-power synchronized two-stage comparator for pwm controller - Google Patents

Abstract

The present invention relates to a comparator, and more particularly to an efficient super power comparator used as a tool of a PWM controller inside a DC-DC converter. A comparison circuit for receiving a reference signal and a sawtooth signal and outputting a PWM signal having a predetermined magnitude when the magnitude of the sawtooth signal is larger than the reference signal, wherein the sawtooth signal has the same period as the system clock; And a falling edge synchronization circuit configured to reset the PWM signal output of the comparison circuit in synchronization with the system clock. The ultra low power synchronous comparator according to the present invention can have a small comparison delay time by synchronizing the falling edge of the output waveform of the comparator to the system clock for high speed.

PWM controller, low power, synchronization, comparator

Description

Ultra-low-power synchronized two-stage comparator for PWM controller

1A shows a typical PWM controller.

1B shows an ideal PWM output signal by a typical PWM controller.

2 illustrates a conventional general CMOS voltage comparator.

3 illustrates a comparator including a falling edge synchronization circuit in accordance with a preferred embodiment of the present invention.

4A illustrates a comparison circuit in a comparator with reduced power consumption and fast delay time in accordance with one preferred embodiment of the present invention.

4B illustrates a comparator including a falling edge synchronization circuit in accordance with another preferred embodiment of the present invention.

FIG. 5 is a graph showing an input waveform and an output waveform of a PWM controller including the voltage comparator shown in FIG. 2. FIG.

6 is a graph showing an input waveform and an output waveform of a PWM controller including a comparator according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: comparator

200: differential circuit

300: differential amplification means 310: current mirror

350: comparison circuit

400: falling edge synchronization circuit

The present invention relates to a comparator, and more particularly, to an efficient ultra-power comparator used as a tool of a PWM (Pulse Width Modulation) controller in a DC-DC converter.

The design criteria for a comparator located inside a PWM controller are different from typical comparators. Typical comparator design criteria are ① low offset voltage, ② high resolution, ③ small delay time, and ④ steady-state stability. Generic comparators have to deal with all other situations. However, comparators used in PWM controllers have a formal input waveform. That is, since the waveform of the input signal is known, it is not necessary to follow all the design criteria of the general comparator described above.

An important requirement for PWM controllers in battery-powered systems is minimal power consumption. Recently, low-power PWM controllers for DC-DC converters have become important due to the increasing number of battery-powered portable systems. However, the design of the circuit becomes increasingly difficult because it requires high speed under the constraint of low power consumption. The most important aspect of the DC-DC converter is power conversion efficiency, where the power consumption of the PWM controller itself must be minimized. In contrast, the switching speed of current DC-DC converters is increasing. The implications of fast switching speeds first relate to switching noise in the signal processing band. By increasing the switching frequency, the switching noise leaves the high frequency out of the signal band. In addition, the second meaning is that the size of the inductor and capacitor outside the chip can be reduced, thereby making the portable device even smaller. However, in circuit design, speed and power are generally mutually constrained conditions.

Accordingly, to solve the above problem, an object of the present invention is to provide an ultra low power synchronized comparator for a PWM controller with a small comparison delay time by synchronizing the falling edge of the output waveform of the comparator to the system clock for high speed. .

Another object of the present invention is to provide an ultra low power synchronized comparator for a PWM controller that can minimize power consumption.

Another object of the present invention is to provide an ultra low power synchronous comparator for a PWM controller that can simplify the circuit design by synchronizing the falling edge of the output waveform of the comparator to the system clock.

To achieve the above objects, according to an aspect of the present invention, a comparison circuit for receiving a reference signal and a sawtooth signal and outputting a PWM signal having a predetermined size when the magnitude of the sawtooth signal is larger than the reference signal Wherein the sawtooth signal has the same period as the system clock; And a falling edge synchronization circuit configured to reset the PWM signal output of the comparison circuit in synchronization with the system clock.

Preferably, the comparison circuit comprises differential amplifying means for distributing and amplifying a bias current according to a difference between two signals input through a positive input terminal and a negative input terminal to generate an output current, and the bias current in the differential amplifying means. A current mirror OTA comprising a current mirror for supplying a; And a pull-up transistor for pulling up an output voltage according to the output current generated by the differential amplifying means, and a gate connected to the drain of a transistor connected to the positive input terminal of the differential amplifying means to push an output voltage. A class AB output unit including a push transistor may be included, and power consumption may be reduced by minimizing a standby current flowing through the pull-up transistor of the class AB output unit.

The falling edge synchronization circuit may include an inverter for inverting the input system clock; A first reset switch connected to an output terminal of the inverter and configured to turn off the pull-up transistor in synchronization with the inverted system clock; And a second reset switch connected to an output terminal of the inverter and configured to turn on the push transistor in synchronization with the inverted system clock.

Preferably, the transistor included in the comparator may be formed of a CMOS.

Other objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. Hereinafter, a preferred embodiment of an ultra low power synchronous comparator for a PWM controller according to the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the detailed description will be made based on a CMOS transistor, and the present invention may be applied to an NMOS, a PMOS transistor, or a JFET in addition to the CMOS. In addition, it is a matter of course that the configuration of the circuit consisting of the N-type transistor and the P-type transistor can be made by converting the P-type transistor and the N-type transistor symmetrical by those skilled in the art. The simulation of the drawings used in the following description is characterized in that it is performed by HSPICE simulation using CMOS 0.35㎛ process parameters, which of course does not limit the scope of rights.

FIG. 1A is a diagram illustrating a general PWM controller, and FIG. 1B is a diagram illustrating an ideal PWM output signal by a general PWM controller.

Referring to FIG. 1A, a PWM controller basically includes an error amplifier (not shown) for detecting and amplifying an error of an output voltage or a current, and a comparator for generating a pulse by comparing the detected error voltage with a saw tooth wave ( Comparator 100), and a driving circuit (not shown) for driving a switch of the DC-DC converter.

Briefly describing the operation of the PWM controller, the comparator 100 outputs only a portion having a higher potential than that of the sawtooth wave at the intersection portion compared with the sawtooth wave having a certain period according to the potential of the error voltage detected at the output of the error amplifier. This adjusts the width of the pulse under a certain period to adjust the output to match the reference voltage (Vc) of the desired error amplifier. In this case, the pulse width determines the size of the output. The principle is that the average output is obtained as the integral of the pulse width time and height (indicative of voltage) by the ratio of the pulse width and the rest time.

Here, the current source I1 charges the capacitor C1 with the slope I1 / C1 of the output voltage Vsaw (t). Whenever the system clock is high, the capacitor C1 is reset, so that the waveform is sawtooth wave Vsaw (t) = (I1 / C1) x t having the period Ts equal to the period of the system clock. Therefore, one of the input signals of the comparator 100 is always sawtooth wave Vsaw (t) as shown in FIG. The sawtooth wave Vsaw (t) is compared with the reference voltage Vc, which is another input signal of the comparator 100, determined by the duty ratio of the PWM output.

Vc is the reference voltage output from the error amplifier and determines the duty ratio of the PWM output. Referring to FIG. 1B, when the duty ratio is set to d (0 ≦ d ≦ 1), the case where Vsaw (t) has a value larger than Vc should be maintained by d × Ts of the clock period Ts. Therefore, Vc is adjusted so that Vsaw (t) can be larger than Vc after (1-d) x Ts after the reset.

FIG. 2 is a diagram illustrating a conventional general CMOS voltage comparator, and FIG. 5 is a graph illustrating an input waveform and an output waveform of a PWM controller including the voltage comparator shown in FIG. 2.

Referring to Fig. 2, transistors M201 to M204 constitute a differential circuit 200 used at the inlet side, transistor M207 is a common sourse amplifier stage for outputting an output signal, and transistors M205 to M206 are M201 to M204 and M207, respectively. It is responsible for supplying current using bias voltage.

Here, when the voltage of Vin- is greater than the voltage of Vin +, V _SG1 of M201 is smaller than V _SG2 of M202, so that drain current I _D1 of M201 is smaller than drain current I _D2 of M202. The smaller I _D1 lowers the voltage between the gate and source of M203, and at the same time the voltage between the gate and source of M204. At this time, since I _D2 is increased, the drain voltage of M204 increases. Thus, the voltage between the gate and the source of M207 increases. This increases the drain current of M207, causing the output voltage Vout to go low. Of course, if the voltage of Vin + is greater than the voltage of Vin-, the same principle causes the output voltage Vout to go high.

Referring to FIG. 5, a sawtooth wave signal having the same period as the system clock is input to the Vin + terminal of the comparator, and a reference signal having a size of 1.8V for outputting a predetermined PWM signal is input to the Vin− terminal. In the periods P1 to P2 of FIG. 5, the amplitude of the sawtooth signal is greater than that of the reference signal, and the PWM signal is output in the periods P3 to P4. Here, the time interval between P1 and P3 is the rising delay time of the PWM signal, and the time interval between P2 and P4 is the falling delay time of the PWM signal.

The PWM output of the comparator is quite different from the ideal PWM output waveform shown in FIG. The input sawtooth waveform with a frequency of 2Mhz is high for low power operation, which makes the latency noticeable on both the rising and falling edges of the comparator's PWM output waveform.

The general comparator shown in FIG. 2 requires significant power to operate at high speed. This is because the bias voltage Vb must always be supplied to two transistors, M205 and M206. However, when designing a comparator for a PWM controller, the controller's power dissipation must be minimized to maximize power conversion efficiency. The general comparator shown in FIG. 2 has been commonly selected for the PWM controller. However, as mentioned above, the general design criteria are not suitable for comparators that need to be located inside the PWM controller.

The PWM controller can predict the fall time of the PWM output waveform. The falling time of the PWM output waveform in the comparator located inside the PWM controller from FIG. 1b indicates that the timing of the falling edge of the sawtooth wave must also be periodic, depending on the system clock period. Therefore, accurate detection of the falling edge of the sawtooth wave can simplify the design of the comparator, which can synchronize the output signal of the comparator to the system clock instead of detecting the falling edge.

3 illustrates a comparator including a falling edge synchronization circuit according to an exemplary embodiment of the present invention. Referring to FIG. 3, when the system clock signal passes through the inverter to become the gate voltage of the transistor M211, and the M211 is a P-type transistor, the gate voltage of the M211 becomes low by the inverter when the system clock signal is momentarily high. M211 is turned on, and the gate voltage of M207 becomes (VDD-V _SD211 ). That is, the gate voltage of M207 rises with the cycle of the system clock, the drain current of M207 rises, and the output voltage Vout decreases momentarily, resulting in a reset effect. In other words, the reset of the output voltage Vout is synchronized to the system clock.

The falling delay time of the comparator can be minimized by using the synchronization method to the system clock described above, and a comparison circuit that can minimize the rising delay time of the comparator will be described later in detail.

4A is a diagram illustrating a comparison circuit in a comparator having a low power consumption and a fast delay time according to an exemplary embodiment of the present invention, and FIG. 4B is a comparator including a falling edge synchronization circuit according to another preferred embodiment of the present invention. Figure is a diagram.

Referring to FIG. 4A, the comparison circuit 350 includes a differential amplifying means 300, a current mirror 310, and a common source amplifier (AB class output unit).

The differential amplification means 300 receives a reference signal and a sawtooth signal through a positive input terminal and a negative input terminal, and outputs a bias current supplied through the current mirror 310 according to the difference between the two signals, and the drain current of the M402 and the M403, respectively. Amplify by dividing by the drain current. The voltage corresponding to the difference between the amplified drain current of M409 and the drain current of M407 is the gate voltage of M412. The current mirror 310 supplies a predetermined current to the differential amplifying means 300 by using the bias voltage, and M401 plays this role.

The common source amplifier (AB class output unit) includes a pull-up transistor M412 which pulls up the output voltage according to the magnitude of the gate voltage of the M412 generated through the differential amplifying means 300, and the gate is differential amplifying means 300. It includes a push transistor M413 is connected to the drain of the transistor M402 connected to the positive input terminal of the terminal to push the output voltage. The power consumption can be reduced by minimizing the quiescent current I _D412 flowing through the pull-up transistor M412 of the class AB output.

The first stage of the comparison circuit 350 shown in FIG. 4A takes a general current mirror OTA scheme. OTA is an operational transconductance amplifier, a circuit that generates an output current based on the difference between two input voltages. The input stage of the OTA includes a differential amplification means 300 and a current mirror 310. The current mirror 310 includes a transistor M401 serving as a current source by a DC bias voltage, the differential amplifying means 300 includes transistors M402 and M403 for receiving differential voltages Vin + and Vin-, and transistors M404 for output current amplification. To M409.

The principle of differential amplification is as follows. Vin + input is in is larger than Vin- input voltage between the source and the gate of the P-type transistor M402 V _SG402 is less than the voltage of V _SG403 between the source of the P-type transistor M403 and a gate, the drain current of the M402 is M403 It has a smaller value than the drain current. Since the drain current of M403 has a large value, the voltage V _SG405 between the gate and the source of M405 increases, and at this time, the voltage V _SG407 between the gate and the source of _M407 also increases. In addition, since the drain current of M402 has a small value, the voltage between the gate and source of M404, M406, M408, and M409 decreases in series. Therefore, the drain voltage of M407 and the drain voltage of M409 decrease.

The second stage of the comparison circuit 350 is composed of a pull-up transistor M412 and a push transistor M413. Since the drain voltage of M409 is reduced, the gate voltage of M412 is lowered, V _{SG412 which} is the source-gate voltage of M412 is gradually increased, so that the drain current I _D412 of M412 is also increased, and the output voltage Vout is raised.

The second stage of the comparison circuit 350 shown in FIG. 4A is similar to a typical two stage comparator using a common source amplifier in which the M412 is not operated by a DC bias voltage and has a current source as a load. When the M412 is operated by DC bias voltage, it is a typical two-stage comparator, and the overall structure is the same as that of a general comparator except for the first push-pull type. However, the problem of the second stage in general is that the current consumption is large because the current source load is always turned on by the DC bias voltage. A typical two stage comparator designed to minimize power dissipation in the PWM controller is around 800nA. Thus, in order to avoid leakage of inactive current, the second stage current I _D412 is controlled by the comparison circuit 350 shown in FIG. 4A. Here, M412 and M413 operate in class AB output stage. When the rise delay time of the PWM signal is measured using the comparison circuit 350, the delay time at the rising edge is much improved by displaying a delay time of several ns compared with the delay time of several tens ns in the comparator shown in FIG. Shows a decrease.

In examining the delay time at the falling edge, the maximum current supplied by M413 is given by Equation (1).

- 수학식 (1)

Equation (1)

Therefore, the maximum current supplied is limited, and the falling speed of the output signal of the comparison circuit 350 is also limited. However, since the falling delay time of the output signal of the comparator is synchronized with the system clock as described above with reference to FIG. 3, the operating speed of the M413 is not important in the system design. However, the pull-up behavior of the M412 is important for accurate operation and high speed of the comparator. Unlike the M413, the pull-up transistor M412 must have a wide swing width at the gate, which requires greater drive capability.

Referring to FIG. 4B, the synchronous comparator further includes a falling edge synchronization circuit 400 in the comparison circuit 350 shown in FIG. 4A.

The falling edge synchronization circuit 400 includes an inverter for inverting an input system clock, a first reset transistor M410 having a gate connected to an output terminal of the inverter, a source connected to a supply voltage VDD, and a drain connected to a gate of a pull-up transistor M412. And a second reset transistor M411 connected to the output terminal of the inverter, a source connected to a supply voltage VDD, and a drain connected to the gate of the push transistor M413. The first reset transistor M410 and the second reset transistor M411 may reset the PWM signal in synchronization with the system clock.

The falling edge synchronization circuit 400 is input to the gates of the P-type transistors M410 and M411 after the input of the system clock having the same period as the sawtooth wave coming into the Vin + input passes through the inverter as described above. When the system clock is instantaneously high, the gate voltages of M410 and M411 are low by the inverter, the M410 and M411 are turned on, and the gate voltage of M413 momentarily rises to turn on M413. Therefore, the turn-on of the push transistor reduces the output voltage Vout, which is very fast in proportion to the gate voltage of M413.

That is, the addition of M410 and M411 serving as a reset switch makes reset signal control possible by making the reset of the sawtooth wave shown in FIG. 1 and the reset of the PWM output waveform shown in FIG. 4B the same as the reset signal of the clock waveform. do. Therefore, the comparator according to the preferred embodiment of the present invention does not detect the negative slope of the input signal waveform but merely detects the positive slope of the input. Therefore, the speed of the M413 becomes insignificant and the size of the M413 can be reduced as much as possible. Even with very low current, the comparison speed of the new comparator is fast as shown in FIG.

6 is a graph illustrating an input waveform and an output waveform of a PWM controller including a comparator according to an exemplary embodiment of the present invention. 6, the output waveform of the comparator according to one preferred embodiment of the present invention is similar to the ideal PWM output. In addition, to maximize the power efficiency of the comparator, the inactive current is designed to be much smaller than 400 nA. The same system clock synchronizes the falling edge of the sawtooth wave and the falling edge of the PWM output waveform, minimizing the falling delay time (the time difference between P6 and P8). The rising edge represents a few ns, which is a much smaller delay time (time difference between P5 and P7) than a conventional comparator (see FIG. 5, about tens of ns).

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention. In addition, the scope of the present invention can be interpreted only by the claims described below.

As described above, the ultra low power synchronous comparator for the PWM controller according to the present invention can have a small comparison delay time by synchronizing the falling edge of the output waveform of the comparator to the system clock for high speed.

It also minimizes power consumption and simplifies circuit design by synchronizing the falling edge of the comparator's output waveform to the system clock.

Claims (4)

For ultra low power synchronous comparators for PWM controllers, A comparison circuit for receiving a reference signal and a sawtooth signal and outputting a PWM signal having a predetermined magnitude when the magnitude of the sawtooth signal is larger than the reference signal, wherein the sawtooth signal has the same period as the system clock; ; And And a falling edge synchronization circuit configured to reset the PWM signal output of the comparison circuit in synchronization with the system clock. The method of claim 1, wherein the comparison circuit, Differential amplifying means for generating an output current by distributing and amplifying a bias current according to a difference between two signals input through a positive input terminal and a negative input terminal; A current mirror OTA including a current mirror for supplying the bias current to the differential amplifying means; And A pull-up transistor for pulling up an output voltage according to the output current generated by the differential amplifying means; A gate is connected to the drain of the transistor connected to the positive input terminal of the differential amplification means and includes a class AB output including a push transistor for pushing an output voltage, An ultra low power synchronous comparator for a PWM controller, characterized in that the power consumption is reduced by minimizing the quiescent current flowing through the pull-up transistor. The method of claim 2, The falling edge synchronization circuit, An inverter for inverting the input system clock; A first reset switch connected to an output terminal of the inverter and configured to turn off the pull-up transistor in synchronization with the inverted system clock; And And a gate coupled to the output of the inverter, the second reset switch being synchronized with the inverted system clock to turn on the push transistor. The method according to claim 2 or 3, And a transistor included in the ultra low power synchronous comparator. The ultra low power synchronous comparator for the PWM controller.

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