KR100602646B1 - Method for processing interfacing malfunction of network processor - Google Patents

Abstract

The present invention relates to a method for handling interfacing malfunctions in a network processor which guarantees stable operation even in the case of packet block loss or status report loss due to abnormal operation of network processor interface hardware providing a network processor interface. A first step of initializing an internal global variable to a specific value when receiving a start packet reception message; A second step of, when the network processor receives the SOP packet block from the physical layer, performs an EOP loss check to process the SOP packet block; A third step of, when the network processor receives the MOP packet block from the physical layer, performs a SOP loss check to process the MOP packet block; And a fourth step of, when the network processor receives the EOP packet block from the physical layer, performs an SOP loss check to process the EOP packet block.

Network Processor, Split Processing, Abnormal Behavior, Interface

Description

{Method for processing interfacing malfunction of network processor}             

1 is a configuration diagram of a switch / router equipped with a network processor to which the present invention is applied;

2 is a conceptual diagram of packet division used in the present invention;

3 is a flowchart of an interfacing malfunction processing method in a network processor according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: physical layer 101: physical layer interface

102: network processor for packet processing 103: network processor for traffic management

104: switch interface 105: switch fabric

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet processing method of a network processor. In particular, the present invention relates to an interfacing malfunction processing of a network processor that guarantees stable operation even when packet block loss or status report is lost due to abnormal operation of a network processor interface hardware providing a network processor interface. It is about a method.

Today's dramatic increase in network traffic is due to the popularity of the Internet, the increasing need for remote access of information, and emerging applications. Even on the Internet alone, the explosive growth of electronic commerce can sometimes put an unsupportable load on the network backbone.

It is also the only one as the most important factor that caused the increase in data traffic volume to exceed voice traffic for the first time. The growing demand for remote access applications, including e-mail, database access, and file transfer, is putting more pressure on the network.

Eliminating network bottlenecks continues to be a top priority for service providers. Routers are often the cause of these bottlenecks. However, general network congestion is often misdiagnosed as a bandwidth problem and is solved by finding a solution with a wider bandwidth.

Today, manufacturers are realizing the difficulty of doing this. Manufacturers are turning to network processor technologies to manage bandwidth resources more efficiently, providing wire-speed, advanced data services commonly found in routers and network application servers. Such services include load balancing, QoS, gateways, firewalls, security, and web caching.

For remote access applications, the top priority is performance, bandwidth-on-demand, security, and authentication. The need for integration of QoS and Class of Service (CoS), integrated voice processing, and more sophisticated security solutions will also determine the design of future remote access network switches. In addition, in a remote connection, you will have to go through an increasing number of physical media such as ISDN, T1, E1, OC-3 through OC-48, cable and xDSL modems.

Industry consultants define a network processor (also referred to herein as a 'NP') as a programmable communication integrated circuit capable of performing one or more of the following functions.

Packet classification-identifies a packet based on known characteristics such as address or protocol.

Packet modification--Modify the packet to conform to IP, ATM, or other protocols (e.g., update the time-to-live field in the header of the IP).

Queue / policy management-Reflects the design strategy for packet queuing, de-queuing and scheduling of packets for specific applications.

Packet forwarding-Sending and receiving data on the switch fabric, and packet forwarding or routing to the appropriate address.

Although this definition accurately describes the basic features of early NPs, not all of the NP's potential features and benefits have yet been realized. Network processors can increase networking bandwidth and eliminate latency issues in a wide range of applications by allowing networking tasks that were previously processed in software to be executed in hardware.

In addition, NP can provide speed improvements through architectures such as parallel distributed processing design and pipeline processing design. These features can enable efficient search engines, improve throughput, and provide fast execution of complex tasks.

The network processor is expected to be the basic network building block for the network in the same way that the CPU and PC are. Representative functions provided by NP include real time processing, security, storage and forwarding, switch fabric interface, and IP packet processing and learning functions. NP is designed to optimize network related tasks, targeting ISO second to fifth layers.

On the other hand, when looking at the external interface of the network processor, it can interface with the data link layer / physical layer, and also with the network processor that performs other auxiliary functions, and interfaces with the switch fabric to handle packet transmission and reception.

It is also easier to process fixed length packets than to process variable length packets upon packet reception.

Fixed-length packets, such as ATM cells, can predict the propagation time through the switch, so it is easy to set up packets to pass through the switch one by one, such as through a pipeline, and the packets can be placed between adjacent packets. It is passed over a single data path in series with no gaps.

On the other hand, variable-length packets vary in processing time through switches, physical layer devices, and other network processors, and because the processing time for previous packets is not known in advance, the time of a particular event, such as packet retrieval and data arbitration scheduling. It is difficult to determine appropriately.

Thus, packets of variable length are divided into fixed-length blocks and transmitted to the switch fabric and other network processors in time.

On upstream, the packet is divided into blocks, and it is recombined downstream. Each block maintains a sequence between the hardware that interfaces with the network processor.

Data link layer / physical layer hardware interfaced with a network processor is divided into a packet or transmitted to a line processor, such as an ATM method, has been made of a fixed length of cells from the line end.

In addition, NPForum has established a protocol that defines how variable-length packets are divided into fixed-length packets and transmitted through a standard called Network Processing Forum Streaming Interface (NPSI), which interfaces with network processors and switch fabrics. Is recommended.

It also describes how to send and receive packets to and from the network processor that handles the network processor and its supporting tasks (forwarding table lookup, security, traffic engineering, and QoS).

Meanwhile, a part related to packet transmission and reception among software modules operating on a network processor operates in close association with hardware operation. In this operation, a packet is divided into several blocks, packet block recognition, packet block state, and packet block transmission and reception protocol.

If the network processor interface hardware and the internal software module of the network processor operate normally, there is no problem, but software malfunction may occur due to missing error reporting due to abnormal operation of the network processor interface hardware protocol. For example, after receiving the first block of a packet (SOP) and receiving the last block (EOP) of the packet, the internal software may not wait for the EOP and perform other processing. do. Alternatively, the SOP may not receive the SOP and may receive a middle block (MOP) or an EOP of the packet. In all these cases, there is a problem that causes a malfunction of the software.

Accordingly, the present invention has been made to solve the above problems, and the present invention provides a network processor capable of guaranteeing stable operation of the internal software of the network processor even if packet block loss or status report is lost due to abnormal operation of the network processor interface hardware. It is an object of the present invention to provide a method for handling interfacing malfunctions.

The present invention for achieving the above object is a first step of initializing the internal global variable to a specific value when the network processor receives the start packet reception message from the physical layer; A second step of, when the network processor receives the SOP packet block from the physical layer, performs an EOP loss check to process the SOP packet block; A third step of, when the network processor receives the MOP packet block from the physical layer, performs a SOP loss check to process the MOP packet block; And a fourth step of processing the EOP packet block by performing an SOP loss check when the network processor receives the EOP packet block from the physical layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a configuration diagram of a switch / router equipped with a network processor to which the present invention is applied.

Referring to FIG. 1, a switch / router equipped with a network processor to which the present invention is applied may include a physical layer 100, a physical layer interface 101, a packet processing network processor 102, and a traffic management network processor 103. And a switch interface 104 and a switch fabric 105.

The physical layer interface 101 includes a gigabit Ethernet media access control (MAC), a POS framer, and an ATM framer because a packet processing network processor 102 is located between the physical layer 100 and the switch fabric 105. It is responsible for the interfacing function for connecting to various physical layers 100, such as).

The packet processing network processor 102 is in charge of general packet processing, and after the packet entering the packet processing network processor 102 through the physical layer interface 101 is separated into a header and data, Therefore, the processing procedure will be different.

The traffic management network processor 103 is in charge of ancillary processing such as forwarding table lookup, security, traffic engineering, and QoS, and basically the header and data stored in the packet memory (not shown) are used for the traffic management network processor 103. By referring to the forwarding table memory (not shown), the output port is determined and output to the corresponding port, or packets not included in the forwarding table are discarded or processed by policy decision. In the case of general best effort processing, there may be no network processor 103 for traffic management.

The switch interface 104 also provides for matching of the network processors 102 and 103 to the switch fabric 104.

As such, the portion that interfaces with the packet processing network processor 102 includes an NP-PHY mode for interfacing with the physical layer 100 by the physical layer interface 101, a packet processing network processor 103, and traffic management. The NP-NP mode interfaces with the network processor 103 and the NP-SW mode interfaces with the network processors 102 and 103 and the switch fabric 105 by the switch interface 104.

The packet 201 received from the packet processing network processor 102 is divided into several blocks and processed as shown in FIG. 2. The start block 202 of the packet, the intermediate blocks 203a, 203b, and 203c of the packet, and the packet Consists of the last block 204.

Network processor for packet processing in spite of malfunctions during long periods of use on hardware protocols, missing status reports for blocks 202-204 or abnormal block loss during packet reception on various modes of interfacing with packet processing network processor 102 Stable operation of 102 is required.

Hereinafter, an operation of a switch / router equipped with a network processor according to an interfacing malfunction processing method of a network processor according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

The following embodiment is based on the example of the interface between the network processor 102 for packet processing in the NP-PHY mode and the Ethernet MAC controller as an example of the physical layer 100, but the same in the NP-NP mode and NP-SW mode It works.

When the packet processing network processor 102 reports that the packet start block is received from the Ethernet MAC controller 100, it initializes the sop_flag to a specific value.

When receiving the SOP packet block, the packet processing network processor 102 compares the same with a specific value, receives and processes the same, and changes sop_flag to an internal thread ID to indicate that the reception of the SOP packet is completed.

Of course, the packet processing network processor 102 determines that the SOP packet block has already been received if the received SOP packet block is different from a specific value, and thus performs EOP loss processing and waits to receive the next packet.

On the other hand, when the packet processing network processor 102 receives the MOP packet block, it compares whether the sop_flag value is equal to a specific value, and if it has a different value, the SOP packet block is already received and normal processing is performed. Process.

Of course, if the sop_flag value of the MOP packet block is equal to the specified value, the packet processing network processor 102 does not receive the SOP packet block and waits to receive the next packet after performing the SOP loss process.

On the other hand, when the packet processing network processor 102 receives the EOP packet block, it compares whether the sop_flag value is equal to a specific value, and if the packet processor has a different value, the SOP packet block is already received and normal processing is performed. Process.

Of course, if the sop_flag value is the same as the specific value upon receiving the EOP packet block, the packet processing network processor 102 does not receive the SOP packet block and waits to receive the next packet after performing the SOP loss process.

3 is a flowchart illustrating an interfacing malfunction processing method in a network processor according to an exemplary embodiment of the present invention.

In the network processor according to an exemplary embodiment of the present invention, an interfacing malfunction processing method includes a process of processing a packet reception start message (S301, S302), and a process of processing a packet block (S303 to S311).

The packet block processing steps S303 to S311 further include received packet determination steps S303 and S304, EOP loss check steps S305, S308 and S311, and SOP loss check steps S306 to S310.

In the process of processing a packet reception start message, the packet processing network processor first receives a reception message of a start packet block from an Ethernet MAC controller, for example, from the network processor interface hardware (S301).

Then, the packet processing network processor initializes the internal global variable sop_flag to a specific value, for example, OxFFFF. At this time, the specific value may be arbitrarily assigned, but it should not be a thread ID value operating in the internal engine (S302).

In the receiving packet determination step, when the packet processing network processor receives a block of packets from the network interface hardware (S303), if it is abnormal after checking the status of the received block, the processing returns to the initial state again after performing abnormal processing. It is determined in which position the received packet belongs (S304).

As a result, if the SOP block, the EOP loss check process is performed. The process starts by comparing whether the internal global variable sop_flag is equal to a specific value (S305).

As a result of the comparison, the internal global variable is changed to the internal thread ID to indicate that the SOP block is received (S306), and the SOP process is performed (S311).

As a result of the comparison, if the EOP block is not equal, the process for receiving the next packet is performed after performing the EOP loss processing.

On the other hand, if the MOP block and the EOP block performs the SOP loss check process, the process begins by comparing whether the internal global variable (sop_flag) is equal to a specific value (S306, 307).

If the internal global variable is not equal to a specific value in the case of a MOP block, MOP block packet processing is performed because the SOP block has already been received (S309), otherwise, after the SOP loss processing is performed because the SOP block is not received. Proceed to the process for receiving the next packet.

In the case of the EOP block, if the internal global variable is not equal to a specific value, the SOP block has already been received, and thus the EOP block packet processing is performed (S310). Otherwise, the SOP loss processing is performed because the SOP block has not been received. After that, the process proceeds to receiving the next packet.

Although described in detail with respect to preferred embodiments of the present invention, those skilled in the art to which the present invention pertains, the present invention without departing from the spirit and scope of the invention defined in the appended claims It will be appreciated that various modifications or changes can be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

According to the present invention as described above, there is an effect of ensuring a stable operation of the network processor even in the abnormal operation that occurs in the process of receiving a packet block between the hardware and the network processor to interface with the network processor.

Claims (5)

In the interfacing malfunction processing method of the network processor, When the network processor receives a Start of Packet (SOP) block, initializing an internal global variable of the network processor to a predetermined flag value; When the network processor receives the SOP block and the internal global variable value is equal to the flag value, replacing the value of the internal global variable with a thread ID value and processing the SOP block; And When the network processor receives a middle of packet (MOP) block or an end of packet (EOP) block and the internal global variable value is different from the flag value, interfacing to the MOP block or EOP block. How to handle malfunctions. The method of claim 1, The flag value is, Interfacing malfunction processing method characterized by having a value other than the internal thread ID value. The method according to claim 1 or 2, And when the network processor receives the SOP block and the internal global variable value is different from the flag value, performing an EOP loss processing. The method according to claim 1 or 2, And receiving, by the network processor, a middle of packet (MOP) or end of packet (EOP) block, and performing an SOP loss process when the internal global variable value is the same as the flag value. How to handle interfacing malfunctions. The method according to claim 1 or 2, And performing an abnormal process when the packet block received by the network processor is abnormal, and then checking whether the packet block belongs to any one of an SOP, a MOP, and an EOP.

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