KR100600885B1 - Organic Electro Luminescence Device for having the time-control buffer - Google Patents

Abstract

An organic light emitting display device including a time adjusting buffer unit for adjusting a delay time of a signal is disclosed. By adjusting the rise time and fall time of the data signal input to the panel portion, the reception characteristics of the data driver having a large variation in characteristics are optimized.

Description

Organic electroluminescent device having a time control buffer unit {Organic Electro Luminescence Device for having the time-control buffer}             

1 is a block diagram schematically illustrating an organic light emitting device according to the related art.

2 is a block diagram schematically illustrating an organic light emitting display device according to a preferred embodiment of the present invention.

3A and 3B are circuit diagrams and timing diagrams illustrating a timing controller of an organic light emitting device according to an exemplary embodiment of the present invention.

4A and 4B are other circuit diagrams and timing diagrams illustrating a timing controller of an organic light emitting device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: central processing control unit 210: memory unit

220: time control buffer unit 230: panel unit

240: power supply

The present invention relates to an organic EL driver circuit, and more particularly, to a circuit for controlling timing of a drive signal input to a data driver of a panel.

The organic EL is a self-luminous element that emits itself by inputting a data signal to a pixel selected by a scan drive without implementing color by an external light source. That is, a selection signal must be input to the organic EL to implement an image, and a data signal must be input to implement a predetermined color and brightness to a specific pixel selected by the selection signal.

1 is a block diagram schematically illustrating an organic light emitting device according to the related art.

Referring to FIG. 1, the organic light emitting device includes a program unit (FPGA: 100), a memory unit (SSRAM / ROM: 110), a buffer unit (Buffer: 120), a panel unit (Panel: 130), and a power unit (Power: 140). ).

The memory unit 110 stores and outputs a data signal according to the implanted program logic of the program unit 100. That is, the data signal stored at a predetermined address by the command signal and the address signal applied from the program unit 100 is output to the program unit 100.

Next, the program unit 100 receiving the data signal from the memory unit 110 applies a command signal and an address signal to the memory unit 110. That is, the address of the memory unit 110 is designated according to the input command signal and address signal, and the data signal corresponding to the address is a program signal and a selection signal according to the implanted program logic of the program unit 100. Is converted to and transferred to the buffer unit 120.

The buffer unit 120 receives the program signal and the selection signal, which are signals output from the program unit 100, and buffers them. The buffer unit 120 delays the output of the program unit 100 for a predetermined time, and outputs the same waveform or inverted waveform as the output signal. In addition, it plays a role of preventing a decrease in transmission efficiency due to impedance loading generated during signal transmission. That is, the buffer unit 120 having an input impedance of infinite in the transmission path of the signal prevents distortion of the signal due to the impedance of the transmission line. In addition, the buffer unit 120 serves as a voltage control voltage source having an output impedance of 0, thereby minimizing the influence of the impedance of the transmission line of the output terminal.

The panel unit 130 receives and displays the program signal and the selection signal output from the buffer unit 120. Typically, the panel unit 130 has a structure in which a plurality of pixels are arranged in a matrix form. In addition, in order to display an image through the pixels, a selection signal for selecting a specific pixel and a program signal for expressing gray scales to the selected pixel must be input. Therefore, in order for the selection signal and the data signal to be input to the pixels, the panel unit in which a plurality of pixels are arranged in a matrix must include a data driver and a scan driver.

The power supply unit 140 receives external power input through an adapter (not shown) to generate power voltages required for operation of the plurality of circuit units.

In recent years, as the manufacturing method of the organic EL is developed, SOP (System On Panel), which is a technology of integrating the data driver and the scan driver into the panel 130, has been adopted.

Problems related to the conventional organic EL device related to the present invention and overcome by the present invention are as follows.

In the organic light emitting device, the data driver is very sensitive to an input signal. That is, since the data driver is directly formed in the panel unit, its characteristics are not constant for each manufactured product. The output signal of the circuit part manufactured and mounted in the form of a semiconductor chip has a constant characteristic regardless of the manufactured product, whereas the data driver receiving the output signal has a sensitive sensitivity change.

Therefore, the organic electroluminescent device must be provided with a buffer control unit so that the output signal of the circuit unit can be adjusted so that the change in the characteristics of the data driver due to the variation of the organic EL manufacturing process is minimized.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting device having a time adjusting buffer unit for adjusting a delay time of an output signal of a corresponding circuit unit in the organic light emitting device.

      The present invention for achieving the above object, a plurality of data lines arranged in the first direction and transmitting a data signal; A plurality of selection scan lines arranged in a second direction and transferring a selection signal; And a plurality of unit pixels connected to the data line and the selection scan line.

     A central processing control unit for generating the data signal; A time adjusting buffer unit for receiving an output of the central processing control unit and outputting a data signal in which rising and falling times are adjusted; A data driver to apply the data signals to the plurality of data lines; a scan driver to apply the selection signals to the plurality of selection scan lines; And a plurality of organic light emitting diodes emitting light corresponding to data currents or data voltages applied to the unit pixels.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating an organic light emitting display device according to a preferred embodiment of the present invention.

Referring to FIG. 2, the organic light emitting device includes a central processing unit 200, a memory unit 210, a time adjusting buffer unit 220, a panel unit 230, and a power supply unit 240.

The memory unit 210 stores and outputs a data signal under the control of the central processing unit 200. That is, the data signal stored at the predetermined address by the command signal and the address signal applied from the central processing control unit 200 is output to the central processing control unit 200.

Next, the central processing control unit 200 receiving the data signal from the memory unit 210 applies a command signal and an address signal to the memory unit 210. That is, the address of the memory unit 210 is designated according to the input command signal and the address signal, and the data signal corresponding to the address is time-controlled buffer unit 220 under the control of the central processing unit 200. Is passed on.

The time adjustment buffer unit 220 receives the data signal output from the central processing unit 200 and buffers it. In addition, timing adjustment is performed to adjust a delay time and a rise time with respect to the output data signal. The time adjustment buffer unit 220 delays the output of the central processing unit 200 for a predetermined time, and outputs the same or inverted waveform as the output signal. In addition, it plays a role of preventing a decrease in transmission efficiency due to impedance loading generated during signal transmission. That is, the time adjusting buffer unit 220 having an input impedance of infinite in the transmission path of the signal prevents distortion of the signal due to the impedance of the transmission line. In addition, the time adjustment buffer unit 220 performs timing adjustment on the output signal of the built-in buffer. That is, the operation of the data driver of the panel unit which reacts sensitively according to the data signal is maximized, and the operation state of the data driver is stabilized.

The panel unit 230 receives and displays a data signal that is an output signal of the time adjustment buffer unit 220. The panel unit 230 has a structure in which a plurality of pixels are arranged in a matrix form. In addition, in order to display an image through the pixels, a selection signal for selecting a specific pixel and a data signal for expressing a gray level are input to the selected pixel. Accordingly, in order for the selection signal and the data signal to be input to the pixels, the panel unit in which a plurality of pixels are arranged in a matrix form includes a data driver and a scan driver. That is, the panel unit 230 is a system on panel (SOP) type in which the data driver and the scan driver are implemented as integrated circuits inside the panel.

The power supply 240 receives external power input through an adapter (not shown) to generate power voltages required for the operation of the plurality of circuit parts.

3A and 3B are circuit diagrams and timing diagrams illustrating a timing controller of an organic light emitting device according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, the time control buffer unit of the organic light emitting device includes a non-inverting amplifier 300 and a timing control circuit 310.

Since the voltage gain of the non-inverting amplifier 300 is 1, the non-inverting amplifier 300 is a voltage follower. This is described as follows.

Input terminals of the operational amplifier constituting the non-inverting amplifier 300 have the same voltage level with each other by a virtual short effect. Therefore, a voltage at the same level as the voltage V1 applied to the positive input terminal of the operational amplifier appears at the negative input terminal. In addition, since the negative input terminal of the operational amplifier is short-circuited with the output terminal of the operational amplifier, the output voltage of the non-inverting amplifier 300 becomes V1.

The timing adjustment circuit 310 is connected to the output terminal of the non-inverting amplifier 300. The timing adjusting circuit 310 adjusts the rise time and the fall time of V1, which is an output signal of the non-inverting amplifier 300. The timing adjusting circuit 310 is composed of a resistor R and a capacitor C, and serves to adjust the rise time and the fall time of the output signal of the non-inverting amplifier 300.

When the Laplace transform is performed on the timing adjusting circuit 310, the current I input to the timing adjusting circuit 310 is V1 / (R + 1 / sC). Therefore, the output voltage Vo of the timing adjustment circuit 310 is represented by the following [Equation 1].

Further, when the time domain transformation is performed on Vo obtained by Equation 1, Equation 2 below can be obtained.

Therefore, the rise time and the fall time of the output Vo of the timing adjustment circuit 310 may be changed according to the time constant RC. Therefore, by adjusting the rise time and the fall time of the output signal of the timing adjustment circuit 310 input to the data driver, it is possible to perform the operation control with the data driver that is sensitive to the characteristics of the input signal.

In order to control the time constant of the output Vo of the timing adjusting circuit 310, the resistor R is preferably a variable resistor. That is, the capacitor C is set to a predetermined value, and the resistor R is adjusted according to the characteristics of the data driver.

Referring to FIG. 3B, when the input signal V1 is a square wave, the data signal Vo has a predetermined rise time and a delay time. The timing adjustment circuit 310 has a characteristic of a low pass filter with respect to the input signal. Therefore, the rising and falling portions of the square wave, which is a level conversion period belonging to the high frequency region on the square wave's frequency spectrum, are filtered out. That is, the output of the timing adjusting circuit 310 has the characteristics of a slow rise and a slow fall according to the RC time constant, instead of a sudden change in the level. As the RC time constant increases, the rise time and fall time increase as the cutoff frequency of the low pass filter decreases. In addition, when the RC time constant decreases, since the cutoff frequency of the timing adjusting circuit 310 which is the low pass filter increases, the rise time and the fall time decrease. By controlling the variable resistor R described above, the data driving capability of the organic light emitting device may be maximized.

4A and 4B are other circuit diagrams and timing diagrams illustrating a timing controller of an organic light emitting device according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, the time adjustment buffer unit may adjust timing of an output signal of an inverting amplifier 400, a non-inverting amplifier 410 connected to an output terminal of the inverting amplifier 400, and the non-inverting amplifier 410. Has a timing adjustment circuit 420.

Inverting amplifier 400 has a negative feedback structure. That is, the positive input terminal of the first operational amplifier 405 is grounded, the resistor R1 is connected between the input voltage source V1 and the node N1, and the resistor R2 is connected to the feedback path between the node N1 and the output terminal. Since a feedback path is formed between the negative input terminal and the output terminal of the first operational amplifier 405, the inverting amplifier 400 has a negative feedback structure.

For example, when the input voltage of the inverting amplifier 400 is V1, the current I1 flowing into the node N1 through the resistor R1 becomes V1 / R1. This is due to the virtual short characteristic of the op amp. That is, since the voltage of the positive input terminal and the voltage of the negative input terminal are the same, when the positive input terminal is connected to the ground, the voltage level of the negative input terminal is 0V. In addition, since the input impedance of the operational amplifier is infinite, the current I2 flowing from the node N1 to the resistor R2 has the same value as I1. Thus, the current I2 is V1 / R1. In addition, since the voltage V2 of the node N2 is -R2 * I2, V2 becomes-(R2 / R1) * V1. That is, the voltage gain V2 / V1 of the inverting amplifier 400 becomes-(R2 / R1).

The non-inverting amplifier 410 is connected to the output terminal of the inverting amplifier. That is, the positive input terminal of the second operational amplifier 415 is connected to the output terminal of the first operational amplifier 405, and the negative input terminal of the second operational amplifier 415 is connected to the output terminal of the second operational amplifier 415. It is connected to the output terminal. As described above, the non-inverting amplifier 410 has a structure in which a negative input terminal is connected to the output terminal, and thus has a negative feedback structure.

The voltage V2 is input to the positive input terminal of the second operational amplifier 415. In addition, the voltage V3 of the node N3 is equal to the voltage V2 of the node N2 due to the virtual short circuit characteristic of the input terminals of the second operational amplifier 415. Therefore, the level of voltage V3 becomes-(R2 / R1) * V1.

The timing adjustment circuit 420 is connected to the output terminal of the non-inverting amplifier 410. In addition, the resistor R3 and the capacitor C are configured to adjust the rise time and the fall time of the output signal of the non-inverting amplifier 410.

When the Laplace transform is performed on the timing adjusting circuit 420, the input impedance of the node N3 facing the timing adjusting circuit 420 becomes R3 + (1 / sC). Therefore, the current I3 flowing into the timing adjustment circuit 420 is V3 / {R3 + (1 / sC)}. In addition, since the output voltage V4 of the timing adjustment circuit 420 is I3 / sC, V4 becomes V3 / (1 + sR3C). If this is expressed as V1, the following [Equation 3] can be obtained.

When the resistors R1 and R2 that determine the voltage gain of the inverting amplifier 400 are the same, the voltage gain of the inverting amplifier is -1. Therefore, Equation 3 is expressed by Equation 4 below.

When Equation 4 is converted into the time domain, V4 is expressed by Equation 5 below.

Therefore, the rise time and fall time of the output V4 of the timing adjustment circuit can be changed according to the time constant R3C. Therefore, by adjusting the rise time and the fall time of the output signal of the timing adjustment circuit input to the data driver, it is possible to perform the operation control with the data driver that is sensitive to the characteristics of the input signal.

In order to control the time constant of the output V4 of the timing adjustment circuit, the resistor R3 is preferably a variable resistor. That is, the capacitor C is set to a predetermined value, and the resistor R3 is adjusted according to the characteristics of the data driver.

Referring to FIG. 4B, when the input signal V1 is a square wave, the data signal V4 has a predetermined rise time and delay time. The timing adjustment circuit 420 has a characteristic of a low pass filter with respect to the input signal. Therefore, the rising and falling portions of the square wave, which is a level conversion period belonging to the high frequency region on the square wave's frequency spectrum, are filtered out. That is, the output of the timing adjustment circuit 420 has a characteristic of a gentle rise and a gentle fall according to the time constant expressed by R3C, instead of a sudden change in the level. As the time constant increases, the rise time and fall time increase because the cutoff frequency of the low pass filter decreases. In addition, when the time constant decreases, the cutoff frequency of the timing adjustment circuit 420 which is the low pass filter increases, so that the rise time and the fall time decrease. By controlling the variable resistor R3 described above, the data driving capability of the organic light emitting device can be maximized.

By controlling the variable resistor R3 described above, the data driving capability of the organic light emitting device can be maximized. In addition, by changing the waveform of the data signal that is the output of the time adjustment buffer unit it is possible to minimize the characteristic change of the data driver having a characteristic sensitive to the data signal.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

According to the present invention as described above, the organic light emitting device has an effect that the change according to the signal characteristics is minimized by appropriately adjusting the data signal input to the data driver using the time control buffer.

Claims (14)

A plurality of data lines arranged in a first direction and transferring data signals; A plurality of selection scan lines arranged in a second direction and transferring a selection signal; And A plurality of unit pixels connected to the data line and the selection scan line; In an organic light emitting device, A central processing control unit for generating the data signal; A time adjusting buffer unit for receiving an output of the central processing control unit and outputting a data signal in which rising and falling times are adjusted; A data driver for applying the data signal to the plurality of data lines; A scan driver which applies the selection signal to the plurality of selection scan lines; And And a plurality of organic light emitting diodes emitting light corresponding to data currents or data voltages applied to the unit pixels. The method of claim 1, wherein the time adjustment buffer unit, A non-inverting amplifier for receiving the output of the central processing controller and outputting a signal having the same gain and phase; And And a timing adjusting circuit for adjusting a rise time and a fall time according to the output signal of the non-inverting amplifier. The organic light emitting device of claim 2, wherein the non-inverting amplifier is an operational amplifier having a structure in which a positive input terminal receives an output of the central processing controller and a negative input terminal is connected to an output terminal. 4. The organic light emitting device of claim 3, wherein the timing adjusting circuit is a low pass filter composed of a resistor and a capacitor. The organic light emitting device of claim 4, wherein the timing adjusting circuit adjusts the rise time and fall time of the input signal by varying the resistance. 6. The organic light emitting device of claim 5, wherein the adjustment of the rise time and the fall time of the timing adjustment circuit is determined by the product of the resistance and the capacitance of the capacitor. 7. The organic light emitting device of claim 6, wherein the organic light emitting device further comprises a gamma correction circuit for gamma correction. The method of claim 1, wherein the time adjustment buffer unit, An inverting amplifier receiving the output of the central processing controller and outputting a signal having the same gain and the opposite phase; A non-inverting amplifier for receiving the output signal of the inverting amplifier and outputting a signal having the same gain and the same phase as the output signal of the inverting amplifier; And And a timing adjusting circuit for adjusting a rising time and a falling time of the output signal of the non-inverting amplifier. 9. The organic light emitting device of claim 8, wherein the timing adjustment circuit is a low pass filter composed of a resistor and a capacitor. 10. The organic light emitting device of claim 9, wherein the timing adjusting circuit adjusts the rise time and the fall time of the input signal by varying the resistance. 11. The organic light emitting device of claim 10, wherein the adjustment of the rise time and the fall time in the timing adjustment circuit is determined by the product of the resistance and the capacitance of the capacitor. The organic light emitting device of claim 11, wherein the organic light emitting device further comprises a gamma correction circuit for gamma correction. The organic light emitting device of claim 1, wherein when the plurality of data lines are formed in the horizontal direction, the plurality of selective scan lines are formed in the second direction. The organic light emitting device of claim 1, wherein when the plurality of data lines are formed in the vertical direction in the first direction, the plurality of selective scan lines are formed in the horizontal direction in the second direction.

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