KR100600326B1 - Control driver for display device - Google Patents

Abstract

The present invention provides an LCD for driving a single port SRAM capable of appropriately adjusting an operation timing when reading / writing data to and from a single port SRAM and an operation timing when displaying data, thereby preventing errors during operation. In order to provide a driver, the present invention provides a driver for controlling a single port memory to drive a display device, the method comprising: receiving and decoding a bank address to enable a plurality of banks included in the memory; A bank address decoder for outputting a plurality of bank enable signals for the bank; A data read / write controller configured to provide a first control signal activated during a period in which the memory is enabled, and a second control signal activated during a data read / write operation of the memory; And a bank for outputting the plurality of bank enable signals in response to the first control signal, and for outputting the plurality of second bank enable signals in response to the second control signal. Provided is a driving driver of a screen display device having an enable signal generator.

Address, Control Unit, Single Port SRAM, Enable, Bank

Description

DRIVE DRIVER FOR DISPLAY DEVICE}             

1 is a block diagram of a drive driver for controlling an SRAM according to the prior art.

FIG. 2 is a waveform diagram showing that a bank enable signal is generated in accordance with an address signal input to the LCD driver shown in FIG.

FIG. 3 is a waveform diagram showing the operation of the LCD driver shown in FIG. 1; FIG.

Fig. 4 is a waveform diagram showing a problem caused by the LCD driver shown in Fig. 1;

5 is a block diagram of a drive driver according to a preferred embodiment of the present invention.

FIG. 6 is a block diagram showing only the drive driver shown in FIG. 5 to more clearly show the present invention. FIG.

FIG. 7 is a circuit diagram showing an interface controller shown in FIG. 6; FIG.

FIG. 8 is a circuit diagram showing a bank enable signal controller and a data read / write controller shown in FIG.

Fig. 9 is a waveform diagram showing the operation of the LCD driver shown in Fig. 6;

10 and 11 are waveform diagrams showing in more detail the operation of the drive driver shown in FIG.

* Explanation of symbols for main parts of the drawings

110: interface control unit

130: bank enable signal generator

The present invention relates to an LCD driver for driving a static random access memory (SRAM) used as a display memory of a display device such as an LCD (Liquid Crystal Display Element).

1 is a block diagram of a driving driver for controlling an SRAM according to the prior art.

Referring to FIG. 1, the LCD driver according to the related art includes an interface controller 12 for receiving and transmitting an address (Ladd <7: 0> .Xadd <7: 0>, Yadd <7: 0>), The bank enable signal generator 11 for generating and outputting the bank enable signals BANK_EN1 to BANK_EN3 by receiving a bank address among the addresses, and a data read / write for controlling the data read or write of the SRAM 20. The control unit 13 is provided.

On the other hand, the SRAM 20 has a plurality of banks, in which three banks 21, 22, and 23 are provided.

Each bank is enabled by the bank enable signals BANK_EN1 to BANK_EN3 output from the bank enable signal controller 11. The bank enable signal generator 11 receives the address Xadd <7: 5> provided from the interface controller and outputs the bank enable signals BANK_EN1 to BANK_EN3.

FIG. 2 is a waveform diagram illustrating that a bank enable signal is generated according to an address signal input to the driving driver shown in FIG.

2 illustrates an operation of generating the bank enable signals BANK_EN1 to BANK_EN3 by the bank enable signal generator 11. Each bank 21, 22, 23 provided in the SRAM is activated by the bank enable signals BANK_EN1 to BANK_EN3.

In addition, the data read / write control unit 13 is a block for supplying a control signal when reading or writing data to the SRAM.

FIG. 3 is a waveform diagram showing the operation of the drive driver shown in FIG.

The memory enable signal MEM shown in FIG. 3 is a waveform for enabling the SRAM, and the precharge signal Pre_charge is a signal for precharging the inside of the SRAM.

In addition, the control signal WRS is a signal generated inside the SRAM in response to the write command.

As described above, the bank enable signal BANK_EN1 is a signal for enabling bank1, and the internal bank enable signal BANK_EN1_IN is a signal that is activated while receiving an address in the enabled bank1. The control signal WRSA is a signal generated for processing data in the SRAM.

The control signal WLEN is a signal that is activated during the time of enabling the decoder to decode the input address. The fact that the control signal WLEN is activated means that the SRAM can activate the word line corresponding to the decoded address. To say.

The word line signal WL_X is a signal indicating that the selected word line is activated according to the decoded address.

Also, the word line signal WL_0 is a signal that should not be generated in the normal operation, and since the address port is opened for a predetermined time even after the normal word line signal WL_X is activated during the period in which the control signal WLEN is activated. It is a signal that is activated for a while due to malfunction.

FIG. 4 is a waveform diagram showing a problem caused by the drive driver shown in FIG.

FIG. 4 is a waveform diagram illustrating the above-described malfunction in more detail. A waveform of a normal word line signal WL0, WL1 is enabled during a period where the bank enable signal Bank_en1 is enabled. However, due to a malfunction, a section in which the word line WL0 is continuously enabled instantaneously (see arrow) will be described in detail.

In order to drive a screen display device such as an LCD, a medium for storing a memory displayed on the screen is required. As described above, an SRAM is used, and an LCD driver is required to drive the SRAM.

At this time, SRAM is divided into a number of pieces, each of which is called a bank. Each bank is enabled using the upper few bits of data input to the SRAM.

On the other hand, when the LCD is driven using a single port SRAM, one address decoder is commonly used to read / write data from the SRAM and to output the data to the LCD.

This common use causes the following problems.

First, as a problem that may arise, the Y address decoding portion of the address decoder should not be used when the data in the SRAM is displayed on the LCD. This is because when data is displayed on the LCD, all data on one line is transferred to the LCD at once.

In addition, two address lines (a line for display and a line for read / write of SRAM) are simultaneously connected to the Y decoding portion, and a signal for selecting the same occurs during the above-described bank enable signal and read / write operation. Is a combination of control signals.

Second, a margin must exist at one of the two address lines connected to the Y decoding section and at the timing at which the selected and Y decoding sections are enabled. If this margin does not exist, the address to be decoded is entered. As soon as it closes, the output address becomes 0 (initial setting value), and this 0 address is output to a valid address, which may cause a malfunction (especially in case of SRAM operating at low voltage, it causes more delay because of gate delay. Can be.)

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and by appropriately adjusting the operation timing when reading / writing data to and from the single port SRAM, the operation timing when displaying data, thereby preventing errors during operation. It is an object of the present invention to provide an LCD driver for driving a single port SRAM.

The present invention provides a plurality of bank enable signals for enabling a plurality of banks included in the memory by receiving and decoding a bank address in a driving driver for controlling a single port memory to drive a display device. A bank address decoder; A data read / write controller configured to provide a first control signal activated during a period in which the memory is enabled, and a second control signal activated during a data read / write operation of the memory; And a bank for outputting the plurality of bank enable signals in response to the first control signal, and for outputting the plurality of second bank enable signals in response to the second control signal. Provided is a driving driver of a screen display device having an enable signal generator.

The present invention provides a bank enable signal that can be addressed when reading / writing data to an SRAM using a bank enable signal generated by a driving driver using a single port SRAM, and for controlling an SRAM. The bank enable signal is set aside to secure timing margins for each signal. In addition, it is to prevent collision between the address signals connected to the Y decoding when displaying data stored in the SRAM and reading / writing data to the SRAM. In addition, when the memory does not need to be enabled, all banks are disabled, reducing power consumption.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a block diagram of a driving driver according to a preferred embodiment of the present invention.

Referring to FIG. 5, the driving driver according to the present exemplary embodiment includes a bank controller 110, an interface controller 120, and a data read / write controller 130 to control the SRAM 200.

Here, the interface controller 110 transmits the addresses (Ladd <7: 0>, Xadd <7: 0>, Yadd <7: 0>) input to the SRAM 200 to the SRAM, and correspond to the bank addresses. The address Xadd <7: 5> is transmitted to the bank controller 110.

The SRAM includes a plurality of banks 210 to 230, and the enable signals BANK_SEN1 to BANK_SEN3 and BANK_AEN1 to BANK_AEN3 for enabling each bank are generated and output by the bank controller 110.

The data read / write controller 120 is a controller for reading or writing data in each bank of the SRAM.

FIG. 6 is a block diagram showing the bank control unit and the data read / write control unit 130 only of the drive driver shown in FIG. 5 for clarity of the present invention.

Referring to FIG. 6, the driving driver according to the present embodiment receives the bank addresses X7 to X5 to control the single port SRAM 200 in order to drive the display device, and the SRAM 200. A bank address decoder 110A for outputting a plurality of bank enable signals BANK_EN1 to BANKE_EN3 for enabling a plurality of banks provided in the bank, a control signal MEN that is activated during an interval in which SRAM is enabled, A data read / write controller 130 for providing a control signal WREN that is activated during a data read / write operation of a memory and a plurality of bank enable signals BANK_EN1 to BANKE_EN3 are input to the control signal MEN. In response, the bank enable signals for outputting the plurality of first bank enable signals BANK_SEN1 to BANKE_SEN3 and for outputting the plurality of second bank enable signals BANK_AEN1 to BANKE_AEN3 in response to the control signal WREN. The generation unit 110B is provided.

FIG. 7 is a circuit diagram illustrating an interface controller shown in FIG. 6.

Referring to FIG. 7, the bank address decoder 110A may include a bank among addresses (Ladd <7: 0> .Xadd <7: 0>, Yadd <7: 0>) that are input to control the SRAM 200. The first decoder 111 for buffering and transmitting the address of the upper bit corresponding to the address Xadd <7: 5> and its inverted signal, and the address and the inverted signal transmitted through the first decoder 111 And a second decoder 112 for selectively receiving a number of bank enable signals BANK_EN1 to BANKE_EN3 corresponding to the number provided in the SRAM 200.

FIG. 8 is a circuit diagram illustrating a bank enable signal controller and a data read / write controller shown in FIG. 6.

Referring to FIG. 8, the data read / write control unit 130 may respond to a read command READ input to read data to the SRAM or a write command WRITE input to write data to the SRAM. A signal combination unit 132 for outputting a control signal WREN and a signal transmission unit 131 for receiving a waveform enabled for the SRAM 200 and transmitting the waveform to the control signal MEN.

In addition, the signal combination unit 132 may output the control signal WREN by inverting the output of the read command RDS buffered by the timing controller, the NOR gate receiving the write command WDS, and the NOR gate. With an inverter.

The bank enable signal generator 110B combines a plurality of bank enable signals BANK_EN1 to BANKE_EN3 in response to the control signal MEN, and outputs a plurality of first bank enable signals BANK_SEN1 to BANKE_SEN3. And a second signal combination section 114 for outputting a plurality of second bank enable signals BANK_AEN1 to BANKE_AEN3 in response to the control signal WREN.

The first signal combination unit 113 includes a plurality of first NAND gates receiving one of a plurality of bank enable signals BANK_EN1 to BANKE_EN3 on one side and a control signal MEN on the other side, and a plurality of first signals. A plurality of first inverters respectively output the plurality of first bank enable signals BANK_SEN1 to BANKE_SEN3 by inverting the outputs of the NAND gates.

The second signal combination unit 114 includes a plurality of second NAND gates receiving one of a plurality of bank enable signals BANK_EN1 to BANKE_EN3 on one side and a control signal WRS on the other side, and a plurality of second A plurality of second inverters respectively inverting outputs of the NAND gate and outputting a plurality of second bank enable signals BANK_AEN1 to BANKE_AEN3 are provided.

FIG. 9 is a waveform diagram showing the operation of the drive driver shown in FIG. 10 and 11 are waveform diagrams showing in more detail the operation of the drive driver shown in FIG.

Hereinafter, the operation of the driving driver according to the present embodiment will be described with reference to FIGS. 5 through 11.

When the drive driver according to the present embodiment uses a single port SRAM to drive a display device such as an LCD, the data is displayed by separating signals for enabling a plurality of banks included in the SRAM separately for address and control. The main feature is that it prevents address collisions that may occur when using the system, and also secures timing margins to eliminate the output of unwanted addresses.

The bank address decoder 110A of the bank control unit 110 generates the bank enable signals BANK_EN1 to BANKE_EN3 that are generated by using the upper three bits of the X address (X5 to X7).

Subsequently, the bank enable signal generation unit 110B is generated by the data read / write control unit 130, the control signal WREN generated by the combination of the write signal WRS, the read signal RDS, and the bank. NAND combination of enable signals BANK_EN1 to BANKE_EN3 enables SRAM, which is a desired section only when data read or write operation of memory is operated, receives and processes X address and Y address. The first bank enable signals BANK_AEN1 to BANKE_AEN3 are generated and output.

Therefore, the SRAM under the control of the driving driver according to the present embodiment is not assigned to any address of the SRAM during a time other than the data read or write operation time, so that the read or write related operation is not performed.

In a similar manner, this time, the enable signal BANK_EN1 to BANKE_EN3 generated by the bank address decoder enables the SRAM's sense amplifier to operate while pre-charging, etc., while SRAM is enabled. The second bank enable signals BANK_SEN1 to BANKE_SEN3 are generated and output.

As shown in FIG. 10, it is shown that the first bank enable signals BANK_AEN1 to BANKE_AEN3 and the second bank enable signals BANK_SEN1 to BANKE_SEN3 operate at intervals of a precharge time.

The precharge signal is generated first, and the read / write signal is generated first, and the address value is input to the memory and set first with a slight timing margin before that, and the designated Y when the read / write signal is generated. It is a typical behavior of SRAM to enable the Y-axis decoder to enable the address to activate the word line.

In addition, since the Y-axis decoder must output a line address during display, it must be enabled during display time. When the LDE0 signal, which is the display signal, is enabled as shown in FIG. 11, a line address must be output to the Y decoder.

In the conventional method, the bank enable signals BANK_EN1 to BANKE_EN3 generated by the bank enable signal controller (see 11 in FIG. 1) are used to select the Y address, and thus are activated in the display device during the SRAM read / write operation. The wrong SRAM address related to the read / write operation could be used for the operation of the display (two word lines WL_X and WL_0 are enabled as shown in FIG. 3 to malfunction).

However, in the driving driver of the present invention, as shown in FIG. 6, the filtered enable signal called the first bank enable signal Bank_AEN selects the Y address of the SRAM. The case where the word lines are enabled at the same time is eliminated.

11, it can be seen that the output of address 0 due to the timing margin error shown in FIG. 4 disappears.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, when driving a single port SRAM in a device such as an OLED driver or an STN driver, the timing margin when displaying data stored in the SRAM and reading / writing data to the SRAM can be generated. The malfunctions can be eliminated.

In addition, when the display is on or when the read / write operation of the SRAM data is not performed, the banks of the entire SRAMs are disabled, thereby saving power consumed.

Claims (5)

In the drive driver to control the single port SRAM to drive the display device, A bank address decoder configured to decode a bank address and output a respective bank enable signal for enabling a plurality of banks included in the single port SRAM; A data read / write controller configured to provide a first control signal activated during a period during which the single port SRAM is enabled, and a second control signal activated during a data read / write operation of the single port SRAM; And Receiving the bank enable signal, outputting a first bank enable signal corresponding to each bank in response to the first control signal, and enabling a second bank corresponding to each bank in response to the second control signal Bank enable signal generator for outputting a signal Driving driver of the display device having a. The method of claim 1, The bank address decoder, A first decoder for buffering and transmitting a row address of an upper bit corresponding to a bank address and an inverted signal thereof among the addresses input to control the single port SRAM; And And a second decoder configured to selectively receive an address transmitted through the first decoder and an inverted signal thereof, and output a bank enable signal corresponding to each bank of the single port SRAM. Driver. The method of claim 1, The data read / write control unit, A signal combination unit for outputting the second control signal in response to a read command input to read data to the single port SRAM or a write command input to write data to the single port SRAM; And And a signal transfer unit configured to receive the waveform enabled by the single port SRAM and transmit the waveform to the first control signal. The method of claim 3, wherein The signal combination unit, A nor gate receiving the read command and the write command; And And an inverter for outputting the second control signal by inverting the output of the NOR gate. The method of claim 1, The bank enable signal generator, A first signal combination unit for inputting a bank enable signal corresponding to each bank and the first control signal and outputting the first bank enable signal corresponding to each bank; And a second signal combination unit configured to output a second bank enable signal by inputting a bank enable signal corresponding to each bank and the second control signal.

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