KR100597851B1 - Substrate strip for a chip scale type semiconductor package - Google Patents

Abstract

The present invention relates to a substrate strip for a chip scale semiconductor package, and in the present invention, area control patterns are further formed on a portion of the base plane to adjust area increase widths of the signal connection patterns while being electrically connected to the respective signal connection patterns. Let's do it. In this case, the area adjustment patterns are, for example, a plurality of pattern lines electrically connected to the respective signal connection patterns, and a plurality of pattern lines connected to the pattern lines one-to-one, electrically separated from each other, and having different sizes from each other. It consists of a combination of pattern pads.

In this state, when the base plane is combined with the semiconductor chip, in the production line, the area of each signal connection pattern is controlled by controlling the electrical connection state between each signal connection pattern and the pattern pads by adjusting the connection state of the pattern lines. Adjust the increment freely.

When the present invention is achieved, the production line can freely adjust the input capacitance value in accordance with the area increase width adjustment of each signal connection pattern, thereby minimizing the additional cost required for adjusting the input capacitance value. As a result, the semiconductor chip can be smoothly speeded up.

Description

Substrate strip for a chip scale type semiconductor package

1 is an exemplary view showing a substrate strip for a chip scale semiconductor package according to the present invention.

Figure 2 is an exemplary view showing an area control pattern according to an embodiment of the present invention.

Figure 3 is an exemplary view showing an area adjustment pattern according to another embodiment of the present invention.

4 is an exemplary view showing a chip scale semiconductor package employing the substrate strip of the present invention.

The present invention relates to a substrate strip for fabricating a chip scale semiconductor package, and more particularly, further arranges dummy patterns adjacent to the signal connection patterns, thereby freeing the area increase of each signal connection pattern. By adjusting, the present invention relates to a substrate strip for a chip scale semiconductor package capable of elastically adjusting an input capacitance value affecting electrical characteristics of a semiconductor chip.

In recent years, as memory capacities of electronic and information devices have increased, semiconductor chips have become increasingly integrated. Accordingly, the size of semiconductor chips has gradually increased.

However, in contrast to the increase in size of such semiconductor chips, packaging technologies for packaging semiconductor chips are moving toward the direction of making the size of the final semiconductor chip package light and small in accordance with the trend of miniaturization and light weight of electronic and information devices.

In recent years, with the rapid development of semiconductor chip packaging technology, surface-mount semiconductor packages such as BGA type semiconductor packages have been developed that can accommodate semiconductor chips of larger sizes while minimizing their size. In addition, as the technology continues to develop, chip-scale semiconductor packages such as FBGA type semiconductor packages and μBGA type semiconductor packages are being developed in which the size of the semiconductor package approaches 120% of the semiconductor chip size.

Various structures of such conventional chip scale semiconductor packages are described, for example, in US Pat. No. 56,63593, "Ball grid array package with lead frame," US Pat. No. 5,706,178, "Sold in a package." Ball grid array integrated circuit package that has vias located within the solder pads of a package ", US Patent No. 5708567" Ball Grid with Ring Type Heat Sink " Ball grid array semiconductor package with ring-type heat sink ", US Patent No. 5729050" Semiconductor package substrate and ball grid array semiconductor package using same " , US Patent No. 5741729 "Ball grid array package for an integ rated circuit), US Pat. No. 5748450, "BGA package using a dummy ball and a repairing method," US Pat. No. 5796170, "Ball grid array integrated circuit." Packages (Ball grid array integrated circuit packages) ".

In recent years, with the rapid development of semiconductor processing technology, information processing speed of semiconductor chips mounted in chip scale semiconductor packages is also gradually increasing.

For example, the so-called "Rambus DRAM", "Synlink DRAM", Synchronous Double Data Rate DRAM, etc., which are recently attracting attention as a next-generation memory device, process the information. The speed is over 200MHz.

As described above, with the rapid increase in the information processing speed of semiconductor chips, a so-called "Propagation time delay" defect factor has rapidly emerged as a big problem preventing the semiconductor chips from speeding up.

Recently, as research on semiconductor chips has been repeated, the argument that "the factor that has the greatest influence on the propagation time delay is input capacitance input from the semiconductor package to the semiconductor chip" has been established. Accordingly, the conventional production line is seeking a variety of methods for adjusting the input capacitance.

Various efforts to reduce this input capacitance have been described, for example, in US Pat. signal pads and signal lines is matched by reducing the size of a ground plane ", US Patent No. 5650739" Programmable Delay Lines ", and the like.

As described above, in order to realize the high speed of the semiconductor chip in the conventional production line, various methods for adjusting the input capacitance have been sought, but despite these efforts, a specific method for more stably adjusting the input capacitance is There is no situation so far.

Although several useful methods have been proposed, they are very difficult to practically apply to a production line because they present additional problems.

For example, "an additional method for installing an option circuit that can adjust the time delay inside the semiconductor chip," in this case, because the enormous additional cost of installing the option circuit is required On the other hand, the production line does not make this solution practical.                         

Another example is "a method of measuring the time delay of a semiconductor chip after the semiconductor package is assembled and reflecting the measured value to the next-designed semiconductor chip or semiconductor package." In this case, the semiconductor chip or semiconductor Due to the enormous additional time and cost involved in redesigning the package, this approach is also not practical on the production line.

Accordingly, an object of the present invention is to freely adjust the input capacitance value of a semiconductor package while minimizing the cost.

Another object of the present invention is to induce stable speed of the semiconductor chip by allowing the input capacitance value of the semiconductor package to be freely adjusted.

It is still another object of the present invention to induce a higher speed of a semiconductor package, thereby to improve the performance of electronic and information devices equipped with the semiconductor package.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

The substrate strip of the present invention for achieving the above object is a base plane, a plurality of solder ball windows for opening the base plane, embedded in the bottom of the base plane, the base plane is coupled to the semiconductor chip In this case, a combination of signal connection patterns electrically connected to the bonding pads of the semiconductor chip may be used.

At this time, the above-described base plane is further formed with an area adjustment pattern for adjusting the area increase width of the signal connection patterns in the state electrically connected to each signal connection pattern, in this case, the area adjustment patterns are, for example, each signal connection pattern And a plurality of pattern lines electrically connected to each other, and a plurality of pattern pads connected to the pattern lines one-to-one, electrically separated from each other, and having different sizes.

In this state, when the base plane is coupled with the semiconductor chip, the production line adjusts the electrical connection state between the signal connection patterns and the pattern pads by adjusting the connection state of the pattern lines.

In this case, if most of the pattern lines for electrically connecting the respective signal connection patterns and the pattern pads in the production line are cut, each signal connection pattern is in an electrically connected state with a few pattern pads. In the production line, the same effect as the overall area of each signal connection pattern is increased slightly.

As such, when the overall area of each signal connection pattern is slightly increased, the input capacitance value that affects the electrical characteristics of the semiconductor chip is also slightly increased.

In addition, when only a few of the pattern lines electrically connecting the respective signal connection patterns and the pattern pads in the production line are cut, each signal connection pattern is in an electrically connected state with most of the pattern pads. In this case, the production line can obtain the same effect as the overall area of each signal pattern is greatly increased.

As such, when the overall area of each signal connection pattern is greatly increased, the input capacitance value which affects the electrical characteristics of the semiconductor chip is also greatly increased.

In other words, in the present invention, by adjusting the connection state of each of the signal connection patterns and the pattern lines electrically connecting the pattern pads, the input capacitance value affecting the electrical characteristics of the semiconductor chip can be freely adjusted.

When the present invention is achieved, the production line can freely adjust the input capacitance value by adjusting the connection state of the pattern lines, thereby minimizing the cost required for adjusting the input capacitance value, while speeding up the semiconductor chip. Can be secured smoothly.

Hereinafter, a substrate strip for a chip scale semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

In general, in a production line, in order to manufacture a chip-scale semiconductor package having a final structure, a process of manufacturing a substrate strip and a process of manufacturing a semiconductor chip assembly are separately performed, and then the substrate strip on which the manufacturing is completed is processed into a semiconductor chip. Attach to the assembly.

1, the substrate strip 10 according to the present invention is arranged on the surface of the base plane 13 with the base plane 13 and the surface of the base plane 13 open. A combination of a plurality of solder ball windows 14 and signal connection patterns 12 made of, for example, metal embedded in the bottom of the base plane 13 is formed.

At this time, one end of the signal connection patterns 12 forms a structure exposed to the upper portion of the base plane 13 through the solder ball windows 14 described above, the other end of the signal connection patterns 12 is the base It extends to the side of the plane 13 to form a structure exposed.

Here, as shown in the figure, the above-described base plane 13, the area control patterns 30 for adjusting the area increase width of the signal connection patterns 12 in an electrically connected state with each of the signal connection patterns 12 ) Is further formed.

The structure of forming the area control patterns 30 is a part of the present invention, and, of course, the area control patterns are not formed in the conventional substrate strip.

In this case, as shown in FIG. 2, the area control patterns 30 according to an embodiment of the present invention are, for example, a plurality of pattern lines 31 electrically connected to the respective signal connection patterns 12. And a plurality of pattern pads 32 connected to the pattern lines 31 one-to-one, electrically separated from each other, and different in size from each other.

In this case, in the production line, the signal connection patterns 12 and the pattern pads are adjusted by adjusting the connection state of the pattern lines 31 electrically connecting the signal connection patterns 12 and the pattern pads 32. Adjust the electrical connection between the two (32).

Here, exposure openings 33 exposing the pattern lines 31 to the outside are further formed in the base plane 13 corresponding to the pattern lines 31 described above. In the production line, by using these exposure openings 33, the connection state of the pattern lines 31 can be freely adjusted.

If, by using an embodiment of the present invention, it is desired to slightly increase the input capacitance value affecting the electrical characteristics of the semiconductor chip, the production line exposed the pattern lines 31 through the exposure opening 33. Proceed with the process of cutting most of the. In this case, each of the signal connection patterns 12 may transmit an electrical signal to only a few pattern pads 32 except for the most pattern pads 32. The same effect as that in which the total area of (12) is slightly increased can be obtained.

For example, in the production line, when cutting the remaining pattern lines 31a, 31b, 31c, 31d except for the pattern line 31e among the pattern lines 31 exposed through the exposure opening 33, each The signal connection patterns 120 can transmit electrical signals only to the pattern pads 32e except for most of the pattern pads 32a, 32b, 32c, and 32d. As a result, each signal connection pattern ( The same effect as that in which the overall area of 12) is slightly increased by the area of the pattern pad 32e can be obtained.

As such, when the overall area of each of the signal connection patterns 12 is slightly increased, when an external electric signal is input to each of the signal connection patterns 12, the input electric signal is " signal connection pattern " 12) -pattern line 31e-pattern pad 32e-bonding pad ", which is input to the semiconductor chip, and thus, input capacitance values affecting the electrical characteristics of the semiconductor chip are also determined. As area increases, it increases slightly.

On the other hand, by using the embodiment of the present invention, if you want to significantly increase the input capacitance value affecting the electrical characteristics of the semiconductor chip, the pattern line 31 exposed through the exposure opening 33 in the production line The process of cutting only a few pattern lines 31 of the proceeds. In this case, each of the signal connection patterns 12 may transmit an electrical signal to most of the pattern pads 32 except for the few pattern pads 32. The same effect as that in which the overall area of the field 12 is greatly increased can be obtained.

For example, in the production line, when only the remaining pattern line 31e except for most of the pattern lines 31a, 31b, 31c, and 31d of the pattern lines 31 exposed through the exposure opening 33 is cut. Each of the signal connection patterns can transmit electrical signals to most of the pattern pads 32a, 32b, 32c, and 32d except for the pattern pads 32e. The same effect as that greatly increased by the area of the pattern pads 32a, 32b, 32c, and 32d can be obtained.

As described above, when the overall area of each signal connection pattern is greatly increased, when an external electric signal is input to each signal connection pattern, the input electric signal is " signal connection pattern 12-pattern line 31a. ) -Pattern pad 32a-bonding pad "," signal connection pattern 12-pattern line 31b-pattern pad 32b-bonding pad "," signal connection pattern 12-pattern line 31c- It is input to the semiconductor chip via the pattern pad 32c-bonding pad, the signal connection pattern 12, the pattern line 31d, the pattern pad 32d, and the bonding pad, respectively. The input capacitance value that affects also increases significantly as the area of each signal connection pattern increases.

That is, in the present invention, the area increase width of each signal connection pattern 12 is adjusted by adjusting the connection state of the pattern lines 31 electrically connecting the signal connection patterns 12 and the pattern pads 32. By adjusting, the input capacitance value affecting the electrical characteristics of the semiconductor chip can be freely adjusted.

When the present invention is achieved, the production line can only freely adjust the input capacitance value by adjusting the connection state of the pattern lines 31, while minimizing the cost required for adjusting the input capacitance value. High speed semiconductor chips can be secured smoothly.

On the other hand, as shown in Figure 3, the area control patterns 40 according to another embodiment of the present invention is a plurality of pattern lines 41 are continuously arranged in electrical connection with each of the signal connection patterns 12 ) And a plurality of pattern pads 42 interposed between the pattern lines 41 in an electrically connected state with the pattern lines 41 and having the same size as each other.

At this time, in another embodiment of the present invention by adjusting the connection state of the pattern lines 41 for electrically connecting the respective signal connection patterns 12 and the pattern pads 42, as in the above-described embodiment, each signal The electrical connection between the connection patterns 12 and the pattern pads 42 is adjusted.

Of course, in another embodiment of the present invention, the base plane 13 corresponding to the pattern lines 41 is further formed with exposure openings 43 for exposing the pattern lines 41 to the outside, the production line In the exposure openings 43, the connection state of the pattern lines 41 can be freely adjusted.

If, in the production line, using a different embodiment of the present invention, to slightly increase the input capacitance value affecting the electrical characteristics of the semiconductor chip, the production line is exposed through the exposure opening 43 A process of cutting only the pattern line 41 located at the front of the pattern lines 41 is performed. In this case, each of the signal connection patterns 12 may transmit an electrical signal only to the pattern pads 42 of the front part except for the pattern pads 42 located at the rear part. The same effect as that in which the overall area of the signal connection patterns 12 is slightly increased can be obtained.

For example, in the production line, when only the pattern line 41b located at the front of the pattern lines 41 exposed through the exposure opening 43 is cut, each of the signal connection patterns 12 is formed in most pattern pads. The electrical signal can be transmitted only to the pattern pads 42a except for (42b, 42c, 42d, 42e). Consequently, in the production line, the overall area of each signal connection pattern 12 is determined by the pattern pad 42a. The same effect as that slightly increased by area can be obtained.

As described above, in the state in which the overall area of each signal connection pattern is slightly increased, when an external electrical source is input to each signal connection pattern, the input electric signal is " signal connection pattern 12-pattern line 41a. The input capacitance value, which affects the electrical characteristics of the semiconductor chip, is also slightly increased in accordance with the area increase of each signal connection pattern 12. Done.

On the other hand, by using another embodiment of the present invention, if you want to significantly increase the input capacitance value affecting the electrical characteristics of the semiconductor chip, in the production line pattern lines 41 exposed through the exposure opening 43 In the process of cutting the pattern line 41 located in the rear part of the). In this case, each of the signal connection patterns 12 may transmit an electrical signal to most of the pattern pads 42 located at the front except the few pattern pads 42 located at the rear, thereby producing In the line, the same effect as that in which the overall area of each signal connection pattern 12 is greatly increased can be obtained.

For example, in the production line, of the pattern lines 41 exposed through the exposure opening 43, only the remaining pattern line 41e except for most of the pattern lines 41a, 41b, 41c, and 41d located at the front part thereof. When cutting, each signal connection pattern 12 is capable of transmitting electrical signals to most of the pattern pads 42a, 42b, 42c, 42d except for the pattern pad 42e. The same effect as the overall area of each signal connection pattern 12 is greatly increased by the area of the pattern pads 42a, 42b, 42c, and 42d can be obtained.

As such, when the overall area of each signal connection pattern 12 is greatly increased, when an external electrical signal is input to each signal connection pattern 12, the input electric signal is " signal connection pattern " 12)-Pattern line 41a-Pattern pad 42a-Pattern line 41b-Pattern pad 42b-Pattern line 41c-Pattern pad 42c-Pattern line 41d-Pattern pad 42d -Input to the semiconductor chip through the "bonding pad", and eventually, the input capacitance value that affects the electrical characteristics of the semiconductor chip also increases significantly in accordance with the area increase of each signal connection pattern (12).

That is, in another embodiment of the present invention, as in the above-described embodiment, by adjusting the connection state of the pattern lines 41 for electrically connecting the respective signal connection patterns 12 and the pattern pads 42, By adjusting the area increase width of the signal connection patterns 12, the input capacitance value affecting the electrical characteristics of the semiconductor chip can be freely adjusted.

When this embodiment of the present invention is achieved, the production line can only freely adjust the input capacitance value by adjusting the connection state of the pattern lines 41, thereby minimizing the cost required for adjusting the input capacitance value. At the same time, it is possible to smoothly increase the speed of the semiconductor chip.

On the other hand, when the manufacture of the substrate strip according to the present invention having the above-described configuration is completed, the production line in the production line by attaching the substrate strip to the semiconductor chip assembly manufactured by a separate manufacturing process, the chip scale of the final structure A semiconductor package is manufactured.

As shown in FIG. 4, the chip scale semiconductor package 100 employing the substrate strip of the present invention generally has a semiconductor chip 1 and a base plane 13 disposed on the semiconductor chip 1. And a combination of a plurality of solder balls 15 arranged in the solder ball windows 14 of the base plane 13. Of course, the base plane 13 is a structure that forms part of the substrate strip 10 described above.

In this case, a plurality of bonding pads 2 are arranged on the surface of the semiconductor chip 1 at predetermined intervals, for example, arranged along a center thereof, and the bonding pads 2 may be external circuit blocks, for example. By forming a series of conductive paths with the printed circuit board (not shown), electrical signals output from the printed circuit board can be quickly input to the semiconductor chip 1, or vice versa, output from the semiconductor chip 1 The electrical signal can be quickly input to the printed circuit board. As another example, the bonding pads 2 may be disposed along an edge of the semiconductor chip 1.

Here, between the base plane 13 and the semiconductor chip 1 is a stress buffer film 3, so-called "elastomer" is interposed, such a stress buffer film 3 is the external impact of the semiconductor chip (1) By buffering the transfer to the, it serves to prevent the semiconductor chip 1 from being damaged by an external force in advance.

In this case, signal connection patterns 12 extending to the outside of the base plane 13 are disposed on the surface of the base plane 13 corresponding to the point where the solder balls 15 are attached. Of course, these signal connection patterns 12 are also a part of the substrate strip 10, similar to the base plane 13 described above.

The signal connection patterns 12 form a structure electrically connected to the bonding pads 2 when the assembly of the semiconductor package is completed through various processes.

At this time, in the production line, after the signal connection patterns 12 and the bonding pads 2 are electrically connected, the resin encapsulation member is connected to the bonding pad region where the signal connection patterns 12 and the bonding pads 2 are in contact with each other. By enclosing (4) to firmly fix the final completed signal connection patterns 12 by particles of the resin encapsulation body 4, even when a strong thermal stress is applied to the signal connection patterns 12, the signal The connection patterns 12 are not damaged by the impact.

In this state, when an external printed circuit board is mounted on top of the semiconductor chip 1, the semiconductor chip 1 and the printed circuit board are connected to each other through a series of signal connection patterns 12, thereby providing a series of electrical conduction paths. To form.

In this case, as described above, in the production line, the area increase widths of the signal connection patterns 12 may be freely adjusted by adjusting the connection state of the area control patterns 30, and thus, the electrical of the semiconductor chip 1 may be controlled. The value of the input capacitance affecting the characteristics can also be smoothly adjusted. As a result, it is possible to minimize the cost required to adjust the input capacitance value, while ensuring high speed of the semiconductor chip.

Then, the chip scale semiconductor package employing the substrate strip of the present invention is shipped to the core device of the electronic device by going through a subsequent process, for example, "electric test process", "printed circuit board mounting process" and the like sequentially.

As described above, in the present invention, additional dummy patterns are further disposed in the vicinity of the signal connection patterns for transmitting an external electrical signal to the bonding pads of the semiconductor chip, thereby increasing the area of each signal connection pattern. By freely adjusting, the input capacitance value affecting the electrical characteristics of the semiconductor chip can be flexibly adjusted.

This invention exhibits an overall useful effect in all varieties of chip scale semiconductor packages manufactured in production lines.

And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

 As described in detail above, in the chip strip type semiconductor package substrate strip according to the present invention, area control patterns for controlling the area increase width of the signal connection patterns are electrically connected to each signal connection pattern on a portion of the base plane. To form more. In this case, the area adjustment patterns are, for example, a plurality of pattern lines electrically connected to the respective signal connection patterns, and a plurality of pattern lines connected to the pattern lines one-to-one, electrically separated from each other, and having different sizes from each other. It consists of a combination of pattern pads.

In this state, when the base plane is combined with the semiconductor chip, in the production line, the area of each signal connection pattern is controlled by controlling the electrical connection state between each signal connection pattern and the pattern pads by adjusting the connection state of the pattern lines. Adjust the increment freely.

When the present invention is achieved, the production line can freely adjust the input capacitance value in accordance with the area increase width adjustment of each signal connection pattern, thereby minimizing the additional cost required for adjusting the input capacitance value. As a result, the semiconductor chip can be smoothly speeded up.

Claims (4)

A base plane; A plurality of solder ball windows opening the base plane; Embedded in a bottom of the base plane, and when the base plane is coupled with a semiconductor chip, includes a signal connection patterns electrically connected to bonding pads of the semiconductor chip, The base plane substrate strip for chip-scale type semiconductor package, characterized in that the area control patterns for adjusting the area increase width of the signal connection patterns in the electrically connected with the respective signal connection patterns are formed. The method of claim 1, wherein the area control patterns comprise: a plurality of pattern lines electrically connected to the signal connection patterns; A substrate strip for a chip scale semiconductor package, characterized in that it comprises a plurality of pattern pads that are connected one-to-one with each of the pattern lines and electrically separated from each other. The method of claim 1, wherein the area control patterns comprise: a plurality of pattern lines continuously arranged in electrical connection with each of the signal connection patterns; And a plurality of pattern pads interposed between the pattern lines in electrical connection with the pattern lines and having the same size as each other. 4. The substrate strip of claim 2, wherein the base plane corresponding to the pattern lines further includes exposed openings for exposing the pattern lines to the outside. 5. .

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