KR100587971B1 - Apparatus for controlling a lot of bus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a multi-layer bus control device.

2. The technical problem to be solved by the invention

The present invention provides an input / output bus for inputting and outputting data, a system bus for transmitting data and a program bus for transmitting data, and a bus connection unit for connecting each bus, and a bus mediator for arbitrating use of each bus. Its purpose is to provide a multi-layer bus control device for controlling each bus to operate independently through a controller that controls the modules.

3. Summary of Solution to Invention

The present invention provides a multi-layer bus control apparatus comprising: a plurality of buses for data transfer; Bus connection means for interconnecting the plurality of buses under control of a control means; Bus arbitration means for arbitrating a usage right of each bus so that each bus operates independently of each other; Data processing means for processing data transmitted through each bus; And said control means for controlling said bus connection means to interconnect said plurality of buses.

4. Important uses of the invention

The present invention is used in a system such as a chip processor.

System-on-chip chip processor, multilayer bus structure, bus arbitration, independent operation, multilayer bus controller

Description

Multi-Layer Bus Control Unit {Apparatus for controlling a lot of bus}             

1 is a configuration diagram of an apparatus for controlling a multi-layer bus in a system chip on chip processor according to the present invention;

2 is a configuration diagram of an image processing apparatus having a multi-layer bus structure according to the present invention.

* Explanation of symbols for the main parts of the drawings

101: data input and output unit 102: I / O bus intermediary

103: input and output processor 104: data memory

105: input and output bus 106: bus switch

107: program bus 108: system bus

109: program memory 110: microprocessor

111: System Bus Arbiter 112: System Handler

113: hardware module

The present invention relates to a multi-layer bus control apparatus, and more particularly, a bus connection unit for separating an input / output bus for input / output of data, a system bus for transferring data, and a program bus for transferring programs, and connecting the respective buses. The present invention relates to a multi-layer bus control device for controlling each bus to operate independently through a bus mediator that mediates the use of the bus and a controller that controls each module.

In the following example, a case where a multi-layer bus control device is applied to a system-on-chip chip processor will be described as an example.

Recently, as multimedia services are diversified, various multimedia devices such as mobile phones, PDAs (Personal Digital Assistants), digital TVs (TeleVision), and DVDPs (Digital Versatile Disc Players) have been introduced. Accordingly, interest in processors for multimedia is increasing.

The processor for multimedia has various functions such as image processing, Liquid-Crystal Display (LCD) / Cathode-Ray Tube (CRT) control, and hardware and peripheral control for coding and decoding of video and audio data. And it is being developed in the form of a system-on-chip processor according to the demand of miniaturization.

A system-on-chip processor refers to an integrated circuit (IC) in which a microprocessor, internal memory, a plurality of peripheral devices, and an external bus interface are loaded in one chip. The development of these system-on-chip processors not only reduces system size, but also reduces system testing time, improves system reliability, and reduces time-to-market.

Among the system-on-chip processors, the system-on-chip processor for multimedia refers to a processor including circuits for performing various functions required for multimedia equipment in one chip.

In the development of the system-on-chip processor for multimedia, initially, a single function circuit such as a discrete cosine transform (DCT) or a motion estimator (ME) is built in the structure, such as a static random access memory (SRAM) or a boot ROM ( Evolving into a built-in boot ROM or a large-capacity Synchronous Dynamic Random Access Memory (SDRAM), more features will be added in the future.

In general, a system for designing a system-on-chip processor for multimedia uses a microprocessor announced by a conventional semiconductor company as a core and adds a circuit for performing the remaining functions, rather than redesigning the whole processor. That is, a method of using a complex instruction set computer (CISC) microprocessor such as x86 or 68k or a reduced instruction set computer (RISC) microprocessor such as ARM is used as a core controller in the system.

In the case of the above-described method, the system bus protocol, in which the main components of the system, such as a microprocessor, a memory device, an input / output device, and the like are connected, is used as a shared communication path. It is common to use one provided by a semiconductor company. Therefore, the developer can design the system chip on the basis of the predetermined standard, thereby reducing the design burden on the external interface and the development period of the system chip on the chip.

However, such a conventional system-on-chip processor uses a single shared system bus with circuitry for performing each function.

Therefore, in the conventional technology as described above, when a circuit portion having a low processing speed, such as an image input / output unit, occupies the system bus, the other circuit portion having a high processing speed must wait until the use of the system bus is completed. There was a problem of this deterioration.

The present invention has been proposed to solve the above problems, the bus connection for separating the input and output bus for data input and output, the system bus for data transfer and the program bus for delivery of the program and connecting each bus and each bus It is an object of the present invention to provide a multi-layer bus control device for controlling each bus to operate independently through a bus intermediator intervening its use and a controller controlling each module.

The apparatus of the present invention for achieving the above object is a multi-layer bus control apparatus, comprising: a plurality of buses for data transfer; Bus connection means for interconnecting the plurality of buses under control of a control means; Bus arbitration means for arbitrating a usage right of each bus so that each bus operates independently of each other; Data processing means for processing data transmitted through each bus; And said control means for controlling said bus connection means to interconnect said plurality of buses.

On the other hand, the present invention has the flexibility and expandability in designing a multimedia system because the performance of the bus is improved by switching the multi-layer bus, and the bus hierarchy is easily increased or decreased according to the design specification of the multimedia application field. It is done.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an exemplary embodiment of a multi-layer bus control apparatus in a system-on-chip chip processor according to the present invention.

The components and operations of the multilayer bus control apparatus in the system-on-chip chip processor according to the present invention will be described below.

First, the data input / output unit 101 receives data from the outside or outputs data that has undergone a predetermined process to the outside.

The I / O bus arbiter 102 arbitrates the bus right of use of the I / O bus 105, that is, the bus master module, that is, the I / O processor 103, the microprocessor 110, and the system processor 112.

An input / output processor (DMAC) 103 is a master module having priority in the use of the input / output bus 105, and transfers data input through the data input / output unit 101 to the data memory 104. The data stored in the data memory 104 is transmitted to the data input / output unit 101.

The data memory 104 stores data received from the data input / output unit 101 and data transmitted through the bus switch 106 through a predetermined process in the hardware module 113. In this case, the data memory 104 preferably uses synchronous dynamic random access memory (SDRAM).

The input / output bus 105 transfers the data input from the data input / output unit 101 to the data memory 104 or transmits the data stored in the data memory 104 to the input / output unit 101 or the bus switch 106. It serves as a passage to the system bus 108 through.

The bus switch 106 connects the system bus 108 to the program bus 107 or the input / output bus 105 under the control of the microprocessor 110.

The program bus 107 serves as a passage for delivering a program that the microprocessor 110 uses to control each module.

The system bus 108 transfers control signals and data stored in the data memory 104 of the bus masters, i.e., the input / output processor 103, the microprocessor 110, and the system processor 112. Acts as a pathway.

The program memory 109 stores a program used by the microprocessor 110 to control each module.

The microprocessor 110 controls the bus switch 106 for connecting the system bus 108 with the input / output bus 105 or the program bus 107, and also by using a program stored in the program memory 109. Control each module.

The system bus mediator 111 arbitrates bus usage rights between the microprocessor 110 and the system processor 112 that wish to use the system bus 108.

A system processor (DMAC) 112 obtains a system bus license and an image I / O bus license from the system bus mediator 111 and the I / O bus mediator 102, respectively, and the data memory 104. In this case, the data stored in the C / D is transferred to the hardware module 113 or the data processed by the hardware module 113 is transferred to the data memory 104.

The hardware module 113 decodes or encodes image data received from the system processor 112.

2 is a configuration diagram of an image processing apparatus having a multi-layer bus structure according to the present invention.

The components and operations of the image processing apparatus having the multi-layer bus structure according to the present invention will be described below.

First, the image input / output bus 201 transfers the image data received from the image input / output unit 21 to the data memory 24 or transfers the image data stored in the data memory 24 to the image input / output unit 21 or the bus. It serves to deliver to the system bus 202 via the switch 204.

The image input / output unit 21 receives image data from the outside or outputs image data that has undergone a predetermined process to the outside.

The input / output bus arbiter 22 arbitrates the bus master module for using the input / output bus 201, that is, the bus right of the input / output processor 23, the microprocessor 29, and the system processor 31.

An input / output processor (DMAC) 23 is a master module having priority in the use of the input / output bus 201, and outputs image data input through the image data input / output unit 21 to the data memory 24. The image data stored in the data memory 24 is transferred to the image input / output unit 21.

The data memory 24 includes image data received through the image input / output unit 21 and image data received through a predetermined process from the peripheral hardware module 37, the encoding hardware module 27, or the decoding hardware module 33. Save it. At this time, it is preferable that the data memory 24 use synchronous dynamic random access memory (SDRAM).

The bus switch 204 connects the system bus 202 to the program bus 203 or the input / output bus 201 under the control of the microprocessor 29.

The program bus 203 serves as a passage for delivering a program that the microprocessor 29 uses to control each module.

Peripheral interface 32 handles the interface with peripheral bus 205.

The address analyzer 25 analyzes the addresses of the encoding hardware module 27 and the decoding hardware module 33.

The reset controller 26 restarts (resets) the image processing apparatus.

The encoding hardware module 27 encodes image data received from the system processor 31.

The program memory 28 stores a program that the microprocessor 29 uses to control each module.

The microprocessor 29 controls the bus switch 204 to connect the system bus 202 with the image input / output bus 201 or the program bus 203.

System bus arbitrator 30 arbitrates the system bus usage rights between the microprocessor 29 and the system processor 31 that act as masters on the system bus 202.

The system processor (DMAC) 31 is the system after the bus switch 204 connects the image input / output bus 201 and the system bus 202 under the control of the microprocessor 29. A system bus license and a video I / O bus license are obtained from the bus intermediator 30 and the input / output bus mediator 22, respectively, and the image data stored in the data memory 24 is encoded by the encoding hardware module 27 and the decoding hardware. Transfer to module 33.

The decoding hardware module 33 decodes the image data received from the system processor 31.

The interrupt controller 34 controls the system interrupt of the peripheral hardware module 37.

The remap / stop controller 35 generates a control signal for stopping the operation of the image processing apparatus or storing data stored in the ROM area to the RAM area.

The timer 36 checks the time.

The peripheral hardware module 37 processes the image data received from the system processor 31 through the peripheral interface 32.

Peripheral bus 205 serves as a path for data transmission with peripherals.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention as described above, the bus input and bus bus for separating the input and output bus and the system bus for the data transfer and the program bus for the transfer of the program and connecting each bus and the bus to mediate the use of each bus The controller controlling the arbiter and each of the modules controls each bus to operate independently, thereby rapidly processing a large amount of data.

In addition, when the present invention is applied to an image processing apparatus having a multi-layer bus structure, it is easy to increase or decrease the bus hierarchy according to the design specification of the multimedia application field, and accordingly, it is possible to design a multimedia system with flexibility and expandability. There is.

Claims (2)

In the multilayer bus controller, Multiple buses for transferring data; Bus connection means for interconnecting the plurality of buses under control of a control means; Bus arbitration means for arbitrating a usage right of each bus so that each bus operates independently of each other; Data processing means for processing data transmitted through each bus; And The control means for controlling the bus connecting means to interconnect the plurality of buses Multi-layer bus control device comprising a. The method of claim 1, The multi-layer bus control apparatus is implemented in a system on-chip chip processor.

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