KR100587644B1 - Effective Input signal generator - Google Patents

Abstract

The present invention discloses a circuit for generating a chip-to-chip signal that can reduce power consumption in a source driver using a low voltage differential signaling interface.

The present invention provides a liquid crystal display device comprising an Nth source driver and an N + 1th source driver, wherein the N + 1th source driver is enabled by an EI signal generated from the Nth source driver to provide an LVDS signal in series. An LVDS interface circuit for inputting and converting the signal into a logic level signal; A valid EI signal generator for inputting the EI signal and a clock signal to generate a valid EI signal for controlling a continuous valid input signal between an Nth source driver and an N + 1th source driver to be provided; Delay means for delaying the output signal of the effective EI signal generator by a predetermined time; Shift register means for generating a predetermined output signal through each shift register in response to an output signal and a clock signal of the delay means; And latch means for storing, in each latch, data input through the LVDS interface circuit in accordance with an output signal output from each shift register of the shift register means.

LCD, Low Voltage, Differential, Signaling, Interface, Source Driver

Description

Effective Input Signal Generator             

1 is a configuration diagram of a liquid crystal display device having a plurality of source drivers according to the related art;

2 is an operation waveform diagram of a source driver of the liquid crystal display shown in FIG. 1;

3 is a configuration diagram of a liquid crystal display device having a plurality of source drivers according to an embodiment of the present invention;

4 is a detailed view of an effective input signal generation circuit used in a source driver in a liquid crystal display device according to an embodiment of the present invention;

5 is an operation waveform diagram of a source driver of the liquid crystal display shown in FIG. 3;

* Description of the symbols for the main parts of the drawings *

100: Nth source driver 200: N + 1th source driver

110, 210: LVDS interface circuit 120, 220: shift register means

130, 230: latch means 140, 240: logic portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a circuit for generating a chip-to-chip signal in a source driver using a low voltage differential signaling interface. It is about.

FIG. 1 is a block diagram of a liquid crystal display having a source driver of a conventional low voltage differential signaling (LVDS) interface. 1 shows that two source drivers 100 and 200 are attached to a liquid crystal panel, and the configuration of each source driver 100 and 200 is schematically illustrated.

Referring to FIG. 1, each source driver 100, 200 includes a mini low voltage differential signaling interface circuit 110 and 210, a shift register means 120 and 220, and a latch. Means 130 and 230 and logic portions 140 and 240.

The N-th source driver 100 further includes an EI signal generator 150 for generating a signal EI transferred from chip to chip. The EI signal is a control signal for continuously providing data to the Nth source driver 100 and the N + 1th source driver 200, and the valid input data is stably provided to the N + 1th source driver 200. Signal to control to be supplied.

The N + 1 th source driver 200 further includes a delay means 250 for delaying the EI signal generated by the EI signal generator 150 of the N th source driver 100 by one clock.

The operation of the source driver having the above configuration will be described below with reference to the operation waveform diagram of FIG. 2.

In the Nth source driver 100, an output signal from which the first to the 76th clock signals are input and the data input through the interface circuit 100 are output from each shift register SR of the shift register means 120. After being stored in each latch LA of the latch means 130 by EN1 through EN77, when the 77th clock signal is applied, the EI signal generator 150 generates the EI signal EI (N).

The EI signal generator 150 generates a high level EI (N) signal until the first valid input signal is applied to the N + 1 th source driver 200 in synchronization with the rising edge of the 77 th clock signal CLK. Occurs. This is performed by driving the LVDS bias circuit 111 of the interface circuit 110 before the first valid input signal D1 is provided to the N + 1 th source driver 200 to obtain the bias voltage of the LVDS receiver 112. To enable it.

Therefore, conventionally, when the EI signal EI (N) having a width of 4 clock cycles is generated through the EI signal generator 150 in the Nth source driver 100, the EI signal is generated by the N + 1th source driver 200. It acts as a data enable signal DEN of the LVDS bias circuit 211 and is simultaneously provided to 80 shift registers SR of the shift fp register means 220.

Therefore, as shown in Fig. 2, the shift register means 220 also has its output signals EN1, EN2, ... in accordance with the EI signal EI (N) having a width of 4 clock cycles. Generates a signal with Since the output signals EN1-EN80 of the shift register means 220 act as enable signals of the latches LA of the latch means 130, enable signals EN1-EN80 having unnecessary four clock cycles. By driving the latch means 130 and the logic unit 140, there is a big problem in power consumption. This is common to all source drivers attached to panels.

The present invention is to solve the problems of the prior art as described above, the object of the present invention is to provide an LCD source driver that can simplify the configuration and reduce the power consumption due to unnecessary data storage.

In order to achieve the above object, the present invention provides a liquid crystal display device including an Nth source driver and an N + 1th source driver, wherein the Nth source driver inputs an LVDS signal in series to convert the signal into a logic level signal. A first LVDS interface circuit, a first plurality of shift registers, a first shift register means for generating a predetermined output signal through each of said first plurality of shift registers, and a first plurality of latches First latch means for storing data input through the first LVDS interface circuit in the first plurality of latches according to an output signal output from each of the first plurality of shift registers, and the Nth source; Generate an EI signal to control the continuous valid input signal between the driver and the N + 1th source driver. And an EI signal generator, wherein the N + 1 th source driver is enabled by the EI signal and has a second LVDS interface circuit for inputting an LVDS signal in series and converting the signal into a logic level signal; A valid EI signal generator for inputting a signal and a clock signal to generate a valid EI signal for controlling a continuous valid input signal between the Nth source driver and the N + 1th source driver to be provided; Delay means for delaying the output signal by a predetermined time and a second plurality of shift registers, and generates a predetermined output signal through each of the second plurality of shift registers by the output signal and the clock signal of the delay means And a second shift register means and a second plurality of latches, each of the second plurality of shift registers. In accordance with an output signal outputted from it provides a liquid crystal display apparatus comprising a second latch means for storing in the second LVDS interface circuit to the second latch each of the plurality of data input through.

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In an embodiment of the present invention, the effective EI signal generator generates an effective EI signal having a smaller width than the EI signal.

In an embodiment of the present invention, the effective EI signal generator comprises: a first flip-flop for delaying the EI signal by a predetermined time in synchronization with the clock signal; A second flip flop for delaying an output signal of the first flip flop by a predetermined time in synchronization with the clock signal; A third flip flop for delaying an output signal of the second flip flop by a predetermined time in synchronization with the clock signal; And an AND gate for inputting an output signal of the first to third flip-flops to generate an effective EI signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.

FIG. 3 is a diagram illustrating a liquid crystal display including a source driver having a mini LVDS interface according to an exemplary embodiment of the present invention. 3 shows that two source drivers 100 and 200 are attached to a liquid crystal panel, and the configuration of each source driver 100 and 200 is schematically illustrated. The liquid crystal display device according to the embodiment of the present invention is applicable to a liquid crystal display device having at least two source drivers of at least two LVDS interface methods.

Referring to FIG. 3, the N-th source driver 100 includes an LVDS interface circuit 110, a shift register means 120, a latch means 130, and a logic unit 140. In addition, the N-th source driver 100 further includes an EI signal generator 150 for generating a signal EI transferred from chip to chip.

The N + 1 th source driver 200 includes an LVDS interface circuit 210, a shift register unit 220, a latch unit 230, and a logic unit 240. In addition, the N +! Number source driver 200 inputs an EI signal generated from the EI signal generator 150 of the Nth source driver 100 to generate an effective EI signal E_EI and an effective EI signal generator 260. And delay means 250 for delaying the effective EI signal E_EI generated by the effective EI signal generator 260 by one clock.

The LVDS interface circuit 110 of the source driver 100 is driven by a bias circuit 111 for providing a bias voltage to the LVDS receiver 112 and a bias provided from the bias circuit 111 and applied in series. And a data receiver 112 for inputting an LVDS data signal of an analog level having a predetermined amplitude and converting the signal into a logic level data signal.

Meanwhile, the LVDS interface circuit 210 of the N + 1 th source driver 200 inputs an EI signal provided from the EI signal generator 150 of the N th source driver 100 as a data enable signal and receives an LVDS receiver ( A bias circuit 111 for providing a bias voltage to the 112 and an analog level LVDS data signal having a predetermined amplitude which is driven in series by a bias provided from the bias circuit 111 and applied in series are inputted. A data receiver 112 for converting the data signal is provided.

In the source drivers 100 and 200, the configuration and operation of the register means 120, 220 and the latch means 130, 230, and the logic units 140, 240 are conventional sources. Since the same configuration and operation as those used in the driver are described, a description of the configuration and operation is omitted here.

On the other hand, the N + 1 th source driver 200 and the LVDS bias circuit 211 for providing a bias by using the EI signal generated from the EI signal generator 150 of the N th source driver 100 as a data enable signal; And an LVDS receiver 212 which is enabled by a bias provided from the bias circuit 211 and converts an analog level LVDS data input signal having a predetermined amplitude into a logic level signal.

4 illustrates an effective signal for generating a valid EI signal by inputting a clock signal CLK and an EI signal generated from the EI signal generator 150 of the N-th source driver 100 in the N + 1 th source driver 200. The detailed configuration diagram of the EI signal generator 260 is shown.

Referring to FIG. 4, a first D flip-flop 261 that generates an output signal temp1 using the clock signal CLK as a clock signal and an EI signal as an input signal, and the clock signal CLK as a clock signal And a second flip-flop 263 which generates an output signal temp2 using the output signal temp1 of the first D flip-flop 261 as an input signal, and the clock signal CLK as a clock signal. A third flip-flop 263 which generates an output signal temp3 using the output signal temp2 of the two-flop flop 262 as an input signal, and an output signal of the first to third flip-flops 261-263. An AND gate 264 for generating an effective EI signal using (temp1), (temp2) and (temp3) as three inputs is provided.

The operation of the source driver having the above configuration will be described below with reference to the operation waveform diagram of FIG. 5.

The interface circuit 110 of the N-th source driver 100 drives the LVDS receiver 112 by a bias provided from the bias circuit 111 to output an analog level LVDS input signal having an amplitude of about 200 to 600 mV. Level shift to the input signal. The level shifted input signal is enabled by each latch LA of the latch means 130 by an output signal EN1-EN80 output from each register SR of the shift register means 120 so that the LVDS receiver 212 can be used. Save the output signal.

When data is stored in the latch means 120 of the N-th source driver 110, an EI signal is generated from the N-th source driver 100 to the N + 1th source driver 200 continuously. In this case, the EI signal is used as a control signal for continuously providing data to the Nth source driver 100 and the N + 1th source driver 200 as the only signal transmitted from chip to chip. That is, after the last data D80 is provided to the Nth source driver 100, the first data D0 is continuously supplied to the N + 1th source driver 200. At this time, the first valid input data D0 of the N + 1 th source driver 200 is provided with a delay difference of one clock cycle, since the last valid data D80 of the N th source driver is shifted. It acts as a start signal for the first shift register SR. In addition, the EI signal acts as a data enable signal DEN to drive the bias circuit 211 of the LVDS interface circuit 210 to provide a bias to the LVDS receiver 212.

At this time, the DI signal generator 150 provides the first valid data D0 of the N + 1 th source driver at the rising edge of the 77 th clock signal CLK of the N th source driver 100 so that the valid data is stably supplied. Generates a signal with a width of four clock cycles, maintaining a high level (logic 1).

The N + 1 th source driver 200 operates the LVDS interface circuit 210 using the EI signal as a data enable signal, inputs an LVDS data signal, and converts the signal into a logic level signal. In addition, the effective EI signal generator 260 inputs the EI signal to generate an effective EI signal E_EI having a width of one clock cycle. That is, as illustrated in FIG. 4, the EI signal is delayed by one clock through the first to third D flip flops 261 to 263, and then the output signal temp1 of the first to third flip flops 261 to 263 is delayed. -temp3 is logic-ended through the AND gate 264 to generate an effective EI signal E_EI having a width of one clock cycle.

That is, as illustrated in FIG. 2, the time T_en for enabling each latch LA of the latch means 230 has a width of 4 clock cycles, as shown in FIG. 2. Likewise, since the time T_en at which each latch LA of the latch means 230 is enabled has a width of one clock cycle, the latch means may reduce power consumption due to unnecessary data storage.

Specifically, each latch stores two pieces of data, the first storing unnecessary data and the second storing valid data. Therefore, in the related art, a total of five data are stored in each latch, of which four data are unnecessary data and only one data is needed. On the other hand, in the present invention, a total of two data are stored, one unnecessary data and one necessary data. Therefore, in the present invention, since unnecessary data is stored four times, unnecessary data is stored only once in the present invention, and thus power consumption may be reduced according to a decrease in the number of unnecessary data storage.

In Fig. 5, T_set_up represents the setup time of the enable signal DEN of the bias circuit 211 with respect to the valid input signal of the (N + 1) th source driver 200, and EN1, EN2 .. are shift register means. As an output signal of each shift register SR of 120 and 220, it acts as an enable signal of each latch LA of the latch means 130 and 230. As shown in FIG. t1 represents the time at which the first valid data of the N + 1th source driver is input, and CLK is a system clock inside the source driver.

As described above, the source driver generates an effective EI signal for storing tag data by using the EI signal generated from the Nth source driver, thereby solving the problem of power consumption due to unnecessary data storage.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (3)

A liquid crystal display device comprising an Nth source driver and an N + 1th source driver, The N-th source driver may include: a first LVDS interface circuit configured to input an LVDS signal in series and convert the LVDS signal into a logic level signal; First shift register means having a first plurality of shift registers and generating a predetermined output signal through each of said first plurality of shift registers; A first latch having a first plurality of latches and storing data input through the first LVDS interface circuit in the first plurality of latches according to an output signal output from each of the first plurality of shift registers; Way; And An EI signal generator for generating an EI signal for controlling a continuous valid input signal between the Nth source driver and the N + 1th source driver to be provided; The N + 1 th source driver is, A second LVDS interface circuit which is enabled by the EI signal and converts the LVDS signal in series into a logic level signal; A valid EI signal generator for inputting the EI signal and a clock signal to generate a valid EI signal for controlling a continuous valid input signal between the Nth source driver and the N + 1th source driver to be provided; Delay means for delaying the output signal of the effective EI signal generator by a predetermined time; A second shift register means comprising a second plurality of shift registers and generating a predetermined output signal through each of the second plurality of shift registers by an output signal and a clock signal of the delay means; And A second latch having a second plurality of latches and storing data input through the second LVDS interface circuit in each of the second plurality of latches according to an output signal output from each of the second plurality of shift registers; A liquid crystal display device comprising means. The method of claim 1, And the effective EI signal generator generates an effective EI signal having a smaller width than the EI signal. The method of claim 1, The effective EI signal generator A first flip-flop for delaying the EI signal by a predetermined time in synchronization with the clock signal; A second flip flop for delaying the output signal of the first flip flop by a predetermined time in synchronization with the clock signal; A third flip flop for delaying an output signal of the second flip flop by a predetermined time in synchronization with the clock signal; And And an AND gate configured to input an output signal of the first to third flip-flops to generate an effective EI signal.

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