KR100586587B1 - Pipelined successive interference canceller for code division multiple access system - Google Patents

Abstract

The present invention is to provide a pipelined serial interference canceller for code division multiple access system that can reduce the decoding delay without increasing the bit error rate in the structure consisting of a plurality of stages through the pipeline. The present invention provides a serial interference canceller pipelined to a plurality of stages, the serial interference canceller comprising: power ranking means for ranking received signals received through a channel in response to received signal power of each user; Time delay means for sequentially delaying the received signal by a predetermined time through a unit delay unit corresponding to the number of stages in the pipeline; Each user for performing a spreading operation in response to a time delay, an estimate of a phase offset, and a spreading code in response to the power ranking information output from the power ranking means, and outputting a regenerated signal via a soft decision and a hard decision function. Unit interference cancellers as many as stages of the pipeline; And a plurality of first accumulating means for filtering only a signal of a corresponding user from delayed received signals respectively output from the unit delay units of the time delay means, wherein interference is removed from each of the plurality of first accumulating means. And a signal is output and input to the unit interference canceller of the next stage of the user.

Code Division Multiple Access System, Pipeline, Series Interference Canceller, Soft Decision, Hard Decision

Description

PIPELINED SUCCESSIVE INTERFERENCE CANCELLER FOR CODE DIVISION MULTIPLE ACCESS SYSTEM}             

1 is a block diagram of a pipelined serial interference canceller in accordance with an embodiment of the present invention.

2 is an internal block diagram of a unit interference canceller corresponding to a j th stage of an i th user;

3 is a graph of soft decision and hard decision functions for the provisional decision of the provisional decision section.

FIG. 4 conceptually illustrates the pipelined serial interference canceller comprised of a conventional multiple stage as in the present invention.

* Description of the main parts of the drawing

100: power ranker 110: time delay unit

ICU: unit interference canceller 120, 200,: accumulator

201, 240: division and integrator

220: matching filter 230: temporary judgment unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple access system, and more particularly, to an interference cancellation unit for efficiently removing multiple access interference inevitably occurring in a code division multiple access system.

Currently used mobile communication standards IS (Interim Standard) -95 and IMT (International Mobile Telecommunication) -2000 adopt a code division multiple access scheme as a multiple access scheme, inevitably causes a problem of multiple access interference. The interference canceller is for removing such multiple access interference.

In general, an interference canceller for canceling multiple access interference is divided into a serial interference canceller (SIC) and a parallel interference canceller (PIC) according to its structure.

In particular, the serial interference canceller performs good interference in a multipath fading environment by performing the interference cancellation after sequentially receiving the received signal power of each user in a large order. However, the decoding delay is a big disadvantage when composed of multiple stages.

On the other hand, the parallel interference canceller has a relatively small decoding delay in the case of a plurality of stages, but performs interference cancellation without considering the magnitude of the received signal power.

The present invention has been made to solve the above problems, and pipelined serial for code division multiple access system, which can reduce the decoding delay without increasing the bit error rate in a structure composed of multiple stages through pipelined Its purpose is to provide an interference canceller.

The present invention for achieving the above object is, in the serial interference canceller pipelined to a plurality of stages, power ranking means for ranking the received signal received through the channel in response to the received signal power of each user ; Time delay means for sequentially delaying the received signal by a predetermined time through a unit delay unit corresponding to the number of stages in the pipeline; Each user for performing a spreading operation in response to a time delay, an estimate of a phase offset, and a spreading code in response to the power ranking information output from the power ranking means, and outputting a regenerated signal via a soft decision and a hard decision function. Unit interference cancellers as many as stages of the pipeline; And a plurality of first accumulating means for filtering only a signal of a corresponding user from delayed received signals respectively output from the unit delay units of the time delay means, wherein interference is removed from each of the plurality of first accumulating means. And a signal is output and input to the unit interference canceller of the next stage of the user.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 1 is a block diagram illustrating a pipelined serial interference canceller according to an embodiment of the present invention, and illustrates a case where the number of users is six and the number of pipelines is four.

As shown in FIG. 1, the pipelined serial interference canceller according to an embodiment of the present invention ranks the received signal r (t) first through the channel in response to the received signal power of each user. Determining power ranker 100, from the time delay unit 110, the power ranker 100 for sequentially delaying the received signal (r (t)) by a predetermined time T _b through the four unit delay unit Regeneration through spreading operation and soft decision and hard decision function according to time delay τ _k , estimate of phase offset φ _k and spread code c _k (t) in response to output power ordering information Filters only the user's signal from the unit interference canceller (ICU) and the delayed received signal (r (t)) output from the unit delay unit of the time delay unit 110 as many pipelines as the user outputs the signal. Multiple accumulators (120) for The signal from which the interference is removed is output from the accumulator 120 and input to the unit interference canceller (ICU) of the next stage of the user.

An internal block diagram of a specific unit interference canceller (ICU) is shown in FIG.

2 is an internal block diagram of the unit interference canceller corresponding to the j th stage of the i th user, i is the index of the user, and j is the index of the stage.

)와 누적기(120)로부터 출력되는 간섭이 제거된 신호(

)를 입력받아 누산하여 i번째 사용자의 신호만을 걸러내기 위한 누적기(200), 상기 누적기(200)로부터 출력되는 합성 신호(

)와 전력순위기(100)의 전력순위정보에 응답된 i번째 사용자의 확산 코드(c_i(t-τ_i)[cosφ_i/sinφ_i])를 곱한 후 한 주기동안 적분하여 합성 신호(

)를 역확산하는 제산 및 적분기(210), 역확산된 합성 신호를 입력받아 i번째 사용자의 확산 코드 방향으로의 신호만을 걸러내기 위한 정합 여파기(Matched filter)(220), 상기 정합 여파기(220)로부터 출력되는 결정 변수

에 대해 연판정 또는 경판정 함수를 수행하는 임시 판정을 위한 임시 판정부(230) 및 상기 임시 판정부(230)로부터 출력된 신호와 전력순위기(100)의 전력순위정보에 응답된 i번째 사용자의 확산 코드(c_i(t-τ_i)[cosφ_i/sinφ_i])를 곱한 후 한 주기동안 적분하여 재확산 동작을 통해 다음 스테이지, 즉 (j+1)번째 스테이지의 입력이 되는 재생성 신 호(

)를 출력하는 제산 및 적분기(240)로 이루어진다. 여기서, 해당 ICU가 최종 스테이지일 경우 정합 여파기(220)로부터 출력된 결정 변수

는 그대로 경판정 장치(도면에 도시되지 않음)로 보내지게 된다.As shown in FIG. 2, the unit interference canceller of the present invention includes a regenerated signal output from a previous stage, that is, the (j-1) th stage.

) And the signal from which the interference output from the accumulator 120 is removed (

), An accumulator 200 for filtering and accumulating only the signal of the i-th user, and a synthesized signal output from the accumulator 200 (

) Is multiplied by the i-th user's spreading code c _i (t-τ _i ) [cosφ _i / sinφ _i ] in response to the power rank information of the power ranker 100, and then integrated for one period to integrate the synthesized signal (

Division and integrator 210 for despreading), a matched filter 220 for filtering only the signal in the direction of spreading code of the i-th user by receiving the despread composite signal, and the matched filter 220 Variables output from

The i-th user who responds to the temporary decision unit 230 for the temporary decision that performs the soft decision or hard decision function with respect to the signal output from the temporary decision unit 230 and the power rank information of the power ranker 100. Multiply by the spreading code (c _i (t-τ _i ) [cosφ _i / sinφ _i ]) and integrate for one period to regenerate the regenerated scene, which is the input of the next stage, i.e. number(

) And a divider and an integrator 240 to output. Here, the decision variable output from the matching filter 220 when the ICU is the final stage.

Is sent directly to the hard decision device (not shown in the figure).

1 and 2, the signal r (t) first received through the channel is determined by the power ranker 100 according to the received signal power of each user. In order to determine the ranking, the spreading code of each user should be input to the power ranker 100, and the power rank information, which is an output, is transmitted to the unit interference canceller (ICU) as many as the number of pipelines per user. The unit interference canceller (ICU) estimates the time delay τ _k , the phase offset φ _k inputted to each user's unit interference canceller (ICU) by the power rank information from the power ranker 100, and the spreading code. c _k (t) will determine the type.

)는 제산 및 적분기(210)에서 i번째 사용자의 확산 코드(c_i(t-τ_i)[cosφ_i/sinφ_i])에 의해 역확산(despread)이 이루어지며, 상기 역확산된 신호는 정합 여파기(220)의 입력이 된다. 따라서, 파이프라인화된 직렬 간섭 제거기에서 단위 간섭 제거기(ICU)는 해당 사용자의 확산 코드 방향으로의 신호만을 걸러내게 된다. 최종적으로, 정합 여파기(220)로부터 출력된 결정 변수

는 도 3에 도시된 바와 같은 연판정(도 3의 (a)) 또는 경판정 함수(도 3의 (b))를 수행하는 임시 판정을 위한 임시 판정부(230)를 통과한 후 제산 및 적분기(240)에서 재확산(respread)됨으로써 다음 스테이지, 즉 (j+1)번째 스테이지의 입력이 되는 재생 성 신호(

)를 만들게 된다. On the other hand, the composite signal (

) Is despread by the spreading code c _i (t-τ _i ) [cosφ _i / sinφ _i ] of the i th user in the division and integrator 210, and the despread signal is matched. The filter 220 is input. Thus, in a pipelined serial interference canceller, the unit interference canceller (ICU) filters out only the signal in the direction of the spreading code of the user. Finally, the decision variable output from the matched filter 220

Division and integrator after passing the temporary decision unit 230 for the temporary decision to perform the soft decision (Fig. 3 (a)) or hard decision function (Fig. 3 (b)) as shown in FIG. By respreading at 240, the regeneration signal that is input to the next stage, i.e., the (j + 1) th stage,

).

4 is a diagram conceptually illustrating a pipelined serial interference canceller composed of a plurality of conventional stages as in the present invention.

Referring to FIG. 4, it can be seen that a large decoding delay occurs in a serial interference canceller composed of multiple stages because one user is wasting time without any operation while one user is detected. As in the present invention, wasteful time can be utilized when pipelined. In other words, in the serial interference canceller composed of multiple stages, only interference by one user is eliminated every bit interval, whereas in the pipelined serial interference canceller of the present invention, interference by multiple users is detected every bit interval. This eliminates more reliable data for the next stage and gives better performance at the same decoding delay.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above has the effect of reducing the decoding delay without increasing the bit error rate while maintaining the multipath fading characteristics of the serial interference canceller.

Claims (4)

In a multi-stage pipelined serial interference canceller, Power ranking means for ranking the received signal received through the channel in response to the received signal power of each user; Time delay means for sequentially delaying the received signal by a predetermined time through a unit delay unit corresponding to the number of stages in the pipeline; Each user for performing a spreading operation in response to a time delay, an estimate of a phase offset, and a spreading code in response to the power ranking information output from the power ranking means, and outputting a regenerated signal via a soft decision and a hard decision function. Unit interference cancellers as many as stages of the pipeline; And And a plurality of first accumulating means for filtering only a signal of a corresponding user from delayed received signals respectively output from the unit delay units of the time delay means, and the signal from which interference is removed from each of the plurality of first accumulating means. And is output to be input to the unit interference canceller of a next stage of the user. The unit interference canceller of claim 1, wherein the unit interference canceller corresponding to the j th stage of an i th user of the plurality of unit interference cancellers comprises: Second accumulating means for receiving and accumulating a regenerated signal output from the (j-1) th stage, which is a previous stage, and a signal from which the interference output from the first accumulating means is removed and filtering only the signal of the i-th user; A first division for despreading the synthesized signal by multiplying the synthesized signal output from the second accumulating means and the spreading code of the i-th user responding to the power rank information from the power ranking means and integrating for one period And integrating means; Matching filter means for receiving a despread composite signal output from the first division and integration means and filtering only a signal in a direction of a spread code of the i-th user; Temporary judgment means for temporary judgment of performing a soft decision or hard decision function on the decision variable output from the matched filtering means; And Second dividing and integrating means for generating a regenerated signal by integrating for one period after multiplying the signal output from the temporary determining means and the spreading code of the i-th user responding to the power ranking information of the power ranking means; Pipelined serial interference canceller comprising a. The method of claim 2, wherein the second division and integration means, And outputting the generated regenerated signal to the next stage (j + 1) th stage. The method of claim 2, wherein the unit interference canceller corresponding to the final stage of each user, And outputting the decision variable output from the matched filtering means to the hard decision device.

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