KR100586057B1 - 프리디코드 정보를 저장하기 위해 ｅｃｃ/패리티 비트들의 이용 - Google Patents

프리디코드 정보를 저장하기 위해 ｅｃｃ/패리티 비트들의 이용 Download PDF

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KR100586057B1
KR100586057B1 KR1020007014659A KR20007014659A KR100586057B1 KR 100586057 B1 KR100586057 B1 KR 100586057B1 KR 1020007014659 A KR1020007014659 A KR 1020007014659A KR 20007014659 A KR20007014659 A KR 20007014659A KR 100586057 B1 KR100586057 B1 KR 100586057B1
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cache
predecode
instruction
information
level
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Korean (ko)
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KR20010025123A (ko
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마하링가이아루파카
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Detection And Correction Of Errors (AREA)
  • Executing Machine-Instructions (AREA)
KR1020007014659A 1998-06-24 1999-01-25 프리디코드 정보를 저장하기 위해 ｅｃｃ/패리티 비트들의 이용 Expired - Lifetime KR100586057B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/103,956 1998-06-24
US09/103,956 US6092182A (en) 1998-06-24 1998-06-24 Using ECC/parity bits to store predecode information

Publications (2)

Publication Number Publication Date
KR20010025123A KR20010025123A (ko) 2001-03-26
KR100586057B1 true KR100586057B1 (ko) 2006-06-07

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KR1020007014659A Expired - Lifetime KR100586057B1 (ko) 1998-06-24 1999-01-25 프리디코드 정보를 저장하기 위해 ｅｃｃ/패리티 비트들의 이용

Country Status (6)

Country Link
US (1) US6092182A (https=)
EP (1) EP1090345B1 (https=)
JP (1) JP3836322B2 (https=)
KR (1) KR100586057B1 (https=)
DE (1) DE69902392T2 (https=)
WO (1) WO1999067705A1 (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6401118B1 (en) * 1998-06-30 2002-06-04 Online Monitoring Services Method and computer program product for an online monitoring search engine
US6460132B1 (en) * 1999-08-31 2002-10-01 Advanced Micro Devices, Inc. Massively parallel instruction predecoding
US6463506B1 (en) * 2000-04-29 2002-10-08 Hewlett-Packard Company Arrangement of data within cache lines so that tags are first data received
WO2002043065A2 (en) * 2000-11-27 2002-05-30 T.T.R. Technologies Ltd. A copy protected dvd disc and method for producing and validating same
US6804799B2 (en) 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache
US7043679B1 (en) 2002-06-27 2006-05-09 Advanced Micro Devices, Inc. Piggybacking of ECC corrections behind loads
US7415638B2 (en) * 2004-11-22 2008-08-19 Qualcomm Incorporated Pre-decode error handling via branch correction
US7421568B2 (en) * 2005-03-04 2008-09-02 Qualcomm Incorporated Power saving methods and apparatus to selectively enable cache bits based on known processor state
US7945763B2 (en) * 2006-12-13 2011-05-17 International Business Machines Corporation Single shared instruction predecoder for supporting multiple processors
US8001361B2 (en) * 2006-12-13 2011-08-16 International Business Machines Corporation Structure for a single shared instruction predecoder for supporting multiple processors
US20080148020A1 (en) * 2006-12-13 2008-06-19 Luick David A Low Cost Persistent Instruction Predecoded Issue and Dispatcher
US7840786B2 (en) * 2007-04-16 2010-11-23 Advanced Micro Devices, Inc. Techniques for storing instructions and related information in a memory hierarchy
US8898437B2 (en) * 2007-11-02 2014-11-25 Qualcomm Incorporated Predecode repair cache for instructions that cross an instruction cache line
US7814300B2 (en) 2008-04-30 2010-10-12 Freescale Semiconductor, Inc. Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
US8145985B2 (en) 2008-09-05 2012-03-27 Freescale Semiconductor, Inc. Error detection schemes for a unified cache in a data processing system
US8291305B2 (en) * 2008-09-05 2012-10-16 Freescale Semiconductor, Inc. Error detection schemes for a cache in a data processing system
US8356239B2 (en) * 2008-09-05 2013-01-15 Freescale Semiconductor, Inc. Selective cache way mirroring
US8316186B2 (en) * 2008-09-20 2012-11-20 Freescale Semiconductor, Inc. Method and apparatus for managing cache reliability based on an associated error rate
US8364896B2 (en) * 2008-09-20 2013-01-29 Freescale Semiconductor, Inc. Method and apparatus for configuring a unified cache based on an associated error rate
US8266498B2 (en) * 2009-03-31 2012-09-11 Freescale Semiconductor, Inc. Implementation of multiple error detection schemes for a cache
US9608826B2 (en) 2009-06-29 2017-03-28 Jpmorgan Chase Bank, N.A. System and method for partner key management
US9218286B2 (en) * 2012-09-27 2015-12-22 Apple Inc. System cache with partial write valid states
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
US9348598B2 (en) 2013-04-23 2016-05-24 Arm Limited Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry
US9710324B2 (en) 2015-02-03 2017-07-18 Qualcomm Incorporated Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC
US10296416B2 (en) * 2016-07-02 2019-05-21 Intel Corporation Read from memory instructions, processors, methods, and systems, that do not take exception on defective data
US10291258B2 (en) 2017-05-25 2019-05-14 Advanced Micro Devices, Inc. Error correcting code for correcting single symbol errors and detecting double bit errors
US12353881B2 (en) * 2020-09-26 2025-07-08 Intel Corporation Circuitry and methods for power efficient generation of length markers for a variable length instruction set

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651324A1 (en) * 1993-10-29 1995-05-03 Advanced Micro Devices, Inc. Speculative instruction queue for variable byte length instructions
EP0798632A2 (en) * 1996-03-25 1997-10-01 Sun Microsystems, Inc. Branch prediction method and apparatus in a multi-level cache system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747043A (en) * 1984-02-10 1988-05-24 Prime Computer, Inc. Multiprocessor cache coherence system
JPS62151971A (ja) * 1985-12-25 1987-07-06 Nec Corp マイクロ・プロセツサ装置
US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system
US5265004A (en) * 1991-10-15 1993-11-23 Allen-Bradley Company, Inc. Sequence controller with combinatorial Boolean logic
EP0651321B1 (en) * 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superscalar microprocessors
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5721854A (en) * 1993-11-02 1998-02-24 International Business Machines Corporation Method and apparatus for dynamic conversion of computer instructions
US5752264A (en) * 1995-03-31 1998-05-12 International Business Machines Corporation Computer architecture incorporating processor clusters and hierarchical cache memories
US5828895A (en) * 1995-09-20 1998-10-27 International Business Machines Corporation Methods and system for predecoding instructions in a superscalar data processing system
US5819067A (en) * 1996-02-23 1998-10-06 Advanced Micro Devices, Inc. Computer system configured to translate a computer program into a second computer program prior to executing the computer program
US5748978A (en) * 1996-05-17 1998-05-05 Advanced Micro Devices, Inc. Byte queue divided into multiple subqueues for optimizing instruction selection logic

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651324A1 (en) * 1993-10-29 1995-05-03 Advanced Micro Devices, Inc. Speculative instruction queue for variable byte length instructions
EP0798632A2 (en) * 1996-03-25 1997-10-01 Sun Microsystems, Inc. Branch prediction method and apparatus in a multi-level cache system

Also Published As

Publication number Publication date
DE69902392D1 (de) 2002-09-05
DE69902392T2 (de) 2003-03-20
EP1090345B1 (en) 2002-07-31
WO1999067705A1 (en) 1999-12-29
EP1090345A1 (en) 2001-04-11
JP2002519755A (ja) 2002-07-02
KR20010025123A (ko) 2001-03-26
JP3836322B2 (ja) 2006-10-25
US6092182A (en) 2000-07-18

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