KR100581810B1 - Light Emitting Display and Driving Method Thereof - Google Patents

Abstract

The present invention relates to a light emitting display device and a driving method thereof for reducing the number of output lines of a data driver.

The light emitting display device of the present invention includes a scan driver for sequentially supplying a scan signal to a scan line, a plurality of output lines, and data for supplying a plurality of data signals to respective output lines during the period in which the scan signal is supplied. An image display unit including a driver, a plurality of pixels located in an area partitioned by the scan line and the data line, and supplying a data signal provided to each output line and supplied to the output line to the plurality of data lines And de-multiplexers including a plurality of data transistors, and initializers including a plurality of initialization transistors for applying a predetermined voltage to the plurality of data lines.

According to this configuration, the desired data signal can be supplied to the pixels by turning on the initialization transistor until the data transistor connected to the same data line as the initialization transistor is turned on.

Description

Light Emitting Display and Driving Method Thereof             

1 illustrates a general light emitting display device.

2 is a diagram illustrating a light emitting display device according to a first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a first embodiment of the demultiplexer illustrated in FIG. 2.

4 is a circuit diagram illustrating a first embodiment of the pixel illustrated in FIG. 2.

FIG. 5 is a circuit diagram illustrating a state in which the demultiplexer and the pixel illustrated in FIGS. 3 and 4 are combined.

FIG. 6 is a waveform diagram illustrating driving waveforms supplied to the demultiplexer and the pixel illustrated in FIG. 5.

FIG. 7 is a circuit diagram illustrating a second embodiment of the pixel illustrated in FIG. 2.

FIG. 8 is a circuit diagram illustrating a state in which the demultiplexer and the pixel illustrated in FIGS. 3 and 7 are combined.

FIG. 9 is a waveform diagram illustrating driving waveforms supplied to the demultiplexer and the pixel illustrated in FIG. 8.

10 is a diagram illustrating a light emitting display device according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating an initialization unit illustrated in FIG. 10.

FIG. 12 is a diagram illustrating a state in which an initialization unit illustrated in FIG. 10 is installed adjacent to a demultiplexer.

FIG. 13 is a circuit diagram illustrating a state in which the demultiplexer, the initialization unit, and the pixels illustrated in FIGS. 4 and 12 are combined.

FIG. 14 is a waveform diagram illustrating driving waveforms supplied to the demultiplexer and the pixel illustrated in FIG. 13.

FIG. 15 is a circuit diagram illustrating a state in which the demultiplexer, the initialization unit, and the pixels illustrated in FIGS. 7 and 12 are combined.

FIG. 16 is a waveform diagram illustrating driving waveforms supplied to the demultiplexer, the initialization unit, and the pixels illustrated in FIGS. 13 and 15.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: image display unit 142,144: pixel circuit

40,140,142R, 142G, 142B, 144R, 144G, 144B: Pixel

50,150: timing control unit 160: demultiplexer block unit

162: demultiplexer 170: demultiplexer control unit

200: initialization block unit 202: initialization unit

The present invention relates to a demultiplexer, a light emitting display device using the same, and a driving method thereof. More particularly, the present invention relates to a demultiplexer, a light emitting display device using the same, and a method of driving the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device uses a thin film transistor (TFT), which is formed for each pixel, to supply light corresponding to a data signal to the light emitting device to emit light from the light emitting device.

1 is a view illustrating a conventional general light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm, and scan lines ( A timing controller for controlling the scan driver 10 for driving S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, and the scan driver 10 and the data driver 20. 50 is provided.

The scan driver 10 generates a scan signal in response to the scan drive control signals SCS from the timing controller 50, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 10 generates a light emission control signal in response to the scan drive control signals SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En.

The data driver 20 generates data signals in response to the data driving control signals DCS from the timing controller 50, and supplies the generated data signals to the data lines D1 to Dm. In this case, the data driver 20 supplies data signals of one horizontal line to the data lines D1 to Dm every one horizontal period.

The timing controller 50 generates the data drive control signal DCS and the scan drive control signals SCS in response to the synchronization signals supplied from the outside. The data driving control signals DCS generated by the timing controller 50 are supplied to the data driver 20, and the scan driving control signals SCS are supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The image display unit 30 receives the first power source VDD and the second power source VSS from the outside. Here, the first power source VDD and the second power source VSS are supplied to the respective pixels 40. Each of the pixels 40 displays an image corresponding to the data signal. In addition, the emission time of the pixels 40 is controlled in response to the emission control signal.

In the conventional light emitting display device driven as described above, each of the pixels 40 is positioned at an intersection of the scan lines S1 to Sn and the data lines D1 to Dm. Here, the data driver 20 includes m output lines to supply a data signal to each of the m data lines D1 to Dm. That is, in the conventional light emitting display device, the data driver 20 should have the same number of output lines as the data lines D1 to Dm. Accordingly, a plurality of data integrated circuits are included in the data driver 20 so that m output lines are provided, thereby increasing a manufacturing cost. In particular, as the resolution and inch of the image display unit 30 become larger, the data driver 20 includes more output lines, thereby further increasing the manufacturing cost.

Accordingly, an object of the present invention is to provide a light emitting display device and a method of driving the same, which can reduce the number of output lines of a data driver.

In order to achieve the above object, the first aspect of the present invention includes a scan driver for sequentially supplying a scan signal to a scan line, a plurality of output lines and a plurality of output lines to each output line during the period in which the scan signal is supplied. A data display unit for supplying a data signal, an image display unit including a plurality of pixels located in a region partitioned by the scan line and the data line, and a data signal provided to each output line and supplied to the output line. A demultiplexer including a plurality of data transistors for supplying a plurality of data lines and an initialization unit including a plurality of initialization transistors for applying a predetermined voltage to the plurality of data lines are provided. .

Preferably, each of the pixels has a plurality of transistors, at least one of which is connected for use as a diode element. And a demultiplexer controller for controlling the demultiplexer so that a plurality of data signals supplied to each of the output lines are supplied to the plurality of data lines. The number of data transistors included in each of the demultiplexers and the number of initialization transistors included in each of the initialization units is set to be the same. The demultiplexer controller supplies a control signal to sequentially turn on the plurality of data transistors during the period in which the scan signal is supplied. The demultiplexer controller supplies an initialization control signal to turn on the initialization transistors before the data transistors are turned on.

According to a second aspect of the present invention, demultiplexers including a plurality of data transistors are provided for each output line of each data driver to supply a plurality of data signals supplied to the output line to the plurality of data lines, and a predetermined power source. A demultiplexing circuit including initialization units including a plurality of initialization transistors for supplying the plurality of data lines is provided.

Preferably, the number of data transistors included in each of the demultiplexers and the number of initialization transistors included in each of the initialization units are set equally. Data transistors included in each of the demultiplexers are sequentially turned on to supply the plurality of data signals to the plurality of data lines. Each initialization transistor included in the initialization unit is turned on before the data transistors and is turned off at different times.

According to a third aspect of the present invention, there is provided a method of sequentially supplying scan signals to a plurality of scan lines, supplying a plurality of data signals to output lines of respective data drivers while the scan signals are supplied, and each of the output lines. Supplying the plurality of data signals to the plurality of data lines while the plurality of data transistors are sequentially turned on, and the initialization transistors connected to the plurality of data lines before the data transistors are turned on. A method of driving a light emitting display device, the method comprising: turning on to supply a voltage of an initialization power supply to the plurality of data lines.

Preferably, the initialization transistors are turned off at different times.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIG. 2 to FIG. 16 that can be easily implemented by those skilled in the art.

2 is a diagram illustrating a light emitting display device according to a first embodiment of the present invention.

2, the light emitting display device according to the first embodiment of the present invention includes a scan driver 110, a data driver 120, an image display unit 130, a timing controller 150, a demultiplexer block unit 160, The demultiplexer controller 170 is provided.

The image display unit 130 includes a plurality of pixels 140 positioned in an area partitioned by the scan lines S1 to Sn and the second data lines DL1 to DLm. Each of the pixels 140 generates light corresponding to a data signal supplied from the second data line DL.

The scan driver 110 generates a scan signal in response to the scan drive control signals SCS supplied from the timing controller 150, and sequentially supplies the generated scan signals to the scan lines S1 to Sn. In addition, the scan driver 110 generates a light emission control signal in response to the scan drive control signals SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En.

The data driver 120 generates data signals in response to the data driving control signals DCS supplied from the timing controller 150, and supplies the generated data signals to the first data lines D1 to Dm / i. . Here, each of the first data lines D1 to Dm / i is provided for each output line of the data driver 120, and the data driver 120 each first data for each period (1 horizontal period) in which the scan signal is supplied. I (i is a natural number of two or more) data signals are supplied to the lines D1 to Dm / i.

The timing controller 150 generates data driving control signals DCS and scan driving control signals SCS in response to synchronization signals supplied from the outside. The data driving control signals DCS generated by the timing controller 150 are supplied to the data driver 120, and the scan driving control signals SCS are supplied to the scan driver 110. In addition, the timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The demultiplexer block unit 160 includes m / i demultiplexers 162. In other words, the demultiplexer block unit 160 includes the same number of demultiplexers 162 as the first data lines D1 to Dm / i, and each demultiplexer 162 includes the first data lines D1 to Dm / i. i) connected to each.

Each of the demultiplexers 162 is connected to i second data lines DL. The demultiplexer 162 sequentially supplies the data signals supplied to the first data line D to the i second data lines DL every one horizontal period. That is, the demultiplexer 162 supplies the data signal supplied to one first data line D to the i second data lines DL. As such, when the data signal supplied to one first data line D is supplied to the i second data lines DL, the number of output lines included in the data driver 120 is drastically reduced. For example, assuming i is 3, the number of output lines included in the data driver 120 is reduced to about 1/3 of the conventional level, and thus the number of data integrated circuits included in the data driver 120 is reduced. Will be. That is, in the present invention, the manufacturing cost can be reduced by supplying the data signals supplied to one first data line D to the i second data lines DL using the demultiplexer 162.

The demultiplexer control unit 170 supplies i control signals to each of the demultiplexers 162 every horizontal period. That is, the demultiplexer controller 170 supplies i control signals such that a data signal supplied to one first data line D is supplied to i second data lines DL. Here, although the demultiplexer controller 170 is illustrated as being installed outside the timing controller 150, in the embodiment of the present invention, the demultiplexer controller 170 may be installed inside the timing controller 150.

FIG. 3 is a diagram illustrating an internal circuit diagram of the demultiplexer illustrated in FIG. 2. In FIG. 3, i is assumed to be 3 for convenience of description. It is assumed that the demultiplexer shown in FIG. 3 is a demultiplexer connected to the first first data line D1.

Referring to FIG. 3, each of the demultiplexers 162 includes a first switching device (or transistor) T1, a second switching device T2, and a third switching device T3.

The first switching element T1 is provided between the first first data line D1 and the first second data line DL1 to supply a data signal supplied to the first first data line D1 to the first second data line D1. DL1). The first switching device T1 is driven by the first control signal CS1 supplied from the demultiplexer controller 170.

The second switching element T2 is provided between the first first data line D1 and the second second data line DL2 to supply a data signal supplied to the first first data line D1 to the second second data line D1. DL2). The second switching device T2 is driven by the second control signal CS2 supplied from the demultiplexer controller 170.

The third switching element T3 is provided between the first first data line D1 and the third second data line DL2 to supply a data signal supplied to the first first data line D1 to the third second data line DL3). The third switching device T3 is driven by the third control signal CS3 supplied from the demultiplexer controller 170.

The detailed operation of the demultiplexer 162 will be described later in combination with the structure of the pixel 140.

FIG. 4 is a circuit diagram illustrating a first embodiment of the pixel illustrated in FIG. 2. Substantially, in the present invention, all of the pixels 140 having a structure in which the initialization signal is supplied before the data signal is applied may be applied. Here, at least one or more transistors among the transistors included in each pixel 140 are connected to be used as diode elements.

Referring to FIG. 4, each of the pixels 140 according to the first embodiment of the present invention is connected to the light emitting element OLED, the second data line DL, the scan line S, and the light emission control line E. FIG. And a pixel circuit 142 for emitting light of the light emitting element OLED.

The anode electrode of the light emitting element OLED is connected to the pixel circuit 142, and the cathode electrode is connected to the second power source VSS. The second power source VSS may be a voltage lower than the first power source VDD, for example, a ground voltage. The light emitting device OLED generates light corresponding to a current supplied from the pixel circuit 142. To this end, the light emitting device OLED is formed of an organic material including fluorescent and / or phosphorescent.

The pixel circuit 142 includes a storage capacitor Cst and a sixth transistor M6 connected between the first power source VDD and the n-1 scan line Sn-1, the first power source VDD and the data line. The second transistor M2 and the fourth transistor M4 connected between the DL, the fifth transistor M5 connected to the light emitting element OLED and the light emission control line En, and the fifth transistor M5. ) And between the first transistor M1 connected between the first node N1, which is common to the second transistor M2 and the fourth transistor M4, and between the gate terminal and the drain terminal of the first transistor M1. A third transistor M3 to be connected is provided. Although the first to sixth transistors M1 to M6 are shown as P-type MOSFETs in FIG. 4, the present invention is not limited thereto.

The source terminal of the first transistor M1 is connected to the first node N1, and the drain terminal is connected to the source terminal of the fifth transistor M5. The gate terminal of the first transistor M1 is connected to the storage capacitor Cst. The first transistor M1 supplies a current corresponding to the voltage charged in the storage capacitor Cst to the light emitting device OLED.

The drain terminal of the third transistor M3 is connected to the gate terminal of the first transistor M1, and the source terminal is connected to the drain terminal of the first transistor M1. The gate terminal of the third transistor M3 is connected to the nth scan line Sn. The third transistor M3 is turned on when the scan signal is supplied to the nth scan line Sn to connect the first transistor M1 in the form of a diode. That is, when the third transistor M3 is turned on, the first transistor M1 is connected in the form of a diode.

The source terminal of the second transistor M2 is connected to the data line DL, and the drain terminal is connected to the first node N1. The gate terminal of the second transistor M2 is connected to the nth scan line Sn. The second transistor M2 is turned on when the scan signal is supplied to the nth scan line Sn and supplies the data signal supplied to the data line DL to the first node N1.

The drain terminal of the fourth transistor M4 is connected to the first node N1, and the source terminal is connected to the first power source VDD. The gate terminal of the fourth transistor M4 is connected to the light emission control line E. FIG. The fourth transistor M4 is turned on when the emission control signal is not supplied to electrically connect the first power source VDD and the first node N1.

The source terminal of the fifth transistor M5 is connected to the drain terminal of the first transistor M1, and the drain terminal is connected to the light emitting element OLED. The gate terminal of the fifth transistor M5 is connected to the light emission control line E. FIG. The fifth transistor M5 is turned on when the emission control signal is not supplied to supply the current supplied from the first transistor M1 to the light emitting device OLED.

The source terminal of the sixth transistor M6 is connected to the storage capacitor Cst, and the drain terminal and the gate terminal are connected to the n-1 th scan line Sn-1. The sixth transistor M6 is turned on when the scan signal is supplied to the n-1 th scan line Sn-1 to initialize the gate terminal of the storage capacitor Cst and the first transistor M1.

5 is a diagram illustrating in detail a connection structure of a demultiplexer and pixels. Here, it is assumed that pixels of red (R), green (G), and blue (B) are connected to one demultiplexer (i.e., i = 3). It is a waveform diagram which shows the drive waveform supplied.

5 and 6, when the scan signal is supplied to the n−1 th scan line Sn−1, the sixth transistor M6 included in each of the pixels 142R, 142G, and 142B is turned on. do. When the sixth transistor M6 is turned on, the gate terminal of the storage capacitor Cst and the first transistor M1 is connected to the n−1 th scan line Sn−1. That is, when the sixth transistor M6 is turned on, a scan signal is supplied to the gate terminals of the storage capacitor Cst and the first transistor M1 and initialized. Here, the scan signal has a lower voltage value than the data signal.

When the scan signal is supplied to the n-th scan line Sn-1, the first switching element T1, the second switching element T2, and the third switching element T3 are sequentially turned on, so that the first second The data signal is sequentially supplied from the data line DL1 to the third second data line DL3. At this time, since the second transistor M2 maintains the turn-off state, the data signal is not supplied to the pixels 142R, 142G, and 142B.

Thereafter, the scan signal is supplied to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 and the third transistor M3 included in each of the pixels 142R, 142G, and 142B are turned on. After the second transistor M2 and the third transistor M3 included in each of the pixels 142R, 142G, and 142B are turned on, the first switching device T1 is turned on by the first control signal CS1. Is on.

When the first switching device T1 is turned on, the data signal supplied to the first first data line D1 is transmitted to the first node N1 of the first pixel 142R via the first switching device T1. Is supplied. At this time, the gate terminal voltage of the first transistor M1 is initialized by the scan signal supplied to the n-th scan line Sn-1 (that is, the voltage of the data signal applied to the first node N1). Since it is set low), the first transistor M1 is turned on. When the first transistor M1 is turned on, the data signal applied to the first node N1 is supplied to one side of the storage capacitor Cst via the first transistor N1 and the third transistor M3. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal. In addition to the voltage corresponding to the data signal, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1.

Thereafter, the first switching device T1 is turned off, and the second switching device T2 and the third switching device T3 are sequentially turned on, so that the data to the second pixel 142G and the third pixel 142B are turned on. The signals are supplied sequentially.

That is, according to the present invention, the data signal supplied to one first data line D1 may be supplied to i second data lines DL by using the demultiplexer 162. However, in the light emitting display device according to the first embodiment of the present invention, a data signal may not be supplied to specific pixels 142.

This will be described in detail with reference to FIG. 5. First, as described above, the voltage corresponding to the data signal is charged to the storage capacitor Cst of the first pixel 142R during the period in which the first switching device T1 is turned on. Here, the second transistor M2 and the third transistor M3 of the second pixel 142G and the third pixel 142B are connected to the nth scan line Sn during the period in which the first switching device T1 is turned on. The turn-on state is maintained by the scan signal supplied to the circuit.

When the second transistor M2 and the third transistor M3 of the second pixel 142G remain turned on, the gate terminal of the first transistor M1 is electrically connected to the second second data line DL2. do. Here, the second second data line DL2 maintains the voltage value of the data signal supplied to the previous period (previous field or previous frame) by the parasitic capacitor or the like. Therefore, the voltage value of the gate terminal of the first transistor M1 is changed to the voltage value of the data signal supplied in the previous period. That is, the voltage value initialized by the scan signal supplied to the n-th scan line Sn- 1 is changed to the voltage value of the data signal supplied in the previous period.

Thereafter, the second switching device T2 is turned on by the second control signal CS2. When the second switching device T2 is turned on, the data signal supplied to the first first data line D1 is supplied to the second second data line D2. The data signal supplied to the second second data line D2 is supplied to the first node N1 via the second transistor M2 of the second pixel 142G. Here, the first node N1 is set to a voltage value corresponding to the current data signal, and the gate terminal of the first transistor M1 is set to the voltage value of the previous data signal. In this case, the first transistor M1 is turned on only when the voltage value supplied to the first node N1 is greater than the sum of the voltage value of the previous data signal and the threshold voltage of the first transistor M1. In other cases, the first transistor M1 is turned off.

That is, in the first embodiment of the present invention, the voltage value of the gate terminal of the first transistor M1 included in the second pixel 142G and the third pixel 142B is changed when the demultiplexer 162 is driven. There is a problem that a data signal cannot be supplied, and therefore, an image of a desired image cannot be displayed.

FIG. 7 is a circuit diagram illustrating a second embodiment of the pixel illustrated in FIG. 2. The pixel 140 shown in FIG. 7 is supplied with an initialization signal before the data signal is applied. At least one transistor included in each pixel 140 is connected to be used as a diode device.

Referring to FIG. 7, each of the pixels 140 according to the second exemplary embodiment of the present invention is connected to the light emitting device OLED, the second data line DL, and the scanning line S to connect the light emitting device OLED. A pixel circuit 144 for emitting light is provided.

The anode electrode of the light emitting element OLED is connected to the pixel circuit 144, and the cathode electrode is connected to the second power source VSS. The second power source VSS may be a voltage lower than the first power source VDD, for example, a ground voltage. The light emitting device OLED generates light corresponding to a current supplied from the pixel circuit 144. To this end, the light emitting device OLED is formed of an organic material including fluorescent and / or phosphorescent.

The pixel circuit 144 includes a second transistor M2 connected to the second data line DL and an nth scan line Sn, and a second transistor connected between the second transistor M2 and the second initialization power supply Vint2. The third transistor M3 and the fourth transistor M4, the first transistor M1 and the fifth transistor M5 connected between the first power source VDD and the light emitting element OLED, and the first transistor M1; The storage capacitor Cst is connected between the source terminal and the gate terminal of the N-type terminal. In FIG. 7, the first to fourth transistors M1 to M4 are illustrated as P-type MOSFETs, and the fifth transistor M5 is illustrated as an N-type MOSFET, but the present invention is not limited thereto. However, the fifth transistor M5 is formed of a MOSFET of a different type from the first to fourth transistors M1 to M4.

The source terminal of the first transistor M1 is connected to the first power source VDD, and the drain terminal is connected to the source terminal of the fifth transistor M5. The gate terminal of the first transistor M1 is connected to the gate terminal of the third transistor M3. The first transistor M1 supplies a current corresponding to the voltage charged in the storage capacitor Cst to the light emitting device OLED.

The drain terminal of the fifth transistor M5 is connected to the light emitting element OLED, and the gate terminal is connected to the n-1th scan line Sn-1. When the scan signal SSn-1 is not supplied to the n−1 th scan line Sn−1, a current supplied from the first transistor M1 is turned on to supply the light emitting device OLED.

The gate terminal of the second transistor M2 is connected to the nth scan line Sn, and the source terminal is connected to the second data line DL. The drain terminal of the second transistor M2 is connected to the source terminal of the third transistor M3. The second transistor M2 is turned on when the scan signal SSn is supplied to the nth scan line Sn and supplies the data signal supplied to the data line DL to the third transistor M3.

The drain terminal of the third transistor M3 is connected to the source terminal of the fourth transistor M4. The drain terminal and the gate terminal of the third transistor M3 are electrically connected to each other. That is, in the third transistor M3, the drain terminal and the gate terminal are electrically connected to each other and used as a diode element.

The gate terminal of the fourth transistor M4 is connected to the n-th scan line Sn-1, and the drain terminal is connected to the second initialization power supply Vint2. The fourth transistor M4 is turned on when the scan signal is supplied to the n-th scan line Sn-1, and supplies the second initialization power supply Vint2 to the third transistor M3.

8 is a diagram illustrating a connection structure between a demultiplexer and pixels illustrated in FIG. 7. Here, it is assumed that pixels of red (R), green (G), and blue (B) are connected to one demultiplexer 162 (i.e., i = 3). It is a waveform diagram which shows the drive waveform supplied to a demultiplexer.

8 and 9, when the scan signal is supplied to the n−1 th scan line Sn−1, the fourth transistor M4 included in each of the pixels 144R, 144G, and 144B is turned on. . When the fourth transistor M4 is turned on, one end of the storage capacitor Cst, the gate terminal of the first transistor M1, and the gate terminal of the third transistor M3 are connected to the second initialization power supply Vint2. . That is, when the fourth transistor M4 is turned on, the second initialization power supply Vint2 is connected to one end of the storage capacitor Cst, the gate terminal of the first transistor M1, and the gate terminal of the third transistor M3. Supplied and initialized. Here, the second initialization power supply Vint2 is set lower than the voltage obtained by subtracting the threshold voltage of the third transistor M3 from the lowest voltage of the data signal that can be supplied from the data driver 120.

Thereafter, the scan signal is supplied to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 included in each of the pixels 144R, 144G, and 144B is turned on. After the second transistor M2 included in each of the pixels 144R, 144G, and 144B is turned on, the first switching device T1 is turned on by the first control signal CS1.

When the first switching device T1 is turned on, the source signal of the first pixel 144R and the third transistor M3 is supplied to the data signal supplied to the first first data line D1 via the first switching device T1. It is supplied to the terminal. At this time, the gate terminal of the third transistor M3 is turned on because it is initialized by the second initialization power supply Vint2 (that is, has a lower voltage than the source terminal). When the third transistor M3 is turned on, the data signal is supplied to the gate terminal of the third transistor M3, that is, one end of the storage capacitor Cst. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal. In addition to the voltage corresponding to the data signal, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1.

Thereafter, the first switching device T1 is turned off, and the second switching device T2 and the third switching device T3 are sequentially turned on, so that data is transferred to the second pixel 144G and the third pixel 144B. The signals are supplied sequentially.

That is, in the second embodiment of the present invention, the data signal supplied to one first data line D1 may be supplied to i second data lines DL by using the demultiplexer 162. However, even in the second embodiment of the present invention, there is a concern that the desired data signal may not be supplied to the pixels 144.

In detail, first, as described above, the voltage corresponding to the data signal is charged to the storage capacitor Cst of the first pixel 144R during the period in which the first switching device T1 is turned on. Here, the second transistors M2 of the second pixel 144G and the third pixel 144B are turned on by the scan signal supplied to the nth scan line Sn during the period in which the first switching element T1 is turned on. Keep on.

When the second transistor M2 of the second pixel 144G is turned on, the gate terminals of the first transistor M1 and the third transistor M3 are electrically connected to the second second data line DL2. do. Here, the second second data line DL2 maintains the voltage value of the data signal supplied to the previous period (previous field or previous frame) by the parasitic capacitor or the like. Therefore, the voltage values of the gate terminals of the first transistor M1 and the third transistor M3 are changed to the voltage values of the data signal supplied in the previous period. That is, the voltage value initialized by the second initialization power supply Vint2 is changed to the voltage value of the data signal supplied in the previous period.

Thereafter, the second switching device T2 is turned on by the second control signal CS2. When the second switching device T2 is turned on, the data signal supplied to the first first data line D1 is supplied to the second second data line D2. The data signal supplied to the second second data line D2 is supplied to the source terminal of the third transistor M3 via the second transistor M2 of the second pixel 144G. That is, a voltage value corresponding to the current data signal is applied to the source terminal of the third transistor M3, and a voltage value corresponding to the previous data signal is applied to the gate terminal. In this case, when the voltage value of the current data signal is greater than the voltage value of the previous data signal and the threshold voltage of the third transistor M1, the third transistor M3 is turned on. Otherwise, the third transistor M3 is turned on. M3 is turned off.

That is, in the second embodiment of the present invention, since the voltage value of the gate terminal of the third transistor M3 included in the second pixel 144G and the third pixel 144B is changed when the demultiplexer 162 is driven. There is a case where a signal is not supplied, thereby causing a problem in that a desired image cannot be displayed. In order to solve such a problem, the light emitting display device of FIG. 10 is proposed in the present invention.

10 is a diagram illustrating a light emitting display device according to a second embodiment of the present invention. 10, the same components as those in FIG. 2 are assigned the same reference numerals and detailed descriptions thereof will be omitted.

Referring to FIG. 10, the light emitting display device according to the second embodiment of the present invention may include a scan driver 110, a data driver 120, an image display unit 130, a timing controller 150, a demultiplexer block unit 160, The demultiplexer controller 170 and the initialization block unit 200 are provided.

The initialization block unit 200 includes a plurality of initialization units 202 connected to the i second data lines DL. The initialization unit 202 supplies the first initialization power before the data signal is supplied to each of the second data lines DL.

To this end, the initialization block unit 200 includes i initialization switching elements T4, T5, and T6 as shown in FIG. 11 (where i is assumed to be 3). The initialization switching elements T4, T5, and T6 It is connected in common with the first initialization power supply Vint1, and is also connected to different second data lines DL. The initialization switching devices T4, T5, and T6 are turned on at the same time and turned off at different times to supply the first initialization power supply Vint1 to each of the second data lines DL.

Meanwhile, in the present invention, the initialization switching elements T4, T5, and T6 included in the initialization unit 202 are positioned adjacent to the data switching elements T1 to T3 included in the demultiplexer 162 as shown in FIG. Can be. Here, the initialization switching elements T4, T5, and T6 are positioned adjacent to the data switching elements T1 to T3 or are separated from each other, or the operation process is the same. Hereinafter, it will be described on the assumption that the initialization switching elements T4, T5, and T6 are positioned adjacent to the data switching elements T1 to T3. As shown in FIG. 12, when the demultiplexer 162 and the initialization unit 202 are disposed, the demultiplexer 162 and the initialization unit 202 will be referred to as a demultiplexing circuit.

The first switching element T1 is provided between the first first data line D1 and the first second data line DL1 to receive a data signal supplied from the first data line D1 to the first second data line DL1. ). The first switching device T1 is turned on by the first control signal CS1 supplied from the demultiplexer controller 170 as shown in FIG. 14.

The second switching element T2 is provided between the first first data line D1 and the second second data line DL2 to supply a data signal supplied to the first first data line D1 to the second second data line D1. DL2). The second switching device T2 is turned on by the second control signal CS2 supplied from the demultiplexer controller 170 as shown in FIG. 14.

The third switching element T3 is provided between the first first data line D1 and the third second data line DL3 to supply a data signal supplied to the first first data line D1 to the third second data line ( DL3). The third switching device T3 is turned on by the third control signal CS3 supplied from the demultiplexer controller 170 as shown in FIG. 14.

The fourth switching element T4 is provided between the first initialization power supply Vint1 and the first second data line DL1 to supply the voltage value of the first initialization power supply Vint1 to the first second data line DL1. . Here, the voltage value of the first initialization power supply Vint1 is set lower than the voltage of the lowest data signal that can be supplied to the image display unit 130. For example, if the lowest voltage that can be supplied from the data driver 120 to the image display unit 130 is 2V, the voltage value of the first initialization power supply Vint1 is set lower than 2V. Substantially, the first initialization power supply Vint1 is set lower than the voltage of the lowest data signal that can be supplied to the image display unit 130 minus the threshold voltage of the transistor included in the pixel 140. The fourth switching device T4 is turned on by the first initialization control signal Cb1 supplied from the demultiplexer controller 170 as shown in FIG. 14.

The fifth switching element T5 is provided between the first initialization power supply Vint1 and the second second data line DL2 to supply the voltage value of the first initialization power supply Vint1 to the second second data line DL2. do. The fifth switching device T5 is turned on by the second initialization control signal Cb2 supplied from the demultiplexer controller 170 as shown in FIG. 14.

The sixth switching element T6 is provided between the first initialization power supply Vint1 and the third second data line DL3 to supply the voltage value of the first initialization power supply Vint1 to the third second data line DL3. do. The sixth switching device T6 is turned on by the third initialization control signal Cb3 supplied from the demultiplexer controller 170 as shown in FIG. 14.

Meanwhile, the demultiplexer controller 170 sequentially supplies the first control signal CS1, the second control signal CS2, and the third control signal CS3 whenever the scan signal is supplied to the scan line S. FIG. Here, each of the control signals CS1 to CS3 is supplied with a time difference of the second period L2. The first control signal CS1 is supplied after the first period L1 after the scan signal SS is supplied. In addition, the third control signal CS3 is raised before the scan signal SS is raised, that is, the first period L1.

The demultiplexer controller 170 simultaneously supplies the first initialization control signal Cb1, the second initialization control signal Cb2, and the third initialization control signal Cb3 to be synchronized with the scan signal SS (at the same time). . Here, the first initialization control signal Cb1 is raised just before the first control signal CS1 is supplied so as not to overlap with the first control signal CS1. The second initialization control signal Cb2 is raised just before the second control signal CS2 is supplied so as not to overlap the second control signal CS2. The third initialization control signal Cb3 is raised just before the third control signal CS3 is supplied. That is, each of the fourth switching elements T4 to the sixth switching elements T6 is turned on before the first switching elements T1 to the third switching elements T3 connected to the same data line are turned on. Is off.

Meanwhile, although the switching elements T1 to T6 are shown in the P type in FIGS. 11 and 12, the present invention is not limited thereto. Subsequently, the switching elements T1 to T6 are set to the same type as the transistors included in the pixels 140 and connected to the second data line DL. For example, when the transistors connected to the second data line DL are formed of P type, the switching elements T1 to T6 are also formed of P type, and the transistors connected to the second data line DL are of N type. When formed as the switching elements (T1 to T6) are also formed of N type.

FIG. 13 is a diagram illustrating a connection structure of the demultiplexer and initializer illustrated in FIG. 12 and the pixels illustrated in FIG. 4. Here, it is assumed that pixels of red (R), green (G), and blue (B) are connected to one demultiplexer (i.e., i = 3). It is a waveform diagram showing a driving waveform.

13 and 14, when the scan signal is supplied to the n−1 th scan line Sn−1, the sixth transistor M6 included in each of the pixels 142R, 142G, and 142B is turned on. . When the sixth transistor M6 is turned on, the gate terminal of the storage capacitor Cst and the first transistor M1 is connected to the n−1 th scan line Sn−1. That is, when the sixth transistor M6 is turned on, a scan signal is supplied to the gate terminals of the storage capacitor Cst and the first transistor M1 and initialized.

Thereafter, the scan signal is supplied to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 and the third transistor M3 included in each of the pixels 142R, 142G, and 142B are turned on. The first initialization control signal Cb1, the second initialization control signal Cb2, and the third initialization control signal Cb3 are supplied to be synchronized with the scan signal supplied to the nth scan line Sn. When the first initialization control signal Cb1 to the third initialization control signal Cb3 are supplied, the fourth switching device T4 to the sixth switching device T6 are turned on.

When the fourth switching device T4 to the sixth switching device T6 are turned on, the voltage of the first initialization power supply Vint1 is supplied to the first second data line DL1 to the third second data line DL3. . The initialization power supply Vint1 supplied to the first second data line DL1 to the third second data line DL3 is supplied to the first node N1 of the pixels 142R, 142G, and 142B. Here, the gate terminal of the first transistor M1 included in each of the pixels 142R, 142G, and 142B is initialized by the scan signal supplied to the n-th scan line Sn-1, that is, the scan terminal Maintain the corresponding voltage.

When the initialization power supply Vint1 is supplied to the first node N1, the first transistor M1 is turned on or turned off. In fact, whether the first transistor M1 is turned on or off is determined by the voltage value of the initialization power supply Vint1. Here, the voltage value of the initialization power supply Vint1 is set lower than the voltage of the lowest data signal that can be supplied to the image display unit 130 minus the threshold voltage of the transistor included in the pixel 140.

For example, when the first transistor M1 is turned on, the voltage value of the gate terminal of the first transistor M1 is changed to the voltage value of the initialization power supply Vint1. When the first transistor M1 is turned off, the voltage value of the gate terminal of the first transistor M1 maintains the voltage value of the scan signal.

Thereafter, the first control signal CS1 is supplied to turn on the first switching device T1. Here, the supply of the first initialization control signal Cb1 is stopped before the first control signal CS1 is supplied, and the second initialization control signal Cb2 and the third initialization control signal Cb3 are the first control signal. The supply continues to overlap with CS1.

When the first control signal CS1 is supplied, the first switching device T1 is turned on. When the first switching device T1 is turned on, the data signal supplied to the first first data line D1 is supplied to the first node N1 of the first pixel 142R via the second transistor M2. do. When the voltage of the data signal is supplied to the first node N1, the first transistor M1 is turned on. In other words, since the voltage value of the gate terminal of the first transistor M1 is set to the voltage value of the initialization power supply Vint1 or the scan signal, the first transistor M1 when the data signal is supplied to the first node N1. ) Is turned on. When the first transistor M1 is turned on, the data signal applied to the first node N1 is supplied to one side of the storage capacitor Cst via the first transistor M1 and the third transistor M3. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal.

Thereafter, the first switching device T1 is turned off, and the second switching device T2 is turned on by the second control signal CS1. Here, before the second control signal CS2 is supplied, the supply of the second initialization control signal Cb2 is stopped, and the third initialization control signal Cb3 is continuously supplied to overlap with the second control signal CS2.

When the first control signal CS1 is supplied, the second switching device T2 is turned on. When the second switching device T2 is turned on, the data signal supplied to the first first data line D1 is supplied to the first node N1 of the second pixel 142G via the second transistor M2. do. When the voltage of the data signal is supplied to the first node N1, the first transistor M1 is turned on. In other words, since the voltage value of the gate terminal of the first transistor M1 is set to the voltage value of the initialization power supply Vint1 or the scan signal, the first transistor M1 when the data signal is supplied to the first node N1. ) Is turned on. When the first transistor M1 is turned on, the data signal applied to the first node N1 is supplied to one side of the storage capacitor Cst via the first transistor M1 and the third transistor M3. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal.

Thereafter, the second switching device T2 is turned off and the third switching device T3 is turned on by the third control signal CS3. Here, the supply of the third initialization control signal Cb3 is stopped before the third control signal CS3 is supplied.

When the third control signal CS3 is supplied, the third switching device T3 is turned on. When the third switching device T3 is turned on, the data signal supplied to the first first data line D1 is supplied to the first node N1 of the third pixel 142B via the second transistor M2. do. When the voltage of the data signal is supplied to the first node N1, the first transistor M1 is turned on. In other words, since the voltage value of the gate terminal of the first transistor M1 is set to the voltage value of the initialization power supply Vint1 or the scan signal, the first transistor M1 when the data signal is supplied to the first node N1. ) Is turned on. When the first transistor M1 is turned on, the data signal applied to the first node N1 is supplied to one side of the storage capacitor Cst via the first transistor M1 and the third transistor M3. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal.

As described above, in the present invention, the data signal supplied to one first data line D1 may be supplied to i second data lines DL by using the demultiplexer 162. In addition, in the present invention, additional initialization switching elements are additionally provided to correspond to the data switching elements, and the first initialization power supply Vint1 is supplied stably until the data signal is supplied to each of the second data lines DL. An image can be displayed.

FIG. 15 is a diagram illustrating a connection structure of the demultiplexer and initializer illustrated in FIG. 12 and the pixels illustrated in FIG. 7. Here, it is assumed that pixels of red (R), green (G), and blue (B) are connected to one demultiplexer.

14 and 15, when the scan signal is supplied to the n−1 th scan line Sn−1, the fourth transistor M4 included in each of the pixels 144R, 144G, and 144B is turned on. . When the fourth transistor M4 is turned on, one end of the storage capacitor Cst, the gate terminal of the first transistor M1, and the gate terminal of the third transistor M3 are connected to the second initialization power supply Vint2. . That is, when the fourth transistor M4 is turned on, the second initialization power supply Vint2 is connected to one end of the storage capacitor Cst, the gate terminal of the first transistor M1, and the gate terminal of the third transistor M3. Supplied and initialized. Here, the second initialization power supply Vint2 is set lower than the voltage obtained by subtracting the threshold voltage of the third transistor M3 from the lowest voltage of the data signal that can be supplied from the data driver 120. On the other hand, the voltage values of the second initialization power supply Vint2 and the first initialization power supply Vint1 are set the same or different.

Thereafter, the scan signal is supplied to the nth scan line Sn. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 included in each of the pixels 144R, 144G, and 144B is turned on. The first initialization control signal Cb1, the second initialization control signal Cb2, and the third initialization control signal Cb3 are supplied to be synchronized with the scan signal supplied to the nth scan line Sn. When the first initialization control signal Cb1 to the third initialization control signal Cb3 are supplied, the fourth switching device T4 to the sixth switching device T6 are turned on.

When the fourth switching device T4 to the sixth switching device T6 are turned on, the voltage of the first initialization power supply Vint1 is supplied to the first second data line DL1 to the third second data line DL3. . The first initialization power supply Vint1 supplied to the first second data line DL1 to the third second data line DL3 is a source terminal of the third transistor M3 included in the pixels 144R, 144G, and 144B. Supplied. Here, the gate terminal of the third transistor M3 maintains the voltage value of the second initialization power supply Vint2 because it is initialized by the second initialization power supply Vint2.

When the first initialization power supply Vint1 is supplied to the source terminal of the third transistor M3, the first transistor M1 is turned on or turned off. In fact, whether to turn on or off of the third transistor M3 is determined by the voltage value of the initialization power supply Vint1. Here, if the third transistor M3 is turned on, the voltage value of the gate terminal of the third transistor M3 is changed to the voltage value of the first initialization power supply Vint1. If the third transistor M3 is turned off, the voltage value of the gate terminal of the third transistor M3 maintains the voltage value of the second initialization power supply Vint2.

Thereafter, the first control signal CS1 is supplied to turn on the first switching device T1. Here, before the first control signal CS1 is supplied, the supply of the first initialization control signal Cb1 is stopped, and the second initialization control signal Cb2 and the third initialization control signal Cb3 are connected to the first control signal C1. It is continuously supplied to overlap CS1).

When the first switching device T1 is turned on, the source signal of the first pixel 144R and the third transistor M3 is supplied to the data signal supplied to the first first data line D1 via the first switching device T1. It is supplied to the terminal. At this time, the gate terminal of the third transistor M3 is turned on because it is initialized by the first initialization power supply Vint1 or the second initialization power supply Vint2. When the third transistor M3 is turned on, the data signal is supplied to the gate terminal of the third transistor M3, that is, one end of the storage capacitor Cst. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal. In addition to the voltage corresponding to the data signal, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1.

Thereafter, the first switching device T1 is turned off, and the second switching device T2 is turned on by the second control signal CS1. Here, before the second control signal CS2 is supplied, the supply of the second initialization control signal Cb2 is stopped, and the third initialization control signal Cb3 is continuously supplied to overlap with the second control signal CS2.

When the second switching device T2 is turned on, the source signal of the second pixel 144G and the third transistor M3 is supplied via the second switching device T2 when the data signal supplied to the first first data line D1 is turned on. It is supplied to the terminal. At this time, the gate terminal of the third transistor M3 is turned on because it is initialized by the first initialization power supply Vint1 or the second initialization power supply Vint2. When the third transistor M3 is turned on, the data signal is supplied to the gate terminal of the third transistor M3, that is, one end of the storage capacitor Cst. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal. In addition to the voltage corresponding to the data signal, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1.

Thereafter, the second switching device T2 is turned off and the third switching device T3 is turned on by the third control signal CS3. Here, the supply of the third initialization control signal Cb3 is stopped before the third control signal CS3 is supplied.

When the third switching device T3 is turned on, the source signal of the third transistor 144B and the third transistor M3 is supplied with the data signal supplied to the first first data line D1 via the third switching device T3. It is supplied to the terminal. At this time, the gate terminal of the third transistor M3 is turned on because it is initialized by the first initialization power supply Vint1 or the second initialization power supply Vint2. When the third transistor M3 is turned on, the data signal is supplied to the gate terminal of the third transistor M3, that is, one end of the storage capacitor Cst. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal. In addition to the voltage corresponding to the data signal, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1.

As described above, in the present invention, the data signal supplied to one first data line D1 may be supplied to i second data lines DL by using the demultiplexer 162. In addition, in the present invention, an initialization switching element is additionally provided to correspond to each of the data switching elements, and the first initialization power supply Vint1 is stably supplied until the data signal is supplied to each of the second data lines DL. An image can be displayed.

In the meantime, a higher current is supplied to the light emitting device OLED from the pixel 140 receiving the data signal later than the pixel 140 receiving the data signal first during the period in which the scan signal SS is experimentally supplied. Accordingly, in the present invention, the application order of the first to third control signals CS1 to CS3 can be set as shown in FIG. 16 in consideration of the luminous efficiency of the light emitting device OLED. In this case, each demultiplexer 162 Assume that it is connected to red (R), green (G) and blue (G) pixels)

In detail, the storage capacitor Cst of the pixel 140 that receives the data signal is charged with a voltage corresponding to the data signal during the scan signal period. However, since the data signal is not sufficiently supplied to the storage capacitor Cst of the pixel 140 which receives the data signal, a voltage higher than the desired voltage is charged. That is, even when a data signal having the same gray level value is supplied, a higher current is supplied to the light emitting device OLED as the pixel 140 receives the data signal later.

On the other hand, the luminous efficiency of the light emitting device OLED is generally set in the order of the green (G) light emitting device (OLED), the red (R) light emitting device (OLED), and the blue (B) light emitting device (OLED). Accordingly, in the present invention, as shown in FIG. 16, the second control signal CS2 is first supplied so that the data signal can be first supplied to the green (G) light emitting device OLED having high luminous efficiency, and blue (B) having low luminous efficiency. The third control signal CS3 is supplied last so that the data signal can be supplied later to the light emitting element OLED. Then, when a data signal having the same gradation value is supplied, the lowest current is supplied to the green (G) light emitting device (OLED) with high luminous efficiency, and the highest to the blue (B) light emitting device (OLED) with low luminous efficiency. Current is supplied. That is, in the present invention, an image having improved white balance can be displayed by controlling the supply order of the first to third control signals CS1 to CS3 in consideration of the luminous efficiency of the light emitting device OLED.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to an embodiment of the present invention, a demultiplexer, a light emitting display device using the same, and a driving method thereof according to the embodiment of the present invention allow the data signal supplied to one output line to be supplied to i data lines using the demultiplexer. Can reduce the cost. In addition, by installing i initialization transistors in each demultiplexer and turning on the initialization transistor until the data transistor connected to the same data line as the initialization transistor is turned on, the desired data signal can be supplied to the pixels. . Further, in the present invention, since the turn-on timing of the transistors included in the demultiplexer is set in consideration of the luminous efficiency of the light emitting device, an image of more improved image quality can be displayed.

Claims (30)

A scan driver for sequentially supplying scan signals to the scan lines; A data driver having a plurality of output lines and supplying a plurality of data signals to respective output lines during a period in which the scan signal is supplied; An image display unit including a plurality of pixels positioned in an area partitioned by the scan line and the data line; Demultiplexers including a plurality of data transistors provided for each output line and supplying a data signal supplied to the output line to a plurality of data lines; And an initialization unit including a plurality of initialization transistors for applying a predetermined voltage to the plurality of data lines. The method of claim 1, Each of the pixels includes a plurality of transistors, and at least one of the transistors is connected to be used as a diode element. The method of claim 1, And a demultiplexer controller for controlling the demultiplexer so that a plurality of data signals supplied to each of the output lines are supplied to the plurality of data lines. The method of claim 3, wherein The number of data transistors included in each of the demultiplexers and the number of initialization transistors included in each of the initialization units are equally set. The method of claim 4, wherein And the demultiplexer controller is configured to supply a control signal to sequentially turn on the plurality of data transistors while the scan signal is supplied. The method of claim 5, The demultiplexer controller is configured to supply an initialization control signal to turn on the initialization transistors before the data transistors are turned on. The method of claim 6, The demultiplexer controller is configured to supply the initialization control signal to turn off the initialization transistors at different times. The method of claim 7, wherein And an initialization transistor connected to the same data line as the data transistor is turned off before the data transistor connected to the same data line is turned on. The method of claim 2, And a voltage value of the predetermined voltage is set so that the transistor used as the diode element can be turned on when the predetermined voltage is applied to the transistor used as the diode element. The method of claim 2, Each of the pixels A light emitting element, A first transistor for controlling a current supplied to the light emitting element in response to the data signal; A storage capacitor connected to the first transistor to charge a voltage corresponding to the data signal; and a second transistor connected to an n (n is a natural number) scan line and a data line to transfer the data signal supplied from the data line to the storage capacitor. The method of claim 10, The data transistors and the initialization transistors are set to the same type as the second transistor. The method of claim 10, Each of the pixels A third transistor connected between the second transistor and the first transistor and electrically connected to a gate terminal and a drain terminal; a fourth transistor controlled by the n−1 th scan line and connected to the third transistor and the second initialization power supply; And a fifth transistor controlled by the n-1th scan line and connected to the light emitting element and the first transistor. The method of claim 10, Each of the pixels A third transistor controlled by the nth scan line and connected to the gate terminal and the drain terminal of the first transistor; A fourth transistor and a fifth transistor connected to the emission control line; and a sixth transistor, wherein the gate terminal and the drain terminal are connected to the n-1 scan line, and the source terminal is connected to the gate terminal of the first transistor. The method of claim 10, And a voltage value of the predetermined power is lower than a voltage value of the lowest data signal that can be supplied from the data driver. The method of claim 10, The voltage value of the predetermined power source is set to be lower than the threshold voltage of the transistor connected to be included in the pixel and used as the diode element at the lowest voltage value of the data signal that can be supplied from the data driver. Light emitting display. The method of claim 1, Each of the demultiplexers is connected to three data lines, and each of the three data lines is connected to a red pixel including a red light emitting device, a green pixel including a green light emitting device, and a blue pixel including a blue light emitting device. . The method of claim 16, And a turn-on order of the data transistors so that the data signal can be supplied to the light emitting device having high luminous efficiency among the red light emitting device, the green light emitting device, and the blue light emitting device. The method of claim 17, The turn-on order of the three data transistors is set such that the data signal is supplied to the green light emitting device first, and the data signal is supplied to the blue light emitting device last. Demultiplexers including a plurality of data transistors provided for each output line of each data driver to supply a plurality of data signals supplied to the output line to the plurality of data lines; A demultiplexing circuit comprising initialization units including a plurality of initialization transistors for supplying a predetermined power supply to the plurality of data lines. The method of claim 19, The number of data transistors included in each of the demultiplexers and the number of initialization transistors included in each of the initialization units are equally set. The method of claim 20, The data transistors included in each of the demultiplexers are sequentially turned on to supply the plurality of data signals to the plurality of data lines. The method of claim 21, Each initialization transistor included in the initialization unit is turned on before the data transistors and is turned off at different times. The method of claim 22, Each of the initialization transistors is turned off before the data transistor connected to the same data line as the initialization transistor is turned on. The method of claim 19, And a voltage value of the predetermined power supply is set lower than a voltage value of the lowest data signal that can be supplied to the data line. Sequentially supplying scan signals to a plurality of scan lines; Supplying a plurality of data signals to output lines of each data driver while the scan signal is supplied; Supplying the plurality of data signals to the plurality of data lines while sequentially turning on the plurality of data transistors provided for each output line; And turning on the initialization transistors connected to the plurality of data lines before the data transistors are turned on to supply a voltage of an initialization power supply to the plurality of data lines. The method of claim 25, And the initialization transistors are turned off at different times. The method of claim 26, And each of the initialization transistors is turned off before the data transistor connected to the same data line as it is turned on. The method of claim 25, Three data transistors are connected to each output line, and each of the three data lines connected to the three data transistors includes a red pixel including a red light emitting device, a green pixel including a green light emitting device, and a blue light emitting device. A driving method of a light emitting display device connected to a blue pixel. The method of claim 28, The turn-on order of the data transistors is set faster as the light emitting efficiency of the light emitting device connected thereto is higher. The method of claim 29, And the data transistors are set in a turn-on order so that the data signal is supplied first to the green light emitting device and the data signal is supplied last to the blue light emitting device.

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