KR100581662B1 - Common engine for plural hash functions having different algorithms - Google Patents

Abstract

The present invention relates to a function calculation engine, and more particularly, to a hash function calculation engine implemented in hardware capable of computing a plurality of hash functions different algorithms. The function calculation engine according to the present invention may share a common value in a calculation circuit in which algorithms are provided for computing at least two or more hash functions, which are different from each other, or algorithms for calculating at least two or more hash functions. have. Therefore, in a circuit for processing a plurality of hash functions with similar algorithm structures, the hardware required for the function processing can be reduced by designing to share the same hardware components.

Hash Function, Hash Engine, SHA-1, HAS, Common Engine

Description

Common engine for plural Hash functions having different algorithms

The following drawings, which are attached to this specification, illustrate the preferred embodiments of the present invention, and together with the detailed description of the invention that serves to further understand the spirit of the present invention, the present invention is described in such drawings. It should not be construed as limited to matters.

1 is a view schematically showing a hash function calculation engine according to the prior art.

2 is a block diagram of a function calculation engine having a plurality of hash function processing units according to the prior art.

3 is a diagram illustrating a plurality of intermediate value processing units in the hash function calculation engine according to the related art.

4 is a block diagram of a common engine for a hash function operation according to an embodiment of the present invention.

5 is a configuration diagram of a common engine for a hash function operation according to another embodiment of the present invention.

FIG. 6 is a detailed configuration diagram of a common engine for computing the hash function of FIG. 4.

<Description of main reference numerals in the drawings>

1, 7 Input buffer 2, 40, 60, 80

210 ... SHA-1 intermediate value processing unit 220 ... HAS intermediate value processing unit

310 ... SHA-1 function processor 320 ... HAS function processor

3, 50, 70, 90 ... Function operator 81 ... Storage block

82 ... Medium value operator 83 ... SHA-1 selection buffer

84 ... SHA-1 intermediate value calculating circuit 85 ... HAS selection buffer

86 ... HAS intermediate value calculation circuit 91 ... selection circuit

92 ... Save function block 93 ... Select function

94.Common function calculator 95 ... Differential function calculator

96. Carry adder 97 ... Shifter

98 ... Output adder 99 ... Output buffer

The present invention relates to a hash function calculation engine, and more particularly, to a hash function calculation engine implemented in hardware capable of computing a plurality of different hash functions.

The idea of a hash is to convert a string into a shorter value or key that symbolizes the original. Finding an item using a short hash value is faster than using an original value to find an item. It is mainly used to search items in the database. The hash algorithm is applied to encryption technology as a function.

Such a hash algorithm is widely used for digital signatures, and typical hash algorithms include message-digest (MD) 4, MD5, Secure Hash Algorithm (SHA) -1, RACE Integrity Primitives Evaluation message-digest (RMD) 160, and HAS (HAS). Hash Algorithm). Here, since the hash algorithm is mostly designed based on MD4, the structure is similar.

On the other hand, generally, a method of calculating a function includes a method implemented using software and a method implemented using hardware. When implemented using software, it is flexible, but computational speed is slow and stability is low.

Therefore, the hardware engine shown in FIG. 1 is used for hash function calculation. The hash function calculation engine implemented in hardware includes an input buffer (1) for temporarily storing input data and an intermediate value processing unit (2) for generating an intermediate value for hash function processing using an intermediate value received from the input buffer (1). And a function processing unit 3 for calculating a hash function. In the case of computing different hash functions in the structure of the hash function calculation engine, at least two hash function calculation engines required for each hash function calculation are required. In addition, different intermediate values are input to hash functions of different algorithms. Accordingly, in order to calculate different hash functions, at least two intermediate value processing units capable of calculating intermediate values input to each hash function are provided.

2 is a configuration diagram of a hash function calculation engine including a plurality of function processing units 310 and 320 to calculate different hash functions SHA-1 and HAS according to the related art. Referring to FIG. 2, a hash function calculation engine implemented to calculate two functions according to the prior art includes an input buffer 1, a SHA-1 function processor 310, a SHA-1 intermediate value processor 210, and a HAS. And a function processor 320 and a HAS median processor 210.

The SHA-1 function processor 310 performs a selection circuit 311, a function value storage block 312, a SHA-1 function operator 313, a carry adder 314, and an output adder to process a function according to SHA-1. 315 and an output buffer 316, the HAS function processor 320 includes a selection circuit 321, a function value storage block 322, a HAS function operator 323, and carry to process a function according to the HAS. An adder 324, an output adder 325, and an output buffer 326 are provided.

Here, the hardware configuration of the other components except for the SHA-1 function calculator 313, the HAS function calculator 323, the SHA-1 intermediate value processor 210, and the HAS intermediate value processor 220 are the same. That is, the selection circuit 311 of the SHA-1 function processor 310 and the selection circuit 321 of the HAS function processor 320, the function value storage block 312 and the HAS function processor of the SHA-1 function processor 310. The function value storage block 322 of 320, the carry adder 314 of the SHA-1 function processor 310, the carry adder 324 of the HAS function processor 320, and the output of the SHA-1 function processor 310 The hardware constituting the adder 315, the output adder 325 of the HAS function processor 320, the output buffer 316 of the SHA-1 function processor 310, and the output buffer 326 of the HAS function processor 320 may be used. Same with each other.

Therefore, by providing the same hardware in each function calculating section (SHA-1 function calculating section 313 and HAS function calculating section 323), hardware for calculating data is unnecessarily consumed.

3 illustrates a detailed configuration of the SHA-1 intermediate value processing unit 210 and the HAS intermediate value processing unit 220, the SHA-1 intermediate value processing unit 210 may include a SHA-1 intermediate value storage block 211. ), A SHA-1 intermediate value variable calculation unit 212, a SHA-1 intermediate value selection buffer 213, and a SHA-1 intermediate value calculation circuit 214, and the HAS intermediate value processing unit 220 stores the HAS intermediate value. A block 221, a HAS intermediate value variable calculating unit 222, a HAS intermediate value selecting buffer 223, and a HAS intermediate value calculating circuit 224 are provided. The A block of the SHA-1 intermediate value processing unit 210 and the C block of the HAS intermediate value processing unit 220 are blocks in which 16 identical data input from the input buffer are stored. Therefore, by storing the same data in storage blocks (blocks A and C) of different spaces, storage blocks for storing data are unnecessarily consumed.

If the algorithms of at least two or more functions are similar (eg, such as SHA-1 algorithm and HAS algorithm), as in the above example, a large number of identical circuits are provided, resulting in a waste of a lot of electrical elements in the circuit design.

In addition, as a large number of unnecessary electric elements are provided in the function processor, a lot of time and effort are required for designing the arrangement of the electric elements, and the volume of hardware increases due to the number of electric elements.

The present invention is to solve the above problems, the algorithm is to share the hardware components necessary for a plurality of different hash function calculation, reducing the amount of electrical elements provided in the hash function calculation engine, and a small hash function calculation engine The purpose is to provide.

In order to achieve the above object, a common engine for a hash function operation according to an aspect of the present invention, an input buffer for generating and storing a block of the input data in a predetermined bit unit; An intermediate value processing unit for generating an intermediate value variable for the hash function operation and sharing a common intermediate value among intermediate values required for at least two different hash function operations different from each other; And a function processor for calculating the hash function using the intermediate value.

Preferably, the function processing unit may operate a function by sharing operators common to at least two or more hash functions having different algorithms.

In accordance with another aspect of the present invention, a common engine for a hash function calculation may include: an input buffer configured to generate and store blocks of input data in predetermined bit units; An intermediate value processing unit for generating and storing intermediate value variables required for at least two hash function operations different from each other; And a function processing unit that calculates a hash function by sharing operators common to at least two hash functions having different algorithms.

Preferably, the median processing unit may share a median common between at least two hash functions with different algorithms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in this specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly introduce the concept of terms in order to best explain their invention. It should be interpreted as meanings and concepts in accordance with the technical spirit of the present invention based on the principle that it can be defined. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations. The same reference numerals among the reference numerals shown in each drawing represent the same members.

4 is a block diagram of a function calculation engine according to an embodiment of the present invention. In one embodiment of the present invention, the algorithm illustrates a function calculation engine including an intermediate value processing unit that shares a storage block storing the same intermediate value in order to calculate similar hash functions SHA-1 and HAS.

Referring to FIG. 4, the function calculation engine according to an exemplary embodiment of the present invention includes an input buffer 7, an intermediate value processor 40, and a function processor 50.

The input buffer 7 stores 512 bits of padded data for generating intermediate values and an initial value of 160 bits for processing the SHA-1 function and the HAS function.

The intermediate value processing unit 40 stores the storage block 41, the intermediate value variable calculating unit 42, and the SHA-1 selection buffer 43 to calculate the intermediate value Wn necessary for the function operation and transmit the intermediate value Wn to the function processing unit 50. And the SHA-1 intermediate value calculating circuit 44, the HAS selection buffer 45, and the HAS intermediate value calculating circuit 46.

The storage block 41 stores 16 intermediate values Wn received from the input buffer 7 and intermediate values Wn calculated and transmitted by the SHA-1 intermediate value calculating circuit 44 and the HAS intermediate value calculating circuit 46. Save). Sixteen intermediate values Wn received from the input buffer 7 are stored in the common block, and intermediate values Wn received from the SHA-1 intermediate value calculation circuit 44 are stored in the SHA-1 block, and HAS The block stores the intermediate value Wn received from the HAS intermediate value calculating circuit 46.

The intermediate value variable calculating section 42 calculates the intermediate value variable Wn 'required for calculating the intermediate value required to process the function of the nth step and transmits it to the SHA-1 selection buffer 43 and the HAS selection buffer 45. do.

On the other hand, since functions with different algorithms require different median values Wn at the same step, the median variable Wn 'is applied to each algorithm. Therefore, in the same step, the median variable Wn 'transmitted to the SHA-1 selection buffer 43 and the HAS selection buffer 45 may be different.

The SHA-1 selection buffer 43 receives the intermediate value variable Wn 'necessary for processing the SHA-1 function of the nth step from the intermediate value variable calculating section 42, and the intermediate value corresponding to the variable Wn' is received. The value Wn is extracted from the storage block 41 and sent to the SHA-1 intermediate value computing circuit 44.

The SHA-1 intermediate value calculating circuit 44 applies the intermediate value variable Wn 'received from the SHA-1 selection buffer 43 to a predetermined intermediate value formula to generate the intermediate value Wn. The intermediate value Wn is stored in the block corresponding to the nth step.

The HAS selection buffer 45 receives the intermediate value variable Wn 'necessary for processing the HAS function of the nth step from the intermediate value variable calculating section 42, and the intermediate value Wn corresponding to the variable Wn'. Is extracted from the storage block 41 and transmitted to the HAS intermediate value calculating circuit 46.

Here, the SHA-1 function calculation is composed of a total of 80 steps, from the 16 intermediate values Wn received from the input buffer 1 and the SHA-1 intermediate value calculation circuit 84 to perform the 80 steps of operations. A total of 64 median values (Wn) generated are required for a total of 80 median values (Wn). Therefore, the intermediate value (Wn) required for the function calculation of steps 1 to 16 of the 80 steps uses 16 data generated by dividing the 512 bits inputted from the input buffer 7 into 32 bits. The intermediate value Wn required for the function calculation uses 64 data generated by calculating according to Equation (1). Accordingly, the SHA-1 intermediate value calculating circuit 44 includes a circuit for calculating Equation 1, and the SHA-1 intermediate value calculating unit 42 includes variables ((n-3) and (n -8), (n-14), and (n-16)).

Wn = ROLT (W (n-3) XOR W (n-8) XOR W (n-14) XOR W (n-13)) (16≤n≤79, n = step)

(ROLT is 1 bit circular left shift operation, XOR is exclusive OR of bits)

The HAS selection buffer 45 receives the intermediate value variable Wn 'necessary for processing the HAS function of the nth step from the intermediate value variable calculating section 42, and the intermediate value Wn corresponding to the variable Wn'. Is extracted from the storage block 41 and transmitted to the HAS intermediate value calculating circuit 46.

The HAS intermediate value calculating circuit 46 applies the intermediate value variable Wn 'received from the HAS selection buffer 45 to a predetermined intermediate value formula to generate the intermediate value Wn, and generates the intermediate value Wn. Wn) is stored in the block corresponding to the nth step.

HAS function calculation consists of 80 steps by repeating 20 steps 4 times, and 16 received from input buffer 1 and 4 generated from HAS intermediate value calculation circuit 46 to perform 20 steps of operations. In total, a total of 20 median values (Wn) are required. Therefore, the HAS intermediate value calculating circuit 46 includes a circuit for calculating the equation (2), and the intermediate value variable calculating section 42 selects the variable Wn 'necessary for the intermediate value calculation based on the equation (2).

W16 = W3 XOR W6 XOR W9 XOR W12

W17 = W15 XOR W2 XOR W5 XOR W8

W18 = W11 XOR W14 XOR W1 XOR W4

W19 = W7 XOR W10 XOR W13 XOR W0

Therefore, the common block of the storage block 41 is provided with 16 blocks for storing 16 intermediate values Wn received from the input buffer 1, and the SHA-1 block includes the SHA-1 intermediate value calculation circuit ( 64 blocks for storing 64 intermediate values Wn received from 44 are provided. In addition, the HAS block is provided with four blocks for storing four intermediate values Wn received from the HAS intermediate value calculating circuit 46.

The function processing unit 50 receives the intermediate value from the storage block 41 and applies it to the SHA-1 function or the HAS function, and outputs a result value through an operation corresponding to the function.

Here, SHA-1 divides 80 steps into 4 rounds and sets each round to 20 steps, and each step is calculated based on the functions and constants of Table 1. As in the SHA-1 algorithm, the HAS algorithm divides 80 steps into four rounds, and each round consists of 20 steps. Each step is calculated based on the functions and constants in Table 2.

round step function a constant One  0≤n≤19 F0 (B, C, D) = (B and C) or (! B and D) K0 = 00000000 2 20≤n≤39 F1 (B, C, D) = B XOR C XOR D K1 = 5a827999 3 40≤n≤59 F2 (B, C, D) = C XOR (B or! Z) K2 = 6ed9eba1 4 60≤n≤79 F3 (B, C, D) = B XOR C XOR D k3 = 8f1bbcdc

round step function a constant One  0≤n≤19 F0 (B, C, D) = (B and C) or (! B and D) K0 = 5a827999 2 20≤n≤39 F1 (B, C, D) = B XOR C XOR D K1 = 6ed9eba1 3 40≤n≤59 F2 (B, C, D) = (B and C) or (B and D) or (C and D) K2 = 8f1bbcdc 4 60≤n≤79 F3 (B, C, D) = B XOR C XOR D K3 = ca62c1d6

The SHA-1 algorithm and the HAS algorithm have the same structure, and the functions used in the algorithm are the functions (F0 (B, C, D), F1 (B, C) except the third round (1, 2, 4 rounds). , D) and F3 (B, C, D)) are all the same. Therefore, when the function processing unit 50 processes the two functions SHA-1 and HAS, it is preferable to share the operators commonly used in the first, second and fourth rounds of the two functions.

5 is a configuration diagram of a function calculation engine according to another embodiment of the present invention. In another embodiment of the present invention, in the calculation of hash functions SHA-1 and HAS similar to each other, a function processor 70 for calculating the two functions SHA-1 and HAS by sharing operators commonly used. An example of a function calculation engine is included. Referring to FIG. 5, the function calculation engine according to another embodiment of the present invention includes an input buffer 7, an intermediate value processor 60, and a function processor 70.

The input buffer 7 stores 512 bits of padded data for generating intermediate values and an initial value of 160 bits for processing the SHA-1 function and the HAS function.

The intermediate value processor 60 calculates the intermediate values required for the SHA-1 function and the HAS function based on Equation 1 and Equation 2, and transmits the intermediate values to the function processor 70.

The intermediate value processing unit 60 is preferably provided so that the algorithm can share a storage area for storing the intermediate value Wn common in the hash functions SHA-1 and HAS similar to each other. Although the median processing unit 60 in the embodiment of the present invention illustrates sharing a storage area for storing the median value Wn common to at least two or more functions, the present invention is not limited thereto. It may be a conventional circuit which can calculate and store the intermediate value Wn necessary for processing.

The function processor 70 calculates a function value by applying the initial value and the intermediate value to a predetermined function calculation circuit. The function processing unit 70 includes a selection circuit 71, a function value storage block 72, a function selection unit 73, a common function operation unit 74, and a differential function operation unit 75 to calculate a plurality of functions having different algorithms. And a carry adder 76, an output adder 77, and an output buffer 78.

The selection circuit 71 receives the control signal according to the repetition of the function operation, selects a signal corresponding thereto, and transmits the selected signal to the function value storage block 72.

The function value storage block 72 blocks and stores the function value generated according to the repetition of the initial value and the function operation in 32 bits.

The common function calculating unit 74 is applied to a function that performs operations of 1, 2, and 4 rounds that are common to the SHA-1 function and the HAS function in a function value which is blocked and stored in 32 bits in the function value storage block 72.

The differential function calculating unit 75 includes a SHA-1 function calculating unit 751 and a HAS function calculating unit 752, and processes operations of different parts in the operation of the two functions (SHA-1 function, HAS function). do. That is, the SHA-1 function operator 751 processes the three round operations shown in Table 1, and the HAS function operator 752 processes the three round operations shown in Table 2.

The carry adder 76 receives the intermediate value Wn received from the intermediate value processing unit, the function value calculated by the common function calculating unit 74 or the differential function calculating unit 75 and the data stored in the function value storing block 72. The data is added to the SHA-1 function or the HAS function, and the added data is transmitted to the selection circuit 71.

The output adder 77 adds the blocked function value stored in the function value storage block 72 to the initial value blocked by the predetermined bit in the input buffer 7 and transmits it to the output buffer 78, and output buffer 78 ) Buffers the output signal of the output adder 77.

Hereinafter, the operation of the hash function calculation engine according to an embodiment of the present invention will be described with reference to SHA-1 function calculation.

The input buffer 7 divides the padded data into 512 bits by 32 bits to generate 16 intermediate values, and stores the intermediate values in the common block of the storage block 81.

The median variable calculator 82 receives the SHA-1 function calculation processing signal and calculates the median variable Wn 'corresponding to the SHA-1 function. Since the intermediate values in steps 0 to 15 use 16 intermediate values (Wn) stored in the common block, the intermediate value calculation is required for the intermediate value calculation for the intermediate values (W16) in steps 16 to 79 (W79). Calculate (Wn '; (n-3), (n-8), (n-14), (n-16)) in that order.

The intermediate value variable Wn 'calculated by the intermediate value variable calculating unit 82 is transmitted to the SHA-1 intermediate value selection buffer 83, and the intermediate value selection buffer 83 receives the intermediate value selection buffer 83 from the storage block 81. The median value Wn corresponding to the median variable Wn 'is extracted and stored. The intermediate value Wn stored in the SHA-1 intermediate value selection buffer 83 is transmitted to the SHA-1 intermediate value calculation circuit 84 and processed by the calculation circuit corresponding to Equation 1 above. The calculated intermediate value Wn is stored in the SHA-1 block of the storage block 81.

For example, in order to calculate the intermediate value W16 in step 16, the variables of (n-3), (n-8), (n-14), and (n-16) are required. Calculate 13, 12, 2, 3 by substituting n = 16. The calculated intermediate value variable W16 '13, 12, 2, 0 is transferred to the intermediate value selection buffer 83, and the intermediate value selection buffer 83 is W13, W12, of the common block in the storage block 81; Extract W2 and W3 and temporarily store them. W13, W12, W2, and W3 are transmitted to the SHA-1 intermediate value calculating circuit 84 to generate the 16th intermediate value W16 through the operation of Equation 1, and the generated 16th intermediate value W16 is stored. It is stored in the SHA-1 block of the block 81.

In the intermediate value calculation, when the intermediate value variable calculation unit 82 receives a HAS function calculation processing signal, the intermediate value Wn in steps 0 to 15 is common to 16 intermediate values Wn stored in the common block. Therefore, the median value required for HAS function calculation requires the median value of 16 steps (W16) to the median value of 19 steps (W19). In the case of the HAS function, since only four intermediate values Wn need to be generated, the intermediate value variable calculating unit 82 does not perform the operation of the intermediate value variable Wn 'necessary for the intermediate value operation, and calculates the intermediate value corresponding to each step. Save the median variables needed for. Therefore, the intermediate value variable calculating unit 82 selects the intermediate value variable Wn 'necessary for the intermediate value Wn operation corresponding to each step, and transmits the intermediate value variable Wn' to the HAS intermediate value selection buffer 85 and the HAS intermediate value selection buffer. 85 stores an intermediate value corresponding to the intermediate value Wn. The HAS intermediate value calculation circuit 86 generates the intermediate value Wn from the intermediate value Wn stored in the HAS intermediate value selection buffer 85 through a calculation circuit corresponding to Equation 2 above to generate the intermediate value Wn of the storage block 81. Store in HAS block.

On the other hand, the 160-bit initial value divided into five 32-bits in the input buffer 7 is transmitted to the selection circuit 91, and the selection circuit 91 receives a function calculation processing signal and converts the initial value to a function value storage block. Transmit to 92. At this time, the initial value is divided into five blocks (A, B, C, D, E) and stored. The initial values of the B, C, and D blocks required for the function calculation among the initial values divided into five blocks are transmitted to the common function calculator 94 and the differential function calculator 95. The function selector 93 checks the steps of the SHA-1 function or the HAS function operation and transmits a function operation signal corresponding thereto. The operation of the function is the 0th step of the SHA-1 function because it illustrates the operation of receiving the initial value of the SHA-1 function. Since both the SHA-1 function and the HAS function operate using the same function except for the third round, the function selector 93 transmits an operation signal to the common function operator 94. Accordingly, the common function calculating unit 94 performs an operation corresponding to F0 (B, C, D) in Table 1, and outputs an operation result.

Meanwhile, the first shifter 971 performs a 5-bit circular left operation on the data stored in the A block of the function value storage block 92 and transmits the data to the first carry adder 961. The first carry adder adds the data received from the first shifter 971 to the data received from the common function calculator 94 and transmits the received data to the second carry adder 962. The second carry adder 962 adds the data received from the E block of the function value storage block 92 to the data received from the first carry adder 961 and transmits the received data to the third carry adder 963. The third carry adder 963 receives and adds the 0th intermediate value of the intermediate value storage block 81 to the data received from the second carry adder 962 and transmits the result value to the fourth carry adder 964. do. The fourth carry adder 964 receives the K0 value from the constant block 966 in which the constant values of Table 1 are stored and adds the data received from the third carry adder 963, and adds the result to the carry transfer adder 965. To send). The carry delivery adder 965 transmits the data received from the fourth carry adder 964 to the selector a located at the most significant bit of the selection circuit 91.

On the other hand, the initial value stored in the A block of the function value storage block 92 is transmitted to the selector (b) located second from the most significant bit of the selection circuit 91, and stored in the A block of the function value storage block 92. The initial value is a 30 bit circular left operation and sent to selector c located third from the most significant bit. Further, the initial value stored in the C block of the function value storage block 92 is transmitted to the selector d located fourth from the most significant bit of the selection circuit 91, and stored in the D block of the function value storage block 92. The initial value is sent to the selector e located at the least significant bit.

In addition, the data stored in blocks of five (A, B, C, D, E) in the function value storage block 92 is stored in the five adders (add0, add1, add2, add3, are sent to add4) in order and added to the initial value.

The initial value input from the input buffer 7 is performed by repeating the above-described process to repeat the operation of a total of 80 steps, and the calculated result is continuously added through the output adder 98, and the added result is output buffer ( 99) to buffer 160-bit signals.

On the other hand, in the repetition of the operation, when calculating the third round of SHA-1 (see Table 1), the function selector 93 operates the SHA-1 function calculating unit 951 and the third round of the HAS (Table 2). Operation), the HAS function operation unit is operated to calculate a function corresponding to each algorithm. In addition, when calculating the HAS, a third shifter 973 and a fourth shifter 974 are used instead of the first shifter 971 and the second shifter 972. At this time, the third shifter 973 receives the information of each step from the function selector 93 and performs circular left operation by the number of bits shown in Table 3, and performs the operation of 20 steps by repeating four rounds. . In addition, the fourth shifter 974 receives information of each step from the function selector 93 and performs the circular left operation by the number of bits shown in Table 4.

step Stage 1 Tier 2 Tier 3 4 steps 5 steps 6 steps 7 steps 8 levels 9 steps 10 steps beat 5 11 7 15 6 13 8 14 7 12 step 11 steps 12 steps Step 13 Step 14 Step 15 16 steps Step 17 18 steps Step 19 20 steps beat 9 11 8 15 6 12 9 14 5 13

round step beat One  0≤n≤19 10 2 20≤n≤39 17 3 40≤n≤59 25 4 60≤n≤79 30

Although the present invention has been described above by means of limited embodiments and drawings, the present invention is not limited thereto and will be described below by the person skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of the claims.

As described above, according to the common engine for hash function calculation of the present invention, by designing a hash function calculation engine that shares the same hardware components in order to process a plurality of functions having a similar structure of the algorithm, it is unnecessary to the function processing The device can be reduced.

Claims (8)

An input buffer for generating and storing blocks of input data in predetermined bit units; An intermediate value processing unit for storing intermediate values required for a plurality of different hash function calculations, but sharing common intermediate values and generating intermediate values for generating non-common intermediate values; And A function processing unit configured to calculate a plurality of hash functions different from each other by using an intermediate value necessary for the hash function operation, the same operation sharing a function, and a different operation for each hash function separately; Common engine for hash function operation, characterized in that. delete The method of claim 1, wherein the intermediate value processing unit A storage block for storing an intermediate value input from the input buffer and an intermediate value generated through an operation; An intermediate value variable calculating unit for calculating an intermediate value necessary for generating an intermediate value; A plurality of intermediate value selection buffers for extracting and storing an intermediate value corresponding to the value received from the intermediate value variable calculator from the storage block; And And a plurality of intermediate value calculating circuits for generating a new intermediate value using the value stored in the intermediate value selection buffer and transmitting the generated intermediate value to the storage block. engine. The method of claim 1 or 3, wherein the function processing unit A common function calculation unit for calculating a function of a part common to a plurality of hash functions having different algorithms; A plurality of differential function calculators for calculating functions of different parts of the plurality of hash functions having different algorithms; And And a function selector which checks the hash function operation step and selects an operation of the common function operation unit or the differential function operation unit. An input buffer for generating and storing blocks of input data in predetermined bit units; An intermediate value processing unit for generating and storing intermediate value variables required for a plurality of hash function calculations having different algorithms; And The algorithm operates on a plurality of different hash functions, the same operation is a shared operation, the integrated operation, and the different operation function processing unit for a separate operation for each hash function; common for a hash function operation engine. The method of claim 5, wherein the intermediate value processing unit Common engine for hash function operation, characterized in that the algorithms share a common intermediate value in a plurality of different hash functions. The method of claim 5, wherein the intermediate value processing unit A storage block for storing an intermediate value input from the input buffer and an intermediate value generated by an operation; An intermediate value variable calculating unit for calculating an intermediate value necessary for generating an intermediate value; A plurality of intermediate value selection buffers for extracting and storing an intermediate value corresponding to the intermediate value variable received from the intermediate value variable calculator from the storage block; And And a plurality of intermediate value calculating circuits for generating a new intermediate value using the value stored in the intermediate value selection buffer and transmitting the generated intermediate value to the storage block. engine. The method of claim 5, wherein the function processing unit A common function calculation unit for calculating a function of a part common to a plurality of hash functions having different algorithms; A plurality of differential function calculators for calculating functions of different parts of the plurality of hash functions having different algorithms; And And a function selector which checks the hash function operation step and selects an operation of the common function operation unit or the differential function operation unit.

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