KR100579074B1 - Cam and Crank Signal Generator of Electric Control Engine - Google Patents

Abstract

The present invention relates to a cam / crank signal generator for a simulator for an electronic control engine, characterized by eliminating the hassle of testing on a real engine equipped with a real system when developing an electronic control engine. A clock generator which generates a sinusoidal signal from 0.1 Hz to 20 KHz and is made of a TTL level square wave signal to be used as a system clock; A counter unit for generating an address for reading Speed Generation Data and TDC Index Signal Data embedded in the EPROM; An EPROM that incorporates Speed Generation Data (crank signal) and TDC Index Signal Data (cam signal) and outputs data in synchronization with the clock of the counter; An address selector for selecting 4, 5, 6, and 8 cylinders of a simulation engine when reading data patterns stored in the EPROM; A buffer which temporarily stores data read from the EPROM and drives a signal output circuit; A signal output unit converting the analog signal so that the engine controller can recognize the cam signal from the data read from the buffer; Characterized in that it comprises a display unit for displaying the RPM of the engine under simulation by the signal output unit.

Engine, simulator, address selector

Description

Cam and Crank Signal Generator of Electric Control Engine {Cam and Crank Signal Generator of Electric Control Engine}

1 is a conventional cam / crank signal sensing configuration diagram.

2 is a block diagram of the present invention.

3 is an embodiment of the present invention.

4 is an exemplary view showing a display unit configuration of the present invention.

Explanation of symbols on the main parts of the drawings

10: clock generator 20: counter circuit

30: EPROM 40: address selector

50: buffer 60: signal output circuit

70: display unit

The present invention relates to a cam / crank signal generator for a simulator of an electronic control engine. In particular, it is possible to eliminate the hassle of testing on a real engine equipped with a real system and to enable a simulator-type test in the development of an electronic control engine. The present invention relates to a cam / crank signal generator for a simulator of an electronic control engine.

As shown in FIG. 1, a conventional method for receiving a signal for a cam / crank has been used by attaching a mechanical ring gear to generate a signal through a VR sensor on the crankshaft and the camshaft.

The problem is that the angle and frequency of the signal sensed by the camshaft and crankshaft change when the system (Install method, Injecton Timing calculation method) is changed. There is a feeling.

That is, in the conventional system, since the sensing wheel and the sensing angle are determined according to the actual engine model, in order to check cams and cranks of various models, the sensing wheels for each model must be separately provided. It was difficult to test the characteristics of several types of cams / cranks at once due to problems such as the need to refit the sensing angles.

The present invention is to solve the above problems,

In developing an engine control apparatus for an electronic control engine, the purpose of the present invention is to provide a circuit for making and using a simulator in order to eliminate the trouble of checking in a real engine state when checking a development function.

In other words, a cam and crank signal, which is the basis of the same control as a real engine, is virtually input and inputted, so that a simulator capable of accurately and conveniently checking the control function even when the cylinders are different for each engine is possible.

As a means for achieving the above object,

The present invention comprises a clock generator which is composed of a Vlotage controlled oscillator and a peripheral circuit and generates a sinusoidal signal from 0.1 Hz to 20 KHz and is made of a square wave signal having a TTL level to be used as a clock of the system;

A counter unit receiving a reference clock from the clock generator and generating an address for reading Speed Generation Data and TDC Index Signal Data embedded in an EPROM;

 An EPROM that incorporates Speed Generation Data (crank signal) and TDC Index Signal Data (cam signal) and outputs data in synchronization with the clock of the counter;

An address selector for selecting 4, 5, 6, and 8 cylinders of a simulation engine when reading data patterns stored in the EPROM;

A buffer which temporarily stores data read from the EPROM and drives a signal output circuit;

A signal output unit converting the analog signal so that the engine controller can recognize the cam signal from the data read from the buffer;

Characterized in that it comprises a display unit for displaying the RPM of the engine under simulation by the signal output unit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a configuration diagram of the present invention, Figures 3 and 4 are detailed circuit diagrams, as shown,

A clock generator (10) composed of a Vlotage controlled oscillator and a peripheral circuit, generating a sinusoidal signal from 0.1 Hz to 20 KHz and being made of a square wave signal having a TTL level to be used as a clock of the system;

A counter unit 20 which receives a reference clock from the clock generator 10 and generates an address for reading Speed Generation Data and TDC Index Signal Data embedded in an EPROM;

 An EPROM 30 incorporating Speed Generation Data (crank signal) and TDC Index Signal Data (cam signal) and outputting data in synchronization with the clock of the counter unit 20;

An address selector 40 for selecting 4, 5, 6, and 8 cylinders of a simulation engine when reading the data pattern stored in the EPROM 30;

A buffer 50 for temporarily storing data read from the EPROM 30 and driving a signal output circuit;

A signal output unit 60 for converting the analog signal so that the engine controller can recognize the cam signal from the data read from the buffer 50;

The signal output unit 60 is configured to include a display unit 70 for displaying the RPM of the engine under simulation.

The clock generator 10 is implemented as a PLL dedicated IC (CD4046BC) and performs the Vlotage Controlled Oscillator function to provide the operation timing of the present invention.

The main peripheral circuit consists of basic oscillation RC (R3, C1) and VCO Input Circuit (R4, VR1, VR2, VR3, C3), and the VCO Input Voltage sets the lower limit to VR3 and the upper limit to VR1. The input voltage can be adjusted to VR2 within the set range, and the VCO input voltage is filtered by the R4 and C3 integrating circuit.

The sine wave output whose frequency is varied by the VCO input voltage is converted into a square wave by the inverter IC U3 having hysteresis and used as a clock of the counter IC U2 and the buffer U5. The output speed of the built-in data (Cam, Crank Data Pattern) is determined, and the data pattern speed is equivalent to the engine RPM.

The counter unit 20 is composed of a power on reset circuit and a 14-stage binary counter, and generates an address signal in synchronization with a clock.

In this circuit, only 12-stage output is used, and when more data patterns are needed in the EPROM 30, it is made to be expandable.

The Power On Reset circuit is composed of RC (R2, C2), Diode (D1), and Inverter IC (U3), and the reset time of the counter IC is determined by RC charging time. ) Is configured to discharge within a short time through the diode (D1).

The EPROM (U4, 30) is a place for storing data for creating a cam and crank cipheral, and implemented with 27C64, and creates a desired data pattern and creates an address map for each engine type (in the case of the same engine). The data pattern is stored in the address map.

Data pattern creation is made by dividing cam and crank signal data to different bit allocations, and adjusting address intervals in consideration of the generation order of the two signals and the necessary phase difference.

The width of the signal is determined by the retention time of the data bits, which can be maintained to the next consecutive address of the data bits in the EPROM.

The engine controller determines the firing order of the cylinder based on the cam signal pattern and calculates the engine RPM and injection timing based on the crank signal pattern.

The number of cam and crank signals generated per one revolution of the CRS and the phase difference between the two signals can be easily generated by manipulating the data pattern, which is very advantageous when the timing system of the real engine changes.

The address selector 40 is composed of a selector switch to select a data pattern suitable for a model of the engine to be simulated when reading the data pattern stored in the EPROM, and the selector switch state is determined by an address map.

In the present invention, the lower 9-Bit is designed to address EPROM directly to the output of the counter U2 and the upper 4-Bit to address through a selector switch to distinguish the address map of the data pattern.

The buffer 50 uses a dedicated IC 74HC574 and temporarily stores the data read from the EPROM, and since the output control terminal is enabled at zero level, the signal output circuit 60 is always synchronized with the control device clock. Is output to

The signal output circuit 60 converts the digital signal output from the buffer 50 into a sine wave analog signal similar to a real VR sensor in synchronization with a clock.

The signal output circuit 60 is composed of the crank signal calculus circuits C4-R14 and C6 and the cam signal calculus circuits C5-R16 and C7. At the rising and falling edges, a differential signal is created in the CR differential circuit, and this signal is integrated at C6 and C7, respectively, and receives a sinusoidal signal and converts it into a pulse type signal for the digital system.

The circuit structure of the display unit 70 is composed of Harris's Icm7216 (Frequency Counters / Timers, U6) and four 7-segments, which are dedicated ICs, and the information displayed in the 7-seg. Is the RPM of the engine to be simulated.

The 7-Segment Driver (U6) Frequency (RPM) has a data pattern embedded in the EPROM and is output in synchronization with the system clock through the buffer (U5). This data pattern is determined by the number of teeth of the ring gear mounted on the CRS used in the timing system of the actual engine. The data pattern embedded in the EPROM can be output by making one pattern in 1-Cycle of the crank signal data pattern.

That is, when one data pattern is output when the crank signal data pattern is output as many as the number of ring gear teeth, it is equal to RPM.

Therefore, in developing the engine control apparatus of the electronic control engine as in the present invention, it is convenient to manufacture and utilize a simulator to eliminate the trouble of checking in a real engine state when checking a development function.

The effect of the present invention eliminates the hassle of testing on a real engine equipped with a real system when developing an electronic control engine, and enables a simulator-type test, and responds without changing hardware when changing or developing a timing system of an electronic control engine. This has a very easy effect.

In addition, the RPM of the engine can be adjusted using only the variable resistor, and the RPM of the engine under simulation is displayed as a number, which is very convenient for testing.

Claims (1)

A clock generator (10) composed of a Vlotage controlled oscillator and a peripheral circuit, generating a sinusoidal signal from 0.1 Hz to 20 KHz and being made of a square wave signal having a TTL level to be used as a clock of the system; A counter unit 20 which receives a reference clock from the clock generator 10 and generates an address for reading Speed Generation Data and TDC Index Signal Data embedded in an EPROM;  An EPROM 30 incorporating Speed Generation Data (crank signal) and TDC Index Signal Data (cam signal) and outputting data in synchronization with the clock of the counter unit 20; An address selector 40 for selecting 4, 5, 6, and 8 cylinders of a simulation engine when reading the data pattern stored in the EPROM 30; A buffer 50 for temporarily storing data read from the EPROM 30 and driving a signal output circuit; A signal output unit 60 for converting the analog signal so that the engine controller can recognize the cam signal from the data read from the buffer 50; And a display unit (70) for displaying the RPM of the engine under simulation by the signal output unit (60).

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