KR100571276B1 - Sense amplifier having pull-up driver made up of nonvolatile memory cell - Google Patents

Abstract

The present invention is to provide a sense amplifier having a pull-up driver consisting of a memory cell that can improve the operating characteristics by ensuring the same sensing margin on all chips, to this end, in the present invention, the read, program verification and erase verification A plurality of pull-ups having different threshold voltages through a program operation and an erase operation to secure different sensing margins during the read, the program verification, and the erase verification during sensing of the data from the main memory cell; A pull-up driver configured to pull-up driving the output terminal of the sensing unit, a program and erase operation controller which performs a program and erase operation on the pull-up memory cell, the read, the program verification, During the erase verification, the pull-up memory cell current is reset to an output terminal of the sensing unit. Providing a sense amplifier comprising an output driver to output a driving up the parts of the sensing output signal and the up-switch driving unit for the pull-in the output of the sensing parts of the pool.

Nonvolatile Memory Cells, Flash Memory Cells, Sense Amplifiers, Read, Program Verification, Erase Verification

Description

SENSE AMPLIFIER HAVING PULL-UP DRIVER MADE UP OF NONVOLATILE MEMORY CELL}

1 is a distribution diagram of threshold voltages after program and erase operations of a typical memory cell.

2 is a block diagram showing a sense amplifier according to the prior art.

3 is an operational waveform diagram of the sense amplifier shown in FIG. 2;

4 is a block diagram showing a sense amplifier according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

21, 44: sensing unit

22, 42: pull-up driver

23, 43: switching unit

24, 45: output driver

41: program and erase operation control unit

411: erasing switching unit

412: word line switching unit

413 to 415: bit line switching unit

416: source voltage switching unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier having a full-up driver consisting of nonvolatile memory cells, and more particularly, to reading and program verification of flash memory devices. The present invention relates to a sense amplifier for sensing data during program verify and erase verify operations.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) devices, are volatile and fast data input / output that loses data over time. Input is largely classified into non-volatile (Read Only Memory) products that maintain their state and are slow in input / output of data. ROM products can be classified into ROM, PROM (Programmable ROM), EPROM (Erasable PROM) and EEPROM (Electrically EPROM). Among these ROM products, data can be programmed and erased by electric method. The demand for EEPROM is on the rise.

In general, an EEPROM or a flash EEPROM having a batch erase function has a stack type gate structure in which a floating gate and a control gate are stacked. Flash memory cells are widely used in portable electronics such as notebooks, PDAs, cellular phones, computer BIOS, and printers. From a circuit point of view, a flash memory cell is a unit string in which n cell transistors are connected in series to form a unit string, and these unit strings are paralleled between a bit line and a ground line. NAND type and each cell transistor are connected in parallel between the bit line and the ground line in parallel to the NAND type, which is advantageous for high integration.

1 is a threshold voltage distribution diagram according to program and erase operation states of a general flash memory device.

As shown in FIG. 1, the threshold voltages of the program and erase operation states of the flash memory device are widely distributed as the capacity of the flash memory device increases. Therefore, when the flash memory device is read, a defect occurs when the margin is insufficient due to the threshold voltage distribution. Accordingly, when sensing the flash memory device using the sense amplifier, not only read but also program verify and erase verify operations are performed to secure a sensing margin of the flash memory device. This sensing margin is secured by driving transistors of different sizes (Width / Length) during read, program verify, and erase verify operations.

FIG. 2 is a circuit diagram showing a configuration of a sense amplifier according to the prior art for performing read, program verify and erase verify operations of a flash memory device, and FIG. 2 is a read operation waveform diagram.

As shown in FIG. 2, a sense amplifier according to the related art includes a sensing unit 21 for reading data from a memory cell MC during read, program verify, and erase verify operations, and read, program verify, and the like. A pull-up driver 22 for pull-up driving the output terminal of the sensing unit 21 to secure different sensing margins during an erase verify operation, and a pull-up driver during read, program verify, and erase verify operations. And a switching unit 23 for connecting the output terminal of the sensing unit 21 and an output driver 24 for outputting the output of the sensing unit 21.

Hereinafter, the operating characteristics of the sense amplifier according to the prior art having such a configuration will be described.

First, a read operation will be described with reference to FIG. 3. In the read mode, the read enable bar signal RDENB is input to the gate of the PMOS transistor P4 of the switching unit 23 at a low level 'O'. Accordingly, the PMOS transistor P4 is turned on and the current flowing through the PMOS transistor P1 of the pull-up driver 22 is supplied to the output terminal of the sensing unit 21. In this state, the sense amplifier enable signal SAEN is input to the gate of the NMOS transistor N3 of the sensing unit 21 at a high level '1' and the sense amplifier enable bar signal SAENB. Is inverted through the inverter INV1 and input to the gates of the PMOS transistor P7 and the NMOS transistor N2 at a high level, respectively, the NMOS transistors N2 and N3 are turned on, and the PMOS transistor P7 is turned on. It is turned off and a current path is formed between the bit line BL and the PMOS transistor P1 which is a pull-up transistor.

In this state, when the memory cell MC is in the program state, the current provided through the PMOS transistor P1, which is a pull-up transistor, does not flow into the ground terminal through the memory cell MC, but instead of the sensing unit 21. Drive the output stage high-up. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 24 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current provided through the PMOS transistor P1 flows to the ground terminal via the PMOS transistor P4, the NMOS transistors N2 and N3, and the memory cell MC. . Accordingly, the output terminal of the sensing unit 21 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

The erase verification operation will be described. In the erase verify mode, the erase verify enable bar signal EVENB is input to the gate of the PMOS transistor P5 of the switching unit 23 at a low level. Accordingly, the PMOS transistor P5 is turned on and the current supplied through the PMOS transistor P2 which is a pull-up transistor is supplied to the output terminal of the sensing unit 21. In this state, the sense amplifier enable signal SAEN is input to the gate of the NMOS transistor N3 at a high level, and the sense amplifier enable bar signal SAENB is inverted through the inverter INV1, and the PMOS transistor ( When input to the gates of the P7 and the NMOS transistor N2, respectively, the NMOS transistors N2 and N3 are turned on, and the PMOS transistor P7 is turned off to PMOS, which is a bit line BL and a pull-up transistor. A current path is formed between the transistors P2.

In this state, when the memory cell MC is in the program state, the current provided through the PMOS transistor P2, which is a pull-up transistor, does not flow into the ground terminal through the memory cell MC, but instead of the sensing unit 21. Drive the output stage high-up. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 24 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current provided through the PMOS transistor P2 flows to the ground terminal via the PMOS transistor P5, the NMOS transistors N2 and N3, and the memory cell MC. . Accordingly, the output terminal of the sensing unit 21 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

The program verification operation will be described. In the program verify mode, the program verify enable bar signal PVENB is input to the gate of the PMOS transistor P6 of the switching unit 23 at a low level. Accordingly, the PMOS transistor P6 is turned on and the current supplied through the PMOS transistor P3, which is a pull-up transistor, is supplied to the output terminal of the sensing unit 21. In this state, the sense amplifier enable signal SAEN is input to the gate of the NMOS transistor N3 at a high level, and the sense amplifier enable bar signal SAENB is inverted through the inverter INV1, and the PMOS transistor ( When input to the gates of the P7 and the NMOS transistor N2, respectively, the NMOS transistors N2 and N3 are turned on, and the PMOS transistor P7 is turned off to PMOS, which is a bit line BL and a pull-up transistor. A current path is formed between the transistors P3.

In this state, when the memory cell MC is in the program state, the current provided through the PMOS transistor P3, which is a pull-up transistor, does not flow into the ground terminal through the memory cell MC, but instead of the sensing unit 21. Drive the output stage high-up. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 24 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current provided through the PMOS transistor P3 flows to the ground terminal via the PMOS transistor P6, the NMOS transistors N2 and N3, and the memory cell MC. . Accordingly, the output terminal of the sensing unit 21 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

In the above-described sense amplifier according to the related art, the width / length of each pull-up transistor P1 to P3 of the pull-up driver 22 in order to obtain the read, erase verify and program verify margins as shown in FIG. 1. To adjust the amount of current. However, when the widths / lengths of the pull-up transistors P1 to P3 are differently formed, defects due to sensing margins are caused due to different characteristics occurring between processes.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and provides a sense amplifier having a pull-up driver composed of a flash memory cell which can improve operating characteristics by securing the same sensing margin on all chips. Its purpose is to.

According to an aspect of the present invention, there is provided a sensing unit configured to sense data from a main memory cell during read, program verify, and erase verify, and different sensing margins during read, program verify, and erase verify. A pull-up driver comprising a plurality of pull-up memory cells having different threshold voltages through a program operation and an erase operation to secure a voltage, and a pull-up driver for pull-up driving an output terminal of the sensing unit. A program and erase operation control unit for performing a program and erase operation with respect to the output unit of the sensing unit by providing a pull-up memory cell current to the sensing unit during the read, program verify, and erase verify operations. An output drive for outputting an output signal of the switching unit and the sensing unit of the pull-up driving unit Provide a sense amplifier that includes the server.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

4 is a block diagram illustrating a sense amplifier in accordance with a preferred embodiment of the present invention.

As shown in FIG. 4, the sense amplifier according to the preferred embodiment of the present invention can control threshold voltages through program and erase operations to secure read, erase verify, and program verify margins as shown in FIG. 1. And a pull-up driver 42 composed of flash memory cells FC1 to FC3. In this case, each of the flash memory cells FC1 to FC3 performs a program operation through a channel hot electron injection method, and performs an erase operation by using an F-N tunneling (Fouler Nordheim Tunneling) method.

First, the bias voltages for performing the read, program and erase operations of the flash memory cells FC1 to FC3 will be briefly described. The bias voltage is shown in Table 1 below.

Gate voltage (VG) Dray Voltage (VD) Source voltage (VS) Bulk voltage (VB) program 9 V 5 V 0 V 0 V elimination -7.5V Floating Floating 9 V Reading 4V 0.8 V 0 V 0 V

For example, in the preferred embodiment of the present invention, the flash memory cells FC1 to FC3 perform erase operations on the flash memory cells FC2 and the flash memory cells FC1 and FC3 to have different sensing margins. Perform the program operation. At this time, the flash memory cell FC1 performs a program operation to be lower than the threshold voltage of the flash memory cell FC3. To this end, the drain bias voltage VD1 of the flash memory cell FC1 is lower than the drain voltage VD3 of the flash memory cell FC3 during the program operation of the flash memory cell FC1. Detailed description thereof will be described later.

As described above, in order to control the threshold voltages of the flash memory cells FC1 to FC3 by performing program and erase operations on the flash memory cells FC1 to FC3, the sense amplifiers according to the preferred embodiment of the present invention may be programmed and erased. An operation control unit 41 is included. The program and erase operation controller 51 may include an erase switch 411, a word line switch 412, first to third bit line switches 413 to 415, and a source voltage switch 413. Is done.

The erase switching unit 411 outputs a negative high voltage VEEI, a positive high voltage VPPI, and an internal voltage VDD according to the read enable signal CVTRDEN and the erase enable signal EREN. . Here, the negative high voltage VEEI is approximately -7.5V, the positive high voltage VPPI is approximately 9V, and the internal voltage VDD is approximately 4V, which is higher than the power supply voltage VCC.

The word line switching unit 412 simultaneously transmits the gate voltage VG to each gate of the flash memory cells FC1 to FC3 according to the read enable signal CVTRDEN, the erase enable signal EREN, and the program enable signal PGMEN. ). In this case, the gate voltage VG becomes one of a negative high voltage VEEI, a positive high voltage VPPI, and an internal voltage VDD.

The first bit line switching unit 413 is operated according to the first enable signal EN1 to supply the read signal CVTRD to the drain of the flash memory cell FC1 or to detect the drain current from the drain. At this time, the read signal CVTRD is supplied from the outside as the drain voltage VD1 of the flash memory cell FC1 during the program operation of the flash memory cell FC1, and its size is appropriately changed according to the operation. On the other hand, the drain voltage VD1 is lower than the drain voltage VD3 of the flash memory cell FC3 during the program operation, and becomes about 0.8 V during the read operation.

The second bit line switching unit 414 is operated according to the second enable signal EN2 to supply the read signal CVTRD to the drain of the flash memory cell FC2 or to detect the drain current from the drain. At this time, the read signal CVTRD becomes the drain voltage VD2 of the flash memory cell FC2.

The third bit line switching unit 415 is operated according to the third enable signal EN3 to supply the read signal CVTRD to the drain of the flash memory cell FC3 or to detect the drain current from the drain. At this time, the read signal CVTRD is externally supplied as the drain voltage VD3 of the flash memory cell FC3 during the program operation of the flash memory cell FC3, and its size is appropriately changed according to the operation. On the other hand, the drain voltage VD3 is higher than the drain voltage VD1 of the flash memory cell FC1 during the program operation, and becomes about 0.8 V during the read operation.

The source voltage switching unit 416 operates according to the source voltage control signals VSC1 and VSC2 of the erase switching unit 411 to supply the source voltages VS1 to VS3 to the sources of the flash memory cells FC1 to FC3. To this end, it consists of NMOS transistors N1 to N3 operated by the control signal VSC1 and PMOS transistors P1 to P3 operated by the control signal VSC2. The NMOS transistors N1 to N3 are connected to the source terminals of the flash memory cells FC1 to FC3, respectively, and supply the ground voltage VSS to the source terminals of the flash memory cells FC1 to FC3 according to the control signal VSC1. The PMOS transistors P1 through P3 are connected to the source ends of the flash memory cells FC1 through FC3, respectively, and supply the power supply voltage VCC to the source ends of the flash memory cells FC1 through FC3 according to the control signal VSC2. .

In addition, the sense amplifier according to the preferred embodiment of the present invention includes a sensing unit 44 for reading data from the memory cell MC during read, program verify and erase verify operations, and at the time of read, program verify and erase verify operations. And a switching unit 43 for connecting the pull-up driver 42 and the output terminal of the sensing unit 44, and an output driver 45 for outputting the output of the sensing unit 44.

The sensing unit 44 senses data from the memory cell MC according to the sense amplifier enable signal SAEN and outputs the data. To this end, the sensing unit 44 includes NMOS transistors N4 to N6, a PMOS transistor P7, and an inverter INV1. For example, when the sense amplifier enable signal SAEN is enabled at a high level, the NMOS transistor N6 and the NMOS transistor N4 are turned on to turn on the bit line BL, the output driver 45, and the switching unit. A current path is formed between the 43. In this state, when the memory cell MC is in the program state, the voltage (approximately 0.8 V) applied to the bit line BL is supplied to the output driver 45 as it is, and in the erase state to the bit line BL. The applied voltage exits to the ground terminal through the memory cell MC. Accordingly, the sensing unit 44 outputs a high level output signal when the memory cell MC is in a program state, and outputs a low level output signal when the memory cell MC is in a program state.

The switching unit 43 includes the flash memory cells FC1 to FC3 and the sensing unit 44 according to the read enable bar signal RDENB, the erase verify enable bar signal EVENB, and the program verify enable bar signal PVENB. Connect the output terminal of. For example, in the read mode, the drain terminal of the flash memory cell FC1 and the output terminal of the sensing unit 44 are connected by the PMOS transistor P4 turned on by the read enable signal RDENB. In the erase verify mode, the drain terminal of the flash memory cell FC2 and the output terminal of the sensing unit 44 are connected by the PMOS transistor P5 turned on by the erase verify enable bar signal EVENB. In the program verify mode, the output terminal of the flash memory cell FC3 and the sensing unit 44 is connected to each other by the PMOS transistor P6 turned on by the program verify enable bar signal PVENB.

The output driver 45 includes an inverter INV2 to invert and output the output signal output from the sensing unit 44 or the driving signal supplied through the switching unit 43.

Hereinafter, the operating characteristics of the sense amplifier according to the preferred embodiment of the present invention described above will be described. For convenience of explanation, the program, erase, and trimming operations of the flash memory cells FC1 to FC3 will be described below.

First, an erase operation of the flash memory cell FC2 for securing an erase verify sensing margin in the erase verify mode will be described. When the erase enable signal EREN is enabled at the high level, the erase switching unit 411 is enabled to output the low level control signal VSC1 and to output the high level control signal VSC2. In addition, a high level bulk voltage VB is output. At this time, the low level control signal VSC1 is the ground voltage VSS, the high level control signal VSC2 is the internal voltage VDD, and the high level bulk voltage VB is the positive high voltage VPPI. Meanwhile, the word line switching unit 412 is enabled by the erase enable signal EREN to output a gate voltage VG having a negative high voltage VEEI. Accordingly, a negative high voltage VEEI of approximately -7.5 V is applied to the gate of the flash memory cell FC2, and the source is in a floating state by turning off the NMOS transistor N2 and the PMOS transistor P2, and in bulk. A positive high voltage (VPPI) of approximately 9V is applied. In addition, the drain of the flash memory cell FC2 is maintained in a floating state by the second bit line switching unit 414 and the switching unit 43. Thus, the flash memory cell FC2 is erased.

The trimming operation is performed on the erased flash memory cell FC2 by using the second bit line switching unit 414. First, the trimming operation is an operation of repeatedly erasing and reading the flash memory cell FC2 until the sensing margin reaches a threshold voltage set to have the lowest threshold voltage. For example, when the read enable signal CVTRDEN is enabled at a high level in order to read the current of the erased flash memory cell FC2, the erase switching unit 411 outputs a high level control signal VSC1. The low level control signal VSC2 and the bulk voltage VB are output. At this time, the high level control signal VSC1 is the internal voltage VDD, and the low level control signal VSC2 and the bulk voltage VB are the ground voltage VSS. Meanwhile, the word line switching unit 412 enabled by the read enable signal CVTRDEN outputs the internal voltage VDD to the gate of the flash memory cell FC2. At this time, the internal voltage VDD is 4V. In this state, when the second enable signal EN2 is enabled at the high level, the second bit line switching unit 414 is enabled to supply the read voltage CVTRD to the drain of the flash memory cell FC2. . At this time, the read voltage CVTRD is approximately 0.8V. Accordingly, the internal voltage VDD of approximately 4 V is applied to the gate of the flash memory cell FC2, the NMOS transistor N2 is turned on to apply the ground voltage VSS to the source, and the ground voltage V is applied to the bulk. VSS) is applied, and a drain voltage VD2 of 0.8V is applied to the drain. Thus, a read operation to the flash memory cell FC2 is performed. The cell FC2 current thus read is output through the second bit line switching unit 414.

The trimming operation (ie, erase and read operation) for the flash memory cell FC2 is repeatedly performed until the threshold voltage of the flash memory cell FC2 is equal to the set threshold voltage.

Meanwhile, a program operation of the flash memory cell FC1 for securing the read sensing margin in the read mode will be described. First, when the read enable signal CVTRDEN is enabled, the erase switching unit 411 outputs a high level control signal VSC1 and a low level control signal VSC2 and a bulk voltage VB. The word line switching unit 412 outputs the gate voltage VG of the positive high voltage VPPI by the program enable signal PGMEN. In this state, when the first enable signal EN1 is enabled, the first bit line switching unit 413 outputs a drain voltage VD1 having approximately 5V. At this time, the drain voltage VD1 is provided from the read voltage CVTRD. Accordingly, a positive high voltage VPPI of about 9 V is applied to the gate of the flash memory cell FC1, the NMOS transistor N1 is turned on to apply a ground voltage VSS to the source, and a ground voltage (VSS) to the bulk. VSS is applied, and a drain voltage VD1 of 5V is applied to the drain. Therefore, the flash memory cell FC1 is programmed to raise the threshold voltage higher than the threshold voltage of the erase state.

The trimming operation is performed on the flash memory cell FC1 programmed as described above using the first bit line switching unit 413. First, the trimming operation is an operation of repeatedly performing a program operation and a read operation until the threshold voltage is set after programming the flash memory cell FC1. For example, when the read enable signal CVTRDEN is enabled at a high level in order to read the current of the programmed flash memory cell FC1, the erase switching unit 411 outputs a high level control signal VSC1. The low level control signal VSC2 and the bulk voltage VB are output. At this time, the high level control signal VSC1 is the internal voltage VDD, and the low level control signal VSC2 and the bulk voltage VB are the ground voltage VSS. Meanwhile, the word line switching unit 412 enabled by the read enable signal CVTRDEN outputs the internal voltage VDD to the gate of the flash memory cell FC1. At this time, the internal voltage VDD is 4V. In this state, when the first enable signal EN1 is enabled at a high level, the first bit line switching unit 413 is enabled to supply the read voltage CVTRD to the drain of the flash memory cell FC1. . At this time, the read voltage CVTRD is approximately 0.8V. Accordingly, the internal voltage VDD of approximately 4 V is applied to the gate of the flash memory cell FC1, the NMOS transistor N1 is turned on to apply the ground voltage VSS to the source, and the ground voltage V is applied to the bulk. VSS) is applied, and a drain voltage VD1 of 0.8V is applied to the drain. Thus, a read operation to the flash memory cell FC1 is performed. The cell FC1 current read in this way is output through the first bit line switching unit 413.

The trimming operation (ie, program and read operation) for the flash memory cell FC1 is repeatedly performed until the threshold voltage of the flash memory cell FC1 is equal to the set threshold voltage.

Finally, a program operation of the flash memory cell FC3 for securing a program verification sensing margin in the program verify mode will be described. The program operation of the flash memory cell FC3 is performed in the same manner as the program operation of the flash memory cell FC1 described above. However, there is a difference in programming the threshold voltage of the programmed flash memory cell FC3 to be higher than the threshold voltage of the flash memory cell FC1. In order to generate such a difference in threshold voltage, the sizes of the drain voltages VD1 and VD3 may be set differently. That is, the drain voltage VD3 is set higher than the drain voltage VD1. Of course, the drain voltage VD3 is determined by the read voltage CVTRD supplied from the outside.

First, when the read enable signal CVTRDEN is enabled, the erase switching unit 411 outputs a high level control signal VSC1 and a low level control signal VSC2 and a bulk voltage VB. The word line switching unit 412 outputs the gate voltage VG of the positive high voltage VPPI by the program enable signal PGMEN. In this state, when the third enable signal EN3 is enabled, the third bit line switching unit 415 outputs the drain voltage VD3 having approximately 6V to 7V. At this time, the drain voltage VD3 is provided from the read voltage CVTRD. Accordingly, a positive high voltage VPPI of about 9 V is applied to the gate of the flash memory cell FC3, the NMOS transistor N3 is turned on to apply a ground voltage VSS to the source, and a ground voltage (VSS) to the bulk. VSS) is applied, and a drain voltage VD3 of 6V to 7V is applied to the drain. Therefore, the flash memory cell FC3 is programmed to raise the threshold voltage higher than the threshold voltage of the erase state.

The trimming operation is performed on the flash memory cell FC3 programmed as described above using the third bit line switching unit 415. First, the trimming operation is an operation of repeatedly performing a program operation and a read operation until the threshold voltage is set after programming the flash memory cell FC3. For example, when the read enable signal CVTRDEN is enabled at a high level to read the programmed current of the flash memory cell FC3, the erase switching unit 411 outputs a high level control signal VSC1. The low level control signal VSC2 and the bulk voltage VB are output. At this time, the high level control signal VSC1 is the internal voltage VDD, and the low level control signal VSC2 and the bulk voltage VB are the ground voltage VSS. Meanwhile, the word line switching unit 412 enabled by the read enable signal CVTRDEN outputs the internal voltage VDD to the gate of the flash memory cell FC3. At this time, the internal voltage VDD is 4V. In this state, when the third enable signal EN3 is enabled at the high level, the third bit line switching unit 415 is enabled to supply the read voltage CVTRD to the drain of the flash memory cell FC3. . At this time, the read voltage CVTRD is approximately 0.8V. Accordingly, the internal voltage VDD of approximately 4V is applied to the gate of the flash memory cell FC3, the NMOS transistor N3 is turned on to apply the ground voltage VSS to the source, and the ground voltage V is applied to the bulk. VSS) is applied, and a drain voltage VD1 of 0.8V is applied to the drain. Therefore, a read operation to the flash memory cell FC3 is performed. The read flash memory cell FC3 current is output through the third bit line switching unit 415.

The trimming operation (ie, program and read operation) for the flash memory cell FC3 is repeatedly performed until the threshold voltage of the flash memory cell FC3 is equal to the set threshold voltage.

Hereinafter, the threshold voltages of the flash memory cells FC1 to FC3 constituting the pull-up driver 42 are set through the erase and program operations and the trimming operation as described above. The sensing operation of the memory cell using the pull-up driver 42 configured as described above will be described.

First, when all threshold voltages of the flash memory cells FC1 to FC3 are set, the flash memory cell read enable signal CVTRDEN and the erase enable signal EREN are disabled at a low level to erase the switching unit. 411 outputs low-level control signals VSC1 and VSC2 and bulk voltage VB. Accordingly, the PMOS transistors P1 to P3 are all turned on. In this case, the word line switching unit 412 outputs the internal voltage VDD. In this state, when both of the first and third enable signals EN1 to EN3 are disabled, the first to third bit line switching units 413 to 415 are all connected to the drain terminals of the flash memory cells FC1 to FC3. Is blocked.

In this state, when entering the read mode, the read enable bar signal RDENB is input to the gate of the PMOS transistor P4 of the switching section 43 at a low level. Accordingly, the PMOS transistor P4 is turned on so that the current of the flash memory cell FC1 of the pull-up driver 22 is transmitted to the output terminal of the sensing unit 44 through the PMOS transistor P4 to drive the output terminal. do. In this state, the sense amplifier enable signal SAEN is enabled at a high level to be input to the gate of the NMOS transistor N6 of the sensing unit 44, and the sense amplifier enable bar signal SAENB is input to the inverter INV1. When inverted through and input to the gates of the PMOS transistor P7 and the NMOS transistor N4 at a high level, respectively, the NMOS transistors N4 and N6 are turned on, and the PMOS transistor P7 is turned off to the bit line. A current path is formed between the BL and the output terminal of the sensing unit 44. That is, a current path is formed between the bit line BL and the pull-up flash memory cell FC1.

In this state, when the memory cell MC is in a program state, current provided through the pull-up flash memory cell FC1 is not introduced into the ground terminal through the memory cell MC, and the output terminal of the sensing unit 44 is not present. Drive to a high level. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 45 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current provided through the flash memory cell FC1 flows to the ground terminal via the PMOS transistor P4, the NMOS transistors N4 and N6, and the memory cell MC. do. Accordingly, the output terminal of the sensing unit 44 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

In the erase verify mode, the erase verify enable bar signal EVENB is input to the gate of the PMOS transistor P5 of the switching unit 43 at a low level. Accordingly, the PMOS transistor P5 is turned on and the current supplied through the pull-up flash memory cell FC2 is supplied to the output terminal of the sensing unit 44. In this state, the sense amplifier enable signal SAEN is input to the gate of the NMOS transistor N6 at a high level, and the sense amplifier enable bar signal SAENB is inverted through the inverter INV1 and the PMOS transistor ( When input to the gates of P7 and NMOS transistor N4, respectively, the NMOS transistors N4 and N6 are turned on, and the PMOS transistor P7 is turned off to turn on the bit line BL and the pull-up flash memory cell. A current path is formed between FC2.

In this state, when the memory cell MC is in the program state, the current supplied through the pull-up flash memory cell FC2 does not flow into the ground terminal through the memory cell MC, but is output from the sensing unit 44. Drive to a high level. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 45 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current supplied through the flash memory cell FC2 flows to the ground terminal via the PMOS transistor P5, the NMOS transistors N4 and N6, and the memory cell MC. do. Accordingly, the output terminal of the sensing unit 44 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

Finally, in the program verify mode, the program verify enable bar signal PVENB is input to the gate of the PMOS transistor P6 of the switching unit 43 at a low level. Accordingly, the PMOS transistor P6 is turned on and the current supplied through the pull-up flash memory cell FC3 is supplied to the output terminal of the sensing unit 44. In this state, the sense amplifier enable signal SAEN is input to the gate of the NMOS transistor N6 at a high level, and the sense amplifier enable bar signal SAENB is inverted through the inverter INV1 and the PMOS transistor ( When input to the gates of P7 and NMOS transistor N4, respectively, the NMOS transistors N4 and N6 are turned on, and the PMOS transistor P7 is turned off to turn on the bit line BL and the pull-up flash memory cell. A current path is formed between the FC3s.

In this state, when the memory cell MC is in the program state, the current supplied to the pull-up flash memory cell FC3 does not flow into the ground terminal through the memory cell MC, and the output terminal of the sensing unit 44 is closed. Pull-up driving to a high level. The voltage pulled up to the high level is inverted to the low level through the inverter INV2 of the output driver 45 and output. As a result, when the memory cell MC is a program cell, the output signal SAOUT becomes low. Meanwhile, when the memory cell MC is in an erased state, current provided through the flash memory cell FC3 flows to the ground terminal via the PMOS transistor P6, the NMOS transistors N4 and N6, and the memory cell MC. do. Accordingly, the output terminal of the sensing unit 44 is maintained at a low level. The voltage at the output terminal having the low level is output inverted to the high level through the inverter INV2. As a result, when the memory cell MC is an erase cell, the output signal SAOUT is output at a high level.

On the other hand, the above-described pull-up driver 42 is described only for the embodiment of the configuration of the flash memory cell, this is an example, all non-volatile memory cells capable of program and erase operation is applicable.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a pull-up driver may be implemented using a flash memory cell capable of adjusting a threshold voltage through a program and erase operation, and thus, the chip may be applied to all chips regardless of process (eg, manufacturing) changes. The same sensing margin can be secured. This allows a sense amplifier to have a consistent operating characteristic that is not affected by the process.

Claims (27)

A sensing unit configured to sense data from the main memory cell during read, program verify, and erase verify; Comprising a plurality of pull-up memory cells having different threshold voltages through a program operation and an erase operation to ensure different sensing margins in the read, the program verification and the erase verification, pull-up the output terminal of the sensing unit A pull-up driver for driving; A program and erase operation controller configured to perform program and erase operations on the pull-up memory cells; A switching unit configured to provide the pull-up memory cell current to the output terminal of the sensing unit during pull-up driving of the output unit of the sensing unit during the read, the program verify, and the erase verify; And An output driver configured to output an output signal of the sensing unit of the pull-up driver; Sense amplifier comprising a. The method of claim 1, wherein the program and erase operation control unit, Outputting first and second source control signals for controlling supply of a source voltage supplied to a source of the pull-up memory cell according to a first read enable signal and an erase enable signal of the pull-up memory cell; An erase switching unit supplying a bulk voltage to the bulk of the pull-up memory cell; A source voltage switching unit configured to supply the source voltage to a source of the pull-up memory cell by operating according to first and second source control signals; A word line switching unit configured to supply a gate voltage to a gate of the pull-up memory cell according to the first read enable signal and the erase enable signal; And A bit line switching unit configured to supply a drain voltage to a drain of a pull-up memory cell according to the erase enable signal; Sense amplifier comprising a. The method according to claim 1 or 2, The pull-up memory cell is a sense amplifier consisting of a nonvolatile memory cell. The method of claim 3, wherein And the nonvolatile memory cell is programmed by channel hot electron injection and erased by F-N tunneling. The method of claim 4, wherein And the nonvolatile memory cell is a flash memory cell. The method according to claim 1 or 2, The pull-up memory cell includes three, one of three is an erase cell, the other is a first program cell programmed to have a higher threshold voltage than the erase cell, and the other is higher than the first program cell. A sense amplifier, which is a second program cell programmed to have a threshold voltage. The method of claim 2, When the pull-up memory cell is erased, the erase switching unit is enabled by the erase enable signal to output the first source control signal at a low level, and output the second source control signal at a high level. A sense amplifier that outputs a bulk voltage at a positive high voltage. The method of claim 7, wherein During the pull-up memory cell erase trimming, the erase switch is enabled by the first read enable signal to output the first and second source control signals to a high level, and to output the bulk voltage to a low level. Sense amplifier. The method of claim 8, And the word line switching unit is enabled by the source enable signal to output a negative high voltage to the gate of the pull-up memory cell when the pull-up memory cell is erased. The method of claim 9, And the word line switching unit is enabled by the first read enable signal and supplies an internal voltage to a gate of the pull-up memory cell during trimming of the pull-up memory cell. The method of claim 8, And the bit line switching unit is disabled to float the drain of the pull-up memory cell when the pull-up memory cell is erased. The method of claim 11, And the bit line switching unit supplies a read voltage to the drain of the pull-up memory cell during trimming of the pull-up memory cell. The method of claim 8, And the source voltage switching unit plots a source of the pull-up memory cell according to the first and second source control signals when the pull-up memory cell is erased. The method of claim 13, And a source voltage switching unit to supply a low level source voltage to a source of the pull-up memory cell according to the first and second control signals when trimming the pull-up memory cell. The method of claim 2, When the pull-up memory cell is programmed, the erase switching unit is enabled by the first read enable signal to output the first source control signal to a high level, and to output the second source control signal to a low level. And a sense amplifier for outputting the bulk voltage at a low level. The method of claim 15, When trimming the pull-up memory cell program, the erase switching unit is enabled by the first read enable signal to output the first and second source control signals to a high level and to output the bulk voltage to a low level. Sense amplifier. The method of claim 8, And the word line switching unit is enabled by a program enable signal to output a positive high voltage to a gate of the pull-up memory cell when the pull-up memory cell is programmed. The method of claim 17, And the word line switching unit is enabled by the first read enable signal to supply an internal voltage to a gate of the pull-up memory cell when the pull-up memory cell program is trimmed. The method of claim 8, And the bit line switching unit is enabled by an enable signal to supply an internal voltage to the drain of the pull-up memory cell when the pull-up memory cell is programmed. The method of claim 19, And the bit line switching unit supplies a read voltage to the drain of the pull-up memory cell when trimming the pull-up memory cell program. The method of claim 8, And a source voltage switching unit to supply a low level to a source of the pull-up memory cell according to the first and second source control signals when the pull-up memory cell is programmed. The method of claim 21, And a source voltage switching unit to supply a low level source voltage to a source of the pull-up memory cell according to the first and second control signals when trimming the pull-up memory cell program. The method of claim 2, The bit line switching unit is configured as many as the number of the pull-up memory cells and is connected one-to-one with the drain of the pull-up memory cell, and supplies drain voltage to each drain of the pull-up memory cell according to an enable signal. And a sense amplifier for reading a current from the drain. The method of claim 23, And a threshold voltage of the full-op memory cell determined by the drain voltage supplied from the bit line switching unit during a program operation. The method according to claim 1 or 2, The sensing unit outputs a high level output signal when the main memory cell is in a program state, and outputs a low level output signal when the memory memory cell is in an erased state. The method according to claim 1 or 2, The switching unit is enabled by the bar signal of the second read enable signal of the main memory cell, the bar signal of the erase verify enable signal, and the bar signal of the program enable signal during the read, the program verify, and the erase verify, respectively. And a sense amplifier for pull-up driving the output terminal of the sensing unit. The method according to claim 1 or 2, The output driver is a sense amplifier for outputting by inverting the output signal of the sensing unit.

Images