KR100562635B1 - Semiconductor memory device for high speed operation - Google Patents

Abstract

The present invention generates a sioeq signal for equalizing the SIO line in the main hole to reduce the load seen by the sioeq signal, so that the sioeq signal for equalizing the SIO line reaches the power supply voltage VDD level for a short time. The semiconductor memory device provides a semiconductor memory device capable of rising to allow sufficient equalization even in a short time.

Semiconductor Memory Device, SIO Line, Equalize, Main Hole

Description

Semiconductor memory device for high speed operation             

1 is a diagram showing a configuration of a memory device according to the prior art for SIO line equalization.

2 is a diagram illustrating a configuration of a memory device according to an embodiment of the present invention for SIO line equalization.

3 is a simulation waveform diagram showing that the SIO line equalizing signal (sioeq) according to the configuration of the present invention rises rapidly to the VDD level as compared to the prior art.

4 is a diagram illustrating a configuration of a memory device according to another exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: cell array block 220: SIO line equalizing unit

230: column decoder 240A, 240B, 240C: equalized signal generator

250: NAND gate 260: dummy buffer

400: bank control circuit part 500: XY cross circuit part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, the signal for equalizing a segment I / O line (hereinafter, “SIO, / SIO”) is rapidly raised to a supply power supply voltage (VDD) level. The present invention relates to a semiconductor memory device capable of high speed operation.

As is well known, as the performance of the system is improved, the operating speed of memory devices such as DRAM is also increasing to satisfy the performance. In order to operate the memory in synchronization with a high frequency clock, the column operation is also increased according to the speed. Should be. In order to speed up the column operation, the output signal of the column decoder and the high speed operation of the local data bus may be preceded in the memory cell array.

1 illustrates a configuration of a memory device according to the prior art for SIO line equalization, in which a memory device includes a plurality of memory banks that can be independently accessed, and FIG. 1 shows a configuration corresponding to one bank. .

Referring to FIG. 1, a plurality of cell array blocks 110, which are blocks in which a plurality of memory cells are matrix arrayed, are arranged in a matrix in the X and Y directions to form a bank. An equalization unit 120 composed of NMOS transistors for equalizing a pair of SIO lines (SIO, / SIO) to Vblp level in an area between cell array blocks of neighboring columns (hereinafter, referred to as a "subhole"). ) Is placed. When 16 unit cell array blocks 110 are arranged in one column, 17 equalizers 17 are arranged in a column direction in a subhole.

The bank control circuit unit 200 includes a plurality of column decoders 130 for outputting column signals yi and a plurality of SIO equalization signal generation units 140 (hereinafter, referred to as “sioeq generation units”) at the bottom of the bank. ) Is placed. The column decoder 130 and the sioeq generator 140 are disposed corresponding to each column, and one column decoder 130 is configured to correspond to 15 cell array blocks on the same column, and one sioeq generator ( 140 is configured to correspond to the 17 equalizing parts 120 formed in the servable hole.

In the right end of the bank, that is, an area between adjacent banks on the X axis (hereinafter referred to as a “main hole”) exists, and the lower right corner area (XY cross area) of the bank receives a signal (signal_A) which is the source of column operation. An XY cross circuit unit 300 having a buffer for buffering and outputting a signal signal_B is disposed. The signal signal_B is input to the bank control circuit unit 200 to finally control the column decoder 130 and the sioeq generator 140.

In operation, when the column signal yi is generated, the data of the bit line of the selected memory cell is transferred to the SIO line, and is transferred to the local data line (hereinafter, "LIO, / LIO") through the switching transistor. The data is read by the amplifier.

At this time, the SIO line should be equalized to the Vblp value in order to continuously operate another column signal. To this end, there is an equalization circuit unit 120 of the SIO line, and there is a sioeq generator 140 for generating an equalized signal. The arrangement structure is as described above.

In particular, the sioeq signal line which transfers the sioeq signal for equalizing the SIO line is extended from the bottom of the bank in the same direction as the column signal yi line.

However, when the length of the LIO line and the SIO line increases and the operating speed increases, the sioeq signal for equalizing the SIO line becomes inactive because the resistance and capacitance of the line (metal wiring) do not reach the supply voltage VDD and are deactivated. There is a problem that the line cannot be equalized, so that when reading continuous data, the LIO line does not reach the voltage enough for the input / output sense amplifier to operate.

The present invention has been proposed to solve the problems of the prior art as described above, by generating a sioeq signal to equalize the SIO line in the main hole to reduce the load (sioeq signal) viewed, SIO line It is an object of the present invention to provide a semiconductor memory device in which a sioeq signal for equalizing a signal is allowed to rise to a power supply voltage VDD level for a short time, so that the SIO line has sufficient equalization even for a short time.

According to an aspect of the present invention, there is provided a bank including cell array blocks arranged in a matrix and including an SIO line equalizing unit disposed in an area between the cell array blocks of a neighboring column; A bank control circuit unit disposed at a lower end of the bank and including a plurality of column decoders; An equalization signal generator arranged at a right end of the bank (main hole) to control the equalizer; And a plurality of equalized signal lines extending in the X-axis direction from the equalized signal generation means to the equalized portion.

In the present invention, the equalized signal line may be connected to an equalizing unit existing on the same low pass, and the plurality of equalized signal lines may be divided into a plurality of groups so as to have one equalized signal generation unit per divided group. can do.

In addition, in the present invention, the output of the equalization signal generation unit is controlled by a cell array block selection signal so as to be mounted on the equalization signal line, so that the sioeq signal is activated only in an active cell array block (block in which the word line is active). Can be.

In addition, in order to design the loads of the equalized signal generators equally, a dummy buffer may be connected to the output terminal of the equalized signal generator, and the skew of each signal output from the plurality of equalized signal generators may be adjusted. In order to suppress it, it is preferable to arrange the equalized signal generator at regular intervals.

In the present invention, the bank control circuit portion has a column decoder for outputting a column signal (yi), wherein the column signal line crosses the plane signal perpendicularly to the equalization signal line, and equalizes with the column signal (yi). The equalization signal generation unit may include a timing adjustment circuit to adjust timing between rise signals.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

Figure 2 shows the configuration of a memory device according to an embodiment of the present invention for SIO line equalization, the sioeq generation unit 240A, 240B, 240C is located in the main hole, the sioeq generation unit 240A, 240B , Sioeq signal transmitted to the equalizing unit 220 formed in each sub-hole from 240C) is transmitted through the sioeq signal line formed extending in the X-axis direction.

Specifically, the memory device includes a plurality of memory banks that can be independently accessed, and FIG. 2 shows a configuration corresponding to one bank.

Referring to FIG. 2, a plurality of cell array blocks 210 are arranged in a matrix in the X and Y directions, and a pair of SIO lines SIO and / SIO are formed in a subhole that is an area between cell array blocks of neighboring columns. An equalizing unit 220 composed of NMOS transistors for equalizing to the Vblp level (VDD / 2 level) is disposed. When 16 cell array blocks 210 are arranged in one column, 17 equalizing units 220 are arranged in a column direction in a subhole.

A bank control circuit unit 400 including a plurality of column decoders 230 for outputting column signals yi is disposed at a lower end of the bank. As the column decoder 230 is disposed corresponding to each column, one column decoder 230 drives a plurality of cell array blocks on the same column.

The sioeq generators 240A, 240B, and 240C are disposed in the main hole, which is an area between the banks adjacent to each other on the right end of the bank, that is, the X axis. One sioeq generator 240A drives the equalizer 220 corresponding to the plurality of low passes. Among the 17 low passes, the equalizer on the first to fifth low passes is the sioeq generator 240A. The equalization part on the sixth to twelfth low pass is driven through the sioeq generating part 240B, and the equalizing part on the thirteenth to seventeenth low pass is driven through the sioeq generating part 240A.

The reason for arranging the sioeq generators 240A, 240B and 240C at regular intervals is to minimize skew between the sioeq signals (signal_C, signal_D, signal_E) output from the respective sioeq generators 240A, 240B and 240C. . The buffer 260 is for a dummy for equally designing the load of each sioeq generator.

In the lower right corner region (XY cross region) of the bank, an XY cross circuit unit 500 having a buffer for buffering the signal signal_A which is the source of the column operation and outputting the signal signal_B is disposed. The signal signal_B is input to the bank control circuit unit 200 to finally control the column decoder 230, and is also applied to the sioeq generating units 240A, 240B, and 240C in the main hole to control it.

Meanwhile, in order to adjust the timing between the column signal yi and the sioeq signal, the sioeq generators 240A, 240B, and 240C have timing control circuits such as delay circuits.

In addition, the sioeq signal is controlled by the cell array block selection signal block_sel so that the sioeq signal is activated only in the active cell array block (block in which the word line is active) and is loaded on the sioeq signal line on each low pass. The NAND gate 250 is configured for this purpose.

3 is a voltage-time waveform diagram of a sioeq signal according to the prior art and the present invention, which is simulated at a power supply voltage VDD 2.5.

Referring to FIG. 3, it can be seen that the sioeq signal rises to the VDD level within a short time. As a result, the present invention generates a sioeq signal for equalizing the SIO line in the main hole to reduce the load seen by the sioeq signal, so that the sioeq signal for equalizing the IO line is supplied with a power supply voltage VDD for a short time. You are going to rise to the level.

4 is a block diagram illustrating a memory device according to another embodiment of the present invention, which is configured in the same manner as in FIG. 2, and the sioeq generation unit is disposed not only on the right main hole but also on the left end of the cell array block 420. In addition, the right sioeq generation unit 440a may drive the right blocks 420A among the cell array blocks, and the left sioeq generation unit 440b may drive only the left blocks 420B in the cell array blocks. .

This is to reduce the loading of the sioeq signal when the size of the chip increases, so that the sioeq signal is full swing in a short time. Skew for each sioeq signal output from the right sioeq generator 440a and the left sioeq generator 440b can be controlled by placing a delay adjustment circuit in the left and right sioeq generators.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention reduces the load of the sioeq signal so that the sioeq signal applied to the equalizing part of the SIO line can rise to the power supply voltage VDD level for a short time so that the SIO line can be sufficiently equalized even in a short time. do.

As a result, when the LIO line is sufficiently reached to the voltage for operating the input / output sense amplifier when reading continuous data, the operation speed of the memory device is improved.

Claims (14)

A bank including an SIO line equalizing unit (220) in which cell array blocks (210) are arranged in a matrix and disposed in an area between the cell array blocks of a neighboring column; A bank control circuit unit 400 disposed at a lower end of the bank and including a plurality of column decoders; An equalization signal generator 240A, 240B, 240C disposed at the right end of the bank to control the equalization unit; And A plurality of equalized signal lines extending in an X-axis direction from the equalized signal generator to the equalized part; Semiconductor memory device comprising a. The method of claim 1, And a buffering means arranged at a lower right corner of the bank to output a signal, which is a source of column operation, to the equalization signal generator. The method according to claim 1 or 2, The equalization signal line, And a common connection to equalizing parts existing on the same low pass. The method according to claim 1 or 2, And dividing the plurality of equalized signal lines into a plurality of groups and providing one equalized signal generator for each divided group. The method of claim 4, wherein And the output of the equalization signal generator is controlled by a cell array block selection signal and mounted on the equalization signal line. The method of claim 5, And an NAND gate having an output terminal of the equalization signal generation unit and the cell array block selection signal and having its output terminal connected to the equalization signal line. The method of claim 6, And a dummy buffer connected to an output terminal of any one of the equalized signal generators in order to design the loads of the equalized signal generators identically. The method of claim 4, wherein And the equalized signal generators are arranged at regular intervals to suppress skew of each signal output from the plurality of equalized signal generators. The method of claim 1, And the bank control circuit portion comprises a column decoder for outputting a column signal (yi), wherein the column signal line perpendicularly intersects the equalization signal line. The method of claim 9, And the equalizing signal generator comprises a timing adjusting circuit to adjust the timing between the column signal (yi) and the equalizing signal. A bank including cell array blocks (SIO line equalizing units) arranged in a matrix and arranged in an area between the cell array blocks of a neighboring column; A bank control circuit unit disposed at a lower end of the bank and including a plurality of column decoders; A first equalized signal generator 440a disposed at a right end of the bank to control the equalizer corresponding to the cell array blocks 420A of the right region of the bank; A second equalized signal generator 440b disposed at a left end of the bank to control the equalizer corresponding to the cell array blocks 420B of the left region of the bank; And A plurality of equalized signal lines extending in an X-axis direction from the first and second equalized signal generators to the equalized part; Semiconductor memory device comprising a. The method of claim 11, And a buffering means arranged at a lower right corner of the bank to output a signal, which is a source of column operation, to the first and second equalized signal generators. The method of claim 12, And the first and second equalized signal generators include delay adjustment means to suppress skew between the equalized signals outputted from the first and second equalized signal generators. The method according to claim 1 or 11, wherein And the right end of the bank is a main hole.

Images