KR100562349B1 - Semiconductor device - Google Patents

Abstract

In order to reduce the size of the semiconductor device (high frequency power amplification module), a semiconductor chip 5 having a plurality of amplification means is mounted on one peripheral surface side of the wiring board 1, and the electrode of the semiconductor chip and the electrode of the wiring board are wired. A semiconductor device electrically connected to each other, wherein the substrate-side bonding electrode 2C to which the wire 7C that is potential-fixed at the reference potential is connected is more than the substrate-side output electrode 2B to which the output wire 7B is connected. It is arrange | positioned at the position far from one side 5X of (5). The substrate side input electrode 2A to which the input wire 7A is connected has a position where the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate side output electrode 2B, or the It arrange | positions farther from the one side 5X of the said semiconductor chip 5 than the board | substrate side bonding electrode 2C.

In addition, in a high frequency power amplifier module in which a semiconductor chip having multiple stages of amplification stage transistors is installed on a wiring board, an input bonding wire for connecting the bonding input electrode 102a corresponding to any one amplification stage transistor 102 and the wiring board 121 ( A first auxiliary line connecting the bonding portions of both ends of the 105, a bonding output electrode 103b and a wiring board 124 corresponding to the amplifying transistor 103 positioned next to this one amplifying transistor; The angle formed by the second auxiliary line connecting the bonding portions at both ends of the output bonding wires 108 to be connected is 72 to 180 degrees, and the gap between the bonding portions of the bonding input electrode 102a and the bonding output electrode 103b is used. By setting it to 0.3mm or more and less than 0.8mm, the high frequency characteristics of the power amplifier module can be improved and miniaturized.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

1 is a perspective view showing an appearance configuration of a high frequency power amplifier according to an embodiment (1) of the present invention;

2 is an equivalent circuit diagram of the high frequency power amplifier;

3 is a plan view of essential parts of a wiring board corresponding to a portion enclosed by a dashed line shown in FIG. 2;

4 is a yabusa perspective view of FIG.

5 is an enlarged plan view of the main part of FIG. 3;

6 is a sectional view showing the principal parts of a transistor formation region of a semiconductor chip incorporated in the high frequency power amplifier;

7 is a cross-sectional view of principal parts in an isolation region of the semiconductor chip;

8 is a plan view of principal parts of a wiring board of a high frequency power amplifier according to an embodiment (2) of the present invention;

9 is a plan view of essential parts of a wiring board of the high frequency power amplifier according to the embodiment (3) of the present invention;

Fig. 10 is a plan view of essential parts of a wiring board of a high frequency power amplifier according to embodiment (4) of the present invention.

11 is a plan view of principal parts of the two-stage power amplifier module of the embodiment (5) of the present invention;

Fig. 12 is an equivalent circuit diagram of a two stage power amplifier module of embodiment (5) of the present invention;

Fig. 13 is a plan view showing the external configuration of a two stage power amplifier module according to the embodiment (5) of the present invention;

14 is a perspective view of a main part of the two-stage power amplifier module of the embodiment (5) of the present invention;

15 is a view showing a relationship between the coupling coefficient and the bonding portion spacing between the input and output bonding wires of the present invention and the prior art;

FIG. 16 is a diagram showing the relationship between the coupling coefficient between the input and output bonding wires and the stability coefficient of the amplifier.

17 is a view showing a relationship between a coupling coefficient and an angle between input and output bonding wires examined by the present inventors;

18 is a plan view of principal parts of a three-stage power amplifier module according to the embodiment (6) of the present invention;

19 is a plan view of main parts of the three-stage power amplifier module of the embodiment (7) of the present invention;

20 is a plan view of principal parts of the two-stage power amplifier module of the embodiment (8) of the present invention;

21 is a plan view of a two stage power amplifier module of the prior art;

22 is a perspective view of a two stage power amplifier module of the prior art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and in particular to useful techniques applied to semiconductor devices in multistage amplifier circuit configurations.

As a semiconductor device, there is a high frequency power amplifier (high frequency power module) incorporated in a portable communication device such as a PDC (Personal Digital Cellular) type mobile phone and a cellular phone or a PHS (Personal Handyphon System) type mobile phone. This high frequency power amplifier has a multistage amplifier circuit structure in which a plurality of amplifiers are connected in multiple stages.

The high frequency power amplifier mounts a semiconductor chip having an amplification means on one peripheral surface on one peripheral surface side of a wiring board, and electrically connects an electrode formed on one peripheral surface of the semiconductor chip with an electrode formed on one peripheral surface of the wiring board with conductive wires. Doing. The amplifying means has, for example, a configuration in which each of the plurality of field effect transistors is electrically connected in parallel, and the gate terminal (input portion) of the amplifying means is electrically connected to a chip side input electrode formed on one surface of the semiconductor chip. The drain terminal (output section) of the amplifying means is electrically connected to the chip side output electrode formed on one circumferential surface of the semiconductor chip. The chip side input electrode is disposed on one side of the semiconductor chip, and the chip side output electrode is disposed on the other side opposite to the one side of the semiconductor chip. The source terminal of the amplifying means is electrically connected to the back electrode formed on the other surface (rear surface) facing the one peripheral surface of the semiconductor chip, and this back electrode is potential fixed at the reference potential. The chip-side input electrodes face each other with one side of the semiconductor chip, and are electrically connected to each other via a wire for input and a substrate-side input electrode formed on one surface of the wiring board, and the chip-side output electrodes face each other with the other side of the semiconductor chip. Thus, the substrate-side output electrode and the output wire formed on one peripheral surface of the wiring board are electrically connected.

In the high frequency power amplifier, attempts have been made to form a plurality of amplifying means in one semiconductor chip in order to reduce the size and cost. For example, in the case of forming two amplifying means in one semiconductor chip. Since the input and output of the amplifying means in the front stage and the amplifying means in the rear stage are reversed, when the input wire and the output wire are close to each other, there is a problem that the high frequency characteristics deteriorate due to mutual induction between the wires. This problem is particularly noticeable between the input wire of the front end and the output wire of the rear end having a large electric power difference.

Therefore, the technique of preventing the deterioration of the high frequency characteristic by mutual induction between wires is described, for example in Unexamined-Japanese-Patent No. 9-260412. This technique forms a chip side bonding electrode between a chip side input electrode and a chip side output electrode, and forms a board side bonding electrode between a board side input electrode and a board side output electrode, and this bonding electrode The electrical connection between the wires and the potential of the chip-side bonding electrode or the substrate-side bonding electrode are fixed to the reference level prevents deterioration of high frequency characteristics due to mutual induction between the input wire and the output wire. .

In addition, high-frequency power amplifier modules using transistors are key devices for mobile communication devices such as PDC (Personal Digital Cellular), GSM (Grobal System for Mobile communication), and the demand is increasing rapidly in recent years. . In addition, the specification is required to be small and inexpensive in addition to the high frequency characteristics of the mobile communication system.

One method of meeting this requirement is described in Patent Publication No. 2755250 (Japanese Patent Laid-Open No. 9-260412). As shown in the plan view of FIG. 21 and the perspective view of FIG. 22, the two transistors 2000 and 3000 are placed close to each other on one semiconductor chip 1000 to reduce the size and cost. In addition, the bonding input electrode 2000b of the ultra-short transistor 2000 and the bonding electrode 7000d of the wiring board are connected by an input bonding wire 9000d. The bonding output electrode 3000c of the second stage transistor 3000 and the bonding electrode 7000a of the wiring substrate 6000 are connected by an output bonding wire 9000a. The bonding electrode 10000a on the semiconductor chip 1000 and the bonding electrode 12000a of the wiring board 6000 are connected by a shield bonding wire 13000a. The shield bonding wire 13000a is provided between the input bonding wire 9000d and the output bonding wire 9000a, and at the same time, the bonding electrodes 10000a and 12000a at both ends thereof are the semiconductor chip 1000 and the wiring board, respectively. It is grounded at a high frequency through a via hole (not shown) formed in the via hole. By providing the shield bonding wire 13000a, the coupling due to mutual inductance between the input bonding wire 9000d and the output bonding wire 9000a is reduced, and the degradation of isolation between the high frequency input / output terminals can be improved. , High frequency characteristics are improved.

The problem of coupling due to mutual inductance between the input bonding wire 9000d and the output bonding wire 9000a is that the first and second transistors 2000 and 3000 are arranged in reverse with the positions of the input and output, so that both Resulting in proximity. This problem is particularly noticeable between the input bonding wire 9000d of the first stage transistor 2000 and the output bonding wire 9000a of the second stage transistor 3000. Compared to the high frequency signal output input to the first transistor 2000, the high frequency signal power output from the second transistor 3000 is 20 dB to 30 dB (100 to 1000 times), and the positive feedback from the output to the input is applied. By On the other hand, although the output bonding wire 9000c of the first stage transistor 2000 and the input bonding wire 9000b of the second stage transistor 3000 are close to each other, the ratio of the high frequency signal power flowing to both is less than 0 dB (1 times). It is small and does not cause a problem of deterioration of high frequency characteristics.

21 and 22, 2000a and 3000a are main body portions of transistors, 2000d and 3000d are source electrodes of transistors, 2000c are output electrodes for bonding the first stage transistor 2000, and 3000b are for bonding second transistors 3000, respectively. The input electrode, 4000 is a ground electrode, 7000b and 7000c are bonding electrodes of the wiring substrate 6000, 8000a and 8000d are lead electrodes, and 104 is a cavity.

However, the present inventors have found the following problems as a result of examining the above description.

The substrate side bonding electrode is disposed between the substrate side input electrode and the substrate side output electrode. That is, each of the board | substrate side input electrode, the board | substrate side bonding electrode, and the board | substrate side output electrode is arrange | positioned in line with one side of a semiconductor chip.

Since the substrate side electrode is generally formed by the screen printing method, the occupied area is larger than that of the chip side electrode formed by the photolithographic technique. In addition, through hole wiring is formed directly under the electrode on the substrate side to shorten the overall path. Since the area (outer size) of the through-hole wiring in the planar direction must be made somewhat large in order to achieve low resistance, the occupied area of the substrate-side electrode becomes large. In addition, since the processing accuracy of the through-holes is small, the area occupied by the substrate-side electrode is increased. Therefore, when each of the substrate-side input electrode, the substrate-side bonding electrode, and the substrate-side output electrode is disposed in a straight line along one side of the semiconductor chip, the electrode array length thereof becomes long, and the chip-side input electrode and the substrate side Since the input electrodes do not face each other, and the chip side output electrode and the substrate side output electrode do not face each other, the length of the input wire and the output wire becomes long. If the length of the input wire and the output wire is increased, the inductance increases and the high frequency characteristic deteriorates. Therefore, the distance between the front amplification means and the rear amplification means must be shortened to shorten the wire length. This increase is a factor that hinders the miniaturization of the high frequency power amplifier.

In addition, the effect of the above-mentioned shield bonding wire 13000a of the prior art is explained with reference to FIG. Fig. 15 shows the coupling coefficient (mutual inductance (unit: nH)) between the input and output bonding wires of the amplifier with respect to the spacing d of the bonding portions of two parallel input and output bonding wires having a length of 1 mm (close to real). . Here, the broken line showing the location of the coupling coefficient 0.12 indicates that the amplifier operates stably when the coupling coefficient is 0.12 or less. This value of 0.12 was obtained from Fig. 16 showing the relationship between the coupling coefficient and the stability coefficient of the amplifier. If the stability factor is greater than 1, the amplifier operates stably. Here, the spacing d of the bonding portions is defined as the distance between the centers of the bonding portions of the two nearest bonding wires.

As shown in Fig. 15, in the case of the prior art in which the shielding wire is provided, the coupling coefficient is smaller than that in the case of the prior art, which is indicated as "no measures" in the drawing, and the high frequency characteristics are high. This is improving. Moreover, the range of the space | interval d of the bonding part whose coupling coefficient is 0.12 or less becomes wider, and the freedom of design increases. Moreover, since the space | interval d of a bonding part can be made small to 0.55 mm, chip area can be made small, a module can be reduced, and cost can be reduced.

In reality, however, inductance caused by via holes is applied in series to both ends of the shield bonding wire 13000a, and thus, the conventional high frequency characteristic cannot be sufficiently improved.

It is an object of the present invention to provide a technique capable of miniaturizing a semiconductor device.

An object of the present invention is to provide a high frequency power amplifier module that can further improve the high frequency characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows.

A semiconductor chip having a planar quadrangular shape, a wiring board on which the semiconductor chip is mounted on one peripheral surface thereof, a first electrode formed on a first region of the peripheral surface of the semiconductor chip and disposed on one side of the semiconductor chip; First amplification means formed in a first region of one circumferential surface of the semiconductor chip and having an input portion electrically connected to the first electrode, and formed in a second region of the circumferential surface of the semiconductor chip, A second amplification means formed in the second electrode disposed in the second region of the circumferential surface of the semiconductor chip, the output unit being electrically connected to the second electrode, the first region and the first region of the circumferential surface of the semiconductor chip. A third electrode formed in a third region between the two regions, and a first electrode formed on one circumferential surface of the wiring substrate so as to face each other with one side of the semiconductor chip and electrically connected to the first electrode through a first wire; 4 A fifth electrode formed on one surface of the wiring board so as to face the pole and one side of the semiconductor chip and electrically connected to the second electrode through a second wire, and to face one side of the semiconductor chip. And a sixth electrode formed on one surface of the wiring board and electrically connected to the third electrode through a third wire which is fixed at a reference potential, wherein the sixth electrode is more than the fifth electrode. It is located at a position far from one side of the semiconductor chip. The fourth electrode is disposed at a position where the distance from one side of the semiconductor chip is substantially equal to the fifth electrode, or at a position farther from one side of the semiconductor chip than the sixth electrode.

According to the above means, the interval between the fourth electrode and the fifth electrode can be narrowed by the amount corresponding to the occupied area of the sixth electrode, so that the interval between the first region and the second region of the semiconductor chip is narrowed. can do. As a result, since the footprint of the semiconductor chip can be reduced, the semiconductor device can be miniaturized.

In addition, the above object is to provide a high-frequency power amplifier module in which a semiconductor chip is provided on a wiring board using a dielectric material as a base, the two or more amplifier stage transistors on the semiconductor chip, a bonding input electrode for inputting high-frequency power to these amplifier transistors; Bonding output electrodes for outputting high-frequency power from these amplifying transistors, and a bonding first electrode for bonding one of both ends of an input bonding wire for connecting a wiring input and a bonding input electrode corresponding to any one of the amplifying transistors. A second beam that connects the bonding lines (central portions) of both ends of the output bonding wires connecting the auxiliary line of the output electrode and the bonding output electrode corresponding to the amplifier stage transistor located next to the one amplifier stage transistor and the wiring board. Bonding input at the same time so that shipbuilding angle falls within the range of 72 ~ 180 ° The bonding portion of the pole gap and the bonding output electrode can be achieved by designing the high-frequency power amplifier module to fit within the range of 0.3mm to less than 0.8mm.

The above object can be achieved by designing a high frequency power amplifier module such that the stability coefficients of the two amplifier stage transistors are not less than 0.3 mm or more and less than 0.8 mm, and the stability coefficients of the two amplifier stage transistors are 1 or more.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a high frequency power amplifier (high frequency power module) incorporated in a portable communication device such as an automobile telephone or a mobile telephone.

(Embodiment 1)

FIG. 1 is a perspective view showing an external configuration of a high frequency power amplifier according to an embodiment (1) of the present invention, FIG. 2 is an equivalent circuit diagram of the high frequency power amplifier, and FIG. 3 is a part enclosed by a dashed line shown in FIG. 4 is a perspective view of the main part of FIG. 3, FIG. 5 is an enlarged plan view of the main part of FIG. 3, and FIG. 6 is a sectional view of the main part of the transistor forming region of the semiconductor chip incorporated in the high frequency power amplifier. 7 is a cross-sectional view illustrating main parts of an isolation region of the semiconductor chip.

As shown in FIG. 1, the high frequency power amplifier of this embodiment has a cap 8 superimposed on one peripheral surface of the plate-shaped wiring board 1, and has a flat spherical structure in appearance. The wiring board 1 is formed in a rectangular shape (a rectangular shape in this embodiment) in a plane, and is formed of a ceramic substrate having a multilayer wiring structure. The cap 8 is formed in a rectangular shape (in the present embodiment, a rectangular shape) and formed of a conductive metal material. Since the cap 8 has a shielding effect, it is potential fixed at a reference potential (for example, 0 [V]).

As shown in Fig. 2, the high frequency power amplifier is composed of a multistage amplifier circuit. This multi-stage amplifying circuit mainly consists of capacitor elements C1 to C11, resistance elements R1 to R4, microstrip lines STL1 to STL3, amplifying means PW1 to amplifying means PW3, and the like.

Each of the amplifying means PW1, PW2, PW3 has a structure in which each of the plurality of field effect transistors is electrically connected in parallel. The amplifying means PW1 is formed with a total length of a gate of about 4000 [µm], the amplifying means PW2 is formed with a total length of a gate of about 3200 [µm], and the amplifying means PW3 has a total length of a gate of about 8000 [µm]. ] Is formed about.

The gate terminal (input section) of the amplifying means PW1 is electrically connected to the input external terminal P _in to which high frequency power (for example, 1 [mW]) is applied, and the drain terminal (output of the amplifying means PW1). Section) is electrically connected to the gate terminal (input section) of the rear end amplifying means PW2 and one end side of the microstrip line STL1. The drain terminal (output section) of the amplifying means PW2 is electrically connected to the gate terminal (input section) of the amplifying means PW3 at the rear end and one end side of the microstrip line STL2. The drain terminal (output part) of the amplifying means PW3 is electrically connected to the output external terminal P _out .

Each source terminal of the amplifying means PW1, PW2, PW3 is electrically connected to an external terminal for reference potential which is fixed to the reference potential (for example, 0 [V]). The other end of each of the microstrip lines STL1, STL2, and STL3 is electrically connected to an external terminal V _DD for a power source potential to which a power source potential (for example, 3.5 [V]) is applied. In addition, an external terminal (V _G ) is electrically connected to each gate terminal of the amplifying means (PW1, PW2, PW3), and a contact voltage (APC signal, automatic power) for adjusting the output power is connected to the external terminal (V _G ). Control signal) is applied.

Each of the amplifying means PW1 and PW2 is formed in the semiconductor chip 5 shown in FIG. 3, and the amplifying means PW3 is formed in the semiconductor chip 5 and other semiconductor chips other than the figure. have. The semiconductor chip 5 is mounted in the concave portion 1A formed on one circumferential surface of the wiring board 1, and the other semiconductor chip is formed on the other circumferential surface of the one wiring surface 1. It is mounted inside. That is, the semiconductor chip in which the amplification means is formed is mounted on the one peripheral surface side of the wiring board 1. Each of the semiconductor chips 5 and the other semiconductor chips is formed in a rectangular shape (a rectangular shape in this embodiment). In addition, the following description is abbreviate | omitted about the other semiconductor chip in which the amplifying means PW3 was formed.

A conductive plate 1B is formed on the bottom surface of the concave portion 1A on which the semiconductor chip 5 is mounted, as shown in FIG. 4. The conductive plate 1B is electrically connected to the reference potential external terminal 4 formed on the other main surface (rear surface) opposite the one main surface of the wiring board 1 through the through hole wiring 3 formed directly below it. have. This reference potential external terminal 4 is potential fixed at 0 [V] potential, for example. In addition, the above-described input external terminal P _in , output external terminal P _out , power potential external terminal V _DD , and external terminal V _G are also formed on the back surface of the wiring board 1. have.

As shown in FIG. 5, the amplifying means PW1 is formed in the first region 5A of the main surface of the semiconductor chip 5. The gate terminal of the amplifying means PW1 is formed in the first region 5A of the one main surface of the semiconductor chip 5, and is disposed on one side 5X side (in this embodiment, one long side side) of the semiconductor chip 5. It is electrically connected with the chip | tip side input electrode 6A arrange | positioned. Further, the drain terminal of the amplifying means PW1 is formed in the first region 5A of the main surface of the semiconductor chip 5, and the other side 5Y side (which is opposite to one side 5X) of the semiconductor chip 5 ( In this embodiment, it is electrically connected with the chip | tip output electrode 6D arrange | positioned at the other long side side.

The amplifying means PW2 is formed in the second region 5B of the one main surface of the semiconductor chip 5. The drain terminal of the amplifying means PW2 is formed in the second region 5B on one circumferential surface of the semiconductor chip 5, and electrically connected to the chip-side output electrode 6B disposed on one side 5X side of the semiconductor chip 5. Is connected. In addition, the gate terminal of the amplifying means PW2 is formed in the second region 5B on one circumferential surface of the semiconductor chip 5, and the chip-side input electrode 6E is disposed on the other side 5Y side of the semiconductor chip 5. ) Is electrically connected.

Each of the source terminals of the amplifying means PW1 and PW2 will be described later in detail, but is electrically connected to the back electrode formed on the other main surface (rear surface) opposite to the main surface of the semiconductor chip 5.

A third region (isolation region) 5C is formed between the first region 5A and the second region 5B on one circumferential surface of the semiconductor chip 5 for electrically separating these regions. In the third region 5C, the chip side bonding electrode 6C disposed on one side 5X side of the semiconductor chip 5 and the chip side bonding electrode disposed on the other side 5Y side of the semiconductor chip 5 ( 6F) is formed.

The chip-side input electrode 6A faces each other 5X of the semiconductor chip 5 so as to face each other through the board-side input electrode 2A and the input wire 7A formed on one circumferential surface of the wiring board 1. It is electrically connected. 2 A of board | substrate side input electrodes are electrically connected with the input external terminal P _in formed in the back surface of the wiring board 1 through the through-hole wiring 3 and inner wiring which were formed directly under it.

The chip-side output electrode 6B is electrically connected via the output-side wire 7B and the substrate-side output electrode 2B formed on one peripheral surface of the wiring board 1 so as to face each other 5X of the semiconductor chip 5. It is. The substrate-side output electrode 2B is formed on one circumferential surface of the wiring board 1 so as to face each other with one side of the other semiconductor chip on which the amplifying means PW3 is formed through the through hole wiring 3 formed underneath and the internal wiring. It is electrically connected with the board | substrate input electrode.

The chip-side bonding electrode 6C is electrically connected to the one side 5X of the semiconductor chip 5 via the wire-side 7C and the board-side bonding electrode 2C formed on one circumferential surface of the wiring board 1. Connected. The substrate-side bonding electrode 2C is electrically connected to the reference potential external terminal 4 formed on the rear surface of the wiring board 1 through the through hole wiring 3 and the inner wiring formed thereunder. That is, the wire 7C is potential fixed at the reference potential.

The chip-side output electrode 6D is electrically connected to the other side 5Y of the semiconductor chip 5 via the substrate-side output electrode 2D and the output wire 7D formed on one circumferential surface of the wiring board 1. Connected. Through-hole wiring 3 is formed directly under the substrate-side output electrode 2D.

The chip-side input electrode 6E faces the other side 5Y of the semiconductor chip 5 so that the board-side input electrode 2E and the input wire 7E formed on one peripheral surface of the wiring board 1 face each other. It is electrically connected through. The substrate-side input electrode 2E is electrically connected to the substrate-side output electrode 2D through the through hole wiring 3 and the internal wiring.

The chip-side bonding electrode 6F faces the other side 5Y of the semiconductor chip 5 so as to be electrically connected to each other via the wire-side 7F and the substrate-side bonding electrode 2F formed on one circumferential surface of the wiring board 1. Is connected. The substrate-side bonding electrode 2F is electrically connected to the reference potential external terminal 4 formed on the rear surface of the wiring board 1 through the through-hole wiring 3 and the inner wiring formed thereunder. That is, the wire 7F is potential fixed at the reference potential.

The distance between the chip-side output electrode 6D and the other side 5Y of the semiconductor chip 5 is shorter than the distance between the chip-side input electrode 6A and the one side 5X of the semiconductor chip 5. The distance between the chip side output electrode 6B and one side 5X of the semiconductor chip 5 is shorter than the distance between the chip side input electrode 6E and the other side 5Y of the semiconductor chip 5. This shortens the length of the output wire and lowers the output resistance.

A source electrode 6S electrically connected to the source terminal of the amplifying means PW1 is formed in the first region 5A of the main surface of the semiconductor chip 5. This source electrode 6S is disposed on the one side 5X side of the semiconductor chip 5 rather than the chip side input electrode 6A. In addition, a source electrode 6S electrically connected to the source terminal of the amplifying means PW2 is disposed in the second region 5B of the main surface of the semiconductor chip 5. These source electrodes 6S are used for probe inspection.

In the high frequency power amplifier of the present embodiment, the input wire 7A is disposed close to the output wire 7B. The input wire 7A is electrically connected to the gate terminal (input section) of the amplification means PW1 at the front end, and the output wire 7B is electrically connected to the drain terminal (output part) of the amplification means PW2 at the rear end. Therefore, although the difference between the electric power flowing through the input wire 7A and the electric power flowing through the output wire 7B is large, the wire 7C which is potential-fixed at the reference potential is the input wire 7A and the output wire. Since it is arrange | positioned between 7B, deterioration of the high frequency characteristic by the mutual inductive action of the input wire 7A and the output wire 7B can be prevented.

Moreover, the output wire 7D is arrange | positioned near the input wire 7E. The output wire 7D is electrically connected to the drain terminal (output part) of the amplification means PW1 at the front end, and the input wire 7E is electrically connected to the gate terminal (input part) of the amplification means PW2 at the rear end. Since the power flowing through the output wire 7D and the power flowing through the input wire 7E are almost the same, the deterioration of the high frequency characteristics due to mutual induction between the wires is small, but the potential is fixed at the reference potential. Since 7F is disposed between the output wire 7D and the input wire 7E, it is possible to prevent deterioration of high frequency characteristics due to mutual induction action between the output wire 7D and the input wire 7E. .

The substrate side bonding electrode 2C is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate side output electrode 2B. 2 A of board | substrate side input electrodes are arrange | positioned in the position where the distance from one side 5X of the semiconductor chip 5 becomes substantially the same as the board | substrate side output electrode 2B. That is, the substrate-side bonding electrode 2C is not disposed between the substrate-side input electrode 2A and the substrate-side output electrode 2B, and the substrate-side input electrode 2A and the substrate-side output electrode ( It is arranged at a position farther from one side 5X of the semiconductor chip 5 than from 2B). Accordingly, the distance between the substrate-side input electrode 2A and the substrate-side output electrode 2B can be narrowed by the amount corresponding to the occupied area of the substrate-side bonding electrode 2C, and accordingly the semiconductor chip ( Since the interval between the first region 5A and the second region 5B in 5) can also be narrowed, the occupied area of the semiconductor chip 5 can be reduced.

The substrate side bonding electrode 2F is disposed at a position farther from the other side 5Y of the semiconductor chip 5 than the substrate side output electrode 2D. The substrate-side input electrode 2E is disposed at a position at which the distance from the other side 5Y of the semiconductor chip 5 is substantially the same as the substrate-side output electrode 2D. That is, the substrate-side bonding electrode 2F is not disposed between the substrate-side input electrode 2E and the substrate-side output electrode 2D, but the substrate-side input electrode 2E and the substrate-side output electrode ( It is arrange | positioned far from the other side 5Y of the semiconductor chip 5 rather than 2D). Therefore, the space | interval of the board | substrate side input electrode 2E and the board | substrate side output electrode 2D can be narrowed only by the thing corresponded to the occupation area of the board | substrate side bonding electrode 2F, and accordingly, the semiconductor chip 5 Since the distance between the first region 5A and the second region 5B of the () can be narrowed, the occupied area of the semiconductor chip 5 can be reduced.

As shown in FIG. 6, the semiconductor chip 5 includes a semiconductor substrate 10 in which a P ⁻ type epitaxial layer 10B is formed on one peripheral surface of a P ⁺ type semiconductor substrate 10A made of, for example, single crystal silicon. Is mainly composed of).

The field effect transistors constituting the amplifying means PW1 and PW2 are formed in the transistor formation region on one main surface of the semiconductor substrate 10. The field effect transistor is mainly composed of a P-type well region 12, a gate insulating film 14, a gate electrode 15, a source region and a drain region, a pair of n ⁻ type semiconductor regions 16 and a pair of n, which are channel formation regions. ^It consists of the ⁺ type semiconductor region 17.

The wiring 19A formed in the wiring layer of the first layer is electrically connected to the n ⁺ type semiconductor region 17 as the drain region through the connection hole formed in the interlayer insulating film 18. The wiring 19B formed in the wiring layer of the first layer is electrically connected to the n ⁺ type semiconductor region 17 as the source region through the connection hole formed in the interlayer insulating film 18. The wiring 19B is electrically connected to the p ⁺ type semiconductor region 13 formed in the p ⁻ type epitaxial layer 13 through the connection hole formed in the interlayer insulating film 18. The p ⁺ type semiconductor region 13 is electrically connected to the p ⁺ type semiconductor substrate 10A. Although not shown in detail in the drawing, the wiring 19C formed in the wiring layer of the first layer is electrically connected to the gate electrode 15 through the connection hole formed in the interlayer insulating film 18.

The wiring 21A formed in the wiring layer of the second layer is electrically connected to the wiring 19A through the connection hole formed in the interlayer insulating film 20. The chip side output electrode 6D and the chip side output electrode 6B are formed in a part of this wiring 21A. The wiring 21B formed in the wiring layer of the second layer is electrically connected to the wiring 19B through the connection hole formed in the interlayer insulating film 20. A part for pro-part inspection is formed in a part of this wiring 21B. Although not shown in the drawing, the wiring formed in the wiring layer of the second layer is electrically connected to the wiring 19C through the connection hole formed in the interlayer insulating film 20. A chip side input electrode 6A and a chip side input electrode 6E are formed in a part of this wiring.

As shown in FIG. 7 in the third region 5C of the semiconductor chip 5, the wiring 19D formed in the wiring layer of the first layer is formed on the field insulating film 11. The wiring 19D extends in the direction that goes straight to the one side 5X of the semiconductor chip 5. In the wiring 19D, the wiring 21D formed in the wiring layer of the second layer is formed through the connection hole formed in the interlayer insulating film 20. This wiring 21D is extended toward the direction which goes directly to one side 5X of the semiconductor chip 5 similarly to the wiring 19D. The chip side bonding electrodes 6C and 6F are formed in a part of this wiring 21D.

The back electrode 21 is formed on the other main surface (rear surface) facing the one main surface of the semiconductor substrate 10. The back electrode 21 is electrically and mechanically connected to the conductive plate 1B formed on the bottom surface of the recessed portion 1A of the wiring board 1 via a conductive adhesive. In other words, the source terminals of the amplifying means PW1 and PW2 are potential fixed at the reference potential.

In the high-frequency power amplifier of the present embodiment, a wiring in which the potential is fixed at the reference potential in the third region (isolation region) 5C between the first region 5A and the second region 5B of the semiconductor chip 5 ( 19D and the wiring 21D extend in the direction that goes straight to one side 5X of the semiconductor chip 5. In addition, in the third region 5C, the P ⁺ type semiconductor region 13, which is fixed at the reference potential, extends in a direction that is directly parallel to the one side 5X of the semiconductor chip 5, and the semiconductor substrate 10 is also referred to as a reference. The potential is fixed to the potential. Therefore, in the semiconductor chip 5, since the interference of magnetic flux is suppressed, the high frequency characteristic does not deteriorate.

Thus, according to this embodiment, the following effects can be acquired.

(1) The substrate side bonding electrode 2C is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate side input electrode 2A and the substrate side output electrode 2B, and the substrate side bonding is performed. The electrode 2F for substrate-side bonding is disposed at a position farther from the other side 5Y of the semiconductor chip 5 than the substrate-side input electrode 2E and the substrate-side output electrode 2D. The distance between the substrate-side input electrode 2A and the substrate-side output electrode 2B can be narrowed by the amount corresponding to the occupied area of (2C), and the area occupied by the substrate-side bonding electrode 2F is reduced. Since the distance between the board | substrate side input electrode 2E and the board | substrate side output electrode 2D can be narrowed by correspondence, the 1st area | region 5A and the 2nd area | region 5B of the semiconductor chip 5, It can narrow the interval of. As a result, since the occupied area of the semiconductor chip 5 can be reduced, miniaturization of the high frequency power amplifier can be achieved.

(2) The substrate-side input electrode 2A is disposed at a position where the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate-side output electrode 2B, and the substrate-side bonding electrode 2C is provided. ) Is disposed at a position farther from one side 5X of the semiconductor chip 5 than the substrate-side input electrode 2A and the substrate-side output electrode 2B, so that the wire 7C is potential-fixed at the reference potential. Intersects between the substrate-side input electrode 2A and the substrate-side output electrode 2B, so that the substrate-side bonding electrode is between the substrate-side input electrode 2A and the substrate-side output electrode 2B. The interference of the magnetic flux can be further suppressed as compared with the case where 2C is disposed.

In addition, in this embodiment, the example which arrange | positioned the wire 7C and the wire 7F which are electric potential fixed at the reference potential was demonstrated. Since the power flowing through the input wire 7E and the power flowing through the output wire 7D are almost the same, the output wire 7D connected to the drain terminal (output part) of the amplification means PW1 at the front end and the amplification means at the rear end are provided. It is not necessary to specifically arrange the wire which is fixed in the reference potential between the input wire 7E connected to the gate terminal (input portion) of (PW2). In this case, the chip side bonding electrode 6F and the substrate side bonding electrode 2F are unnecessary.

In addition, in this embodiment, the example which arrange | positioned the board | substrate side input electrode 2A in the position where the distance from the one side 5X of the semiconductor chip 5 becomes substantially the same as the board | substrate side output electrode 2B was demonstrated. 2 A of board | substrate side input electrodes may be arrange | positioned far from the one side 5X of the semiconductor chip 5 rather than 2 C of board | substrate side bonding electrodes. Also in this case, although the same effect as the above-mentioned embodiment can be obtained, since the length of the input wire 7A becomes long, a high frequency characteristic deteriorates slightly.

(Embodiment 2)

Fig. 8 is a plan view of main parts of a wiring board of the high frequency power amplifier according to the embodiment (2) of the present invention.

The high frequency power amplifier of this embodiment is basically the same as that of Embodiment 1 mentioned above, and the following structures are different.

That is, as shown in FIG. 8, the one end side of the wire 7G extending on the third region 5C of the semiconductor chip 5 is electrically and mechanically connected to the substrate side bonding electrode 2C. The other end side of the wire 7G is electrically and mechanically connected to the side bonding electrode 2F. Since the substrate-side bonding electrode 2C and the substrate-side bonding electrode 2F are electrically connected to the reference potential external terminal 4, the wire 7G is potential fixed at the reference potential.

In this manner, one end of the wire 7G is connected to the substrate-side bonding electrode 2C, and the other end side of the wire 7G is connected to the substrate-side bonding electrode 2F, thereby providing the input wire 7A. ) And the deterioration of the high frequency characteristic due to the mutual induction action of the output wire 7B and the mutual induction effect between the output wire 7D and the input wire 7E can be prevented.

(Embodiment 3)

Fig. 9 is a plan view of main parts of a wiring board of the high frequency power amplifier according to the embodiment (3) of the present invention.

The high frequency electrode amplifier of this embodiment is basically the same as that of Embodiment 1 mentioned above, and the following structures are different.

That is, as shown in FIG. 9, amplification means PW1, PW2, and PW3 are formed in one semiconductor chip 5. As shown in FIG. PW3 is formed in the fourth region 5D of one circumferential surface of the semiconductor chip 5.

The gate terminal (input section) of the amplifying means PW3 is formed in the fourth region 5D of the one main surface of the semiconductor chip 5, and is formed on one side 5X side of the semiconductor chip 5 (one long side in the present embodiment). It is electrically connected with the chip | tip side input electrode 6H arrange | positioned at the side). The drain terminal (output part) of the amplifying means PW3 is formed in the fourth region 5D of a part of the surface of the semiconductor chip 5, and has the other side opposite to one side 5X of the semiconductor chip 5 ( It is electrically connected with the chip | tip output electrode 6K arrange | positioned at the 5Y) side (other long side in this embodiment). The source terminal of the amplifying means PW3 is electrically connected to the back electrode 21 formed on the back surface of the semiconductor chip 5 in the same manner as the amplifying means PW1.

A fifth region (isolation region) 5E for electrically separating these regions is formed between the second region 5B and the fourth region 5D on one circumferential surface of the semiconductor chip 5.

The chip-side input electrode 6H faces each other 5X of the semiconductor chip 5 so as to face each other through the board-side input electrode 2H and the input wire 7H formed on one circumferential surface of the wiring board 1. It is electrically connected. The substrate-side input electrode 2H is electrically connected to the substrate-side output electrode 2B through the through-hole wiring 3 and the internal wiring formed just below it.

The chip-side output electrode 6K is electrically connected to the other side 5Y of the semiconductor chip 5 via the substrate-side output electrode 2K and the output wire 7K formed on one circumferential surface of the wiring board 1. Connected. The substrate-side output electrode 2K is electrically connected to an output external terminal formed on the rear surface of the wiring board 1 through the through-hole wiring 3 and the inner wiring formed thereunder.

On one circumferential surface of the wiring board 1, a substrate side bonding electrode 2J is formed so as to face each other 5X of the semiconductor chip 5, and faces the other side 5Y of the semiconductor chip 5. 2L of board | substrate side bonding electrodes are formed. The substrate side bonding electrodes 2J and 2L are electrically connected to the reference potential terminal 4 formed on the back surface of the wiring board 1 in the same manner as the substrate side bonding electrodes 2C.

The substrate-side bonding electrode 2J is disposed at a position at which the distance from one side 5X of the semiconductor chip 5 is substantially the same as the substrate-side bonding electrode 2C, and the substrate-side bonding electrode 2L is The distance from the other side 5Y of the semiconductor chip 5 is disposed at a position substantially equal to the substrate-side bonding electrode 2F.

One end side of the wire 7L extending on the fifth region 5E of the semiconductor chip 5 is electrically and mechanically connected to the substrate side bonding electrode 2J, and the substrate side bonding electrode 2L is connected to the substrate 2 bonding electrode 2J. The other end side of the wire 7L is electrically and mechanically connected to each other.

In the high frequency power amplifier of the present embodiment, two wires 7L are arranged. The difference between the power flowing through the input wire 7E and the power flowing through the output wire 7K is greater than the difference between the power flowing through the input wire 7A and the power flowing through the output wire 7B. . Therefore, as in the present embodiment, by increasing the number of wires that are fixed to the reference potential in accordance with the electric power difference, deterioration of high frequency characteristics due to mutual induction between the input wire and the output wire can be prevented in a more stable state. Can be.

(Embodiment 4)

Fig. 10 is a plan view of main parts of a wiring board of the high frequency power amplifier according to the embodiment (4) of the present invention.

The high frequency power amplifier of this embodiment is basically the same as that of Embodiment 1 mentioned above, and the following structures are different.

That is, as shown in FIG. 10, the board | substrate side output electrode 2B is arrange | positioned in the position which opposes each other 5X of the semiconductor chip 5, and the board | substrate side input electrode 2A of the semiconductor chip 5 It is arrange | positioned in the position which opposes the other side 5P which meets about one side 5X.

Thus, the board | substrate side output electrode 2B is arrange | positioned in the position which mutually faces the one side 5X of the semiconductor chip 5, and the board | substrate side input electrode 2A is placed on the one side 5X of the semiconductor chip 5, and so on. By arrange | positioning in the position which opposes the other edge | side 5P which meets with respect to each other, the magnetic flux of the input wire 7A and the output wire 7B becomes orthogonal, and the mutual induction effect between these wires can be suppressed. Can be.

In addition, since there is no need to provide a substrate-side bonding electrode for connecting the wires that are fixed at the reference potential, the distance between the first region 5A and the second region 5B of the semiconductor chip 5 can be narrowed. The area occupied by the semiconductor chip 5 can be reduced. As a result, miniaturization of the high frequency power amplifier can be achieved.

(Embodiment 5)

As shown in Fig. 15, in the case of the present invention, the coupling coefficient is smaller than in the case of the prior art, and the high frequency characteristics are improved. Moreover, the range of the space | interval d of the bonding part whose coupling coefficient is 0.12 or less (stable coefficient 1 or more) becomes wider further, and the freedom of design increases. In addition, since the distance d of the bonding portion can be reduced to 0.3 mm, the chip area can be further reduced, and the module size can be reduced and the cost can be reduced.

In addition, although FIG. 15 shows the case where the angle (phi) formed between input / output bonding wires is 90 degrees, as shown in FIG. 7, this angle (phi) should just be in the range of 72-180 degrees. Moreover, when the angle (phi) is 140 degrees, a coupling coefficient becomes minimum and it turns out that a minimum point exists.

In the specific design of the high frequency power amplifier module of the present invention, the bonding portion spacing d and the angle φ are selected on the basis of the above.

In addition, as apparent from the above description, the present invention is based on the fact that the angle? Is not set to 0 degrees as in the prior art. Therefore, the high frequency power amplifier module may be designed such that the angle φ is in the range of 72 to 180 degrees, and the stability coefficient of the two amplifying transistors corresponding to the input / output bonding wires is 1 or more.

The two-stage power amplifier module of Embodiment (5) of this invention is demonstrated with reference to FIGS. Fig. 11 is a plan view of a main part, Fig. 12 is an equivalent circuit diagram, Fig. 13 is a plan view showing an appearance configuration, and Fig. 14 is a major part perspective view.

As shown in Fig. 11, transistors 102 and 103 composed of MOSFETs of the first and second stages are formed in close proximity to one silicon chip 101. As shown in Figs. Flow direction of the high frequency signal from the gate electrode 102a of the first transistor 102 to the drain electrode 102b and flow direction of the high frequency signal from the gate electrode 103a of the second transistor 103 to the drain electrode 103b. These transistors are arranged so as to be reversed.

The gate electrode 102a, which is a high frequency input terminal, is connected to the end 121 of the input matching circuit 125 on the wiring board 113 by one input bonding wire 105. The drain electrode 103b, which is a high frequency output terminal, is connected to the end 124 of the output matching circuit 127 on the wiring board 113 by four output bonding wires 108. The gate electrode 102a is disposed along one side of the left side of the silicon chip 101, and the drain electrode 103b is disposed along one side of the upper side of the silicon chip 101. The angle formed between the input bonding wire 105 and the output bonding wire 108 is about 90 °. The bonding wires 106 and 107 are connected to both ends 122 and 123 of the inter-level matching circuit 126 on the wiring board 113 by connecting the drain electrode 102b and the gate electrode 103b, respectively. The distance d between the gate electrode 102a (bonding input electrode) of the first transistor 102 and the drain electrode 103b (output wire for bonding wire) of the second transistor 103 is approximately 0.6 mm. .

The silicon chip 101 is mounted in the cavity 104 formed in the wiring board 113. On the back surface of the silicon chip 101, a metal film is deposited as the source electrode of the first transistor 102 and the source electrode of the second transistor 103, and is connected to the ground potential through the wiring in the cavity 104. As a material of the wiring substrate 113, a dielectric substrate such as glass ceramic or alumina is used. Moreover, copper, silver, silver platinum, etc. are used for the wiring.

12 and 13, symbols P _in , P _out , V _gg , and V _dd are high frequency signal input terminals, high frequency signal output terminals, gate voltage application terminals, and drain voltage application terminals, respectively, which are external to the power amplifier module. Connection terminal. In FIG. 13, boundaries between regions of the input matching circuit 125, the end-to-end matching circuit 126, and the output matching circuit 127 are indicated by auxiliary lines. Incidentally, in Fig. 14, the three-dimensional shape of the vicinity of the cavity 104 is set to about 90 degrees between the input bonding wire 105 and the output bonding wire 108, but the angle is in the range of 72 to 180 degrees. You can choose from.

Embodiment 6

The three-stage power amplifier module of Embodiment (6) of the present invention will be described with reference to the principal plane view of FIG. Transistors 102, 103, and 114 composed of MOSFETs of the first stage, the second stage, and the output stage are formed in close proximity to one silicon chip 101. The flow direction of the high frequency signal from the gate electrode 102a of the first transistor 102 to the drain electrode 102b and the flow direction of the high frequency signal from the gate electrode 103a of the second transistor 103 to the drain electrode 103b These transistors are placed in reverse. The output terminal transistor 114 is arranged so that the direction of flowing the high frequency signal from the gate electrode 114a to the drain electrode 114b is opposite to that of the second transistor 103.

The difference from the embodiment (5) is that the angle between the input bonding wire 105 of the first stage transistor 102 and the output bonding wire 108 of the second stage transistor 103 is 140 °, and the output terminal transistor 114 is On the same chip, the angle formed between the output bonding wire 110 of this transistor and the input bonding wire 107 of the second transistor 103 is about 90 ° and the gate electrode 103a of the second transistor 103 ( The distance d of the bonding portion between the bonding input electrode) and the drain electrode 114b (bonding output electrode) of the output terminal transistor 114 is approximately 0.7 mm, and the present invention is also applied here.

According to this embodiment, as shown in Fig. 17, the coupling coefficient between the first and second stage input / output bonding wires can be minimized, and the isolation can be further improved. In addition, since the present invention is applied, sufficient isolation between the second stage and the input / output bonding wires of the output stage can be ensured. Therefore, even in the present embodiment in which three transistors are formed on the same chip due to the reduction of the semiconductor chip area, the high frequency characteristics can be improved despite the shortening of the distance between these transistors.

(Embodiment 7)

The three-stage power amplifier module of Embodiment (7) of the present invention will be described with reference to the main part plan view of FIG. The difference from the embodiment (6) is that the shield bonding wire 201 and the shield wiring 204 are provided between the second stage transistor 103 and the output terminal transistor 114 by applying a shielding technique, and both ends thereof are provided. It is at the point connected to the ground potential via the electrode 202 and via-hole 203 on a wiring board.

In the present embodiment, the conventional shielding technique is applied between the first stage and the second stage, but these transistor regions have a large original area and can improve high frequency characteristics.

Embodiment 8

The two-stage power amplifier module of Embodiment 8 of the present invention will be described with reference to the principal plane view of FIG.

The difference from the embodiment (5) lies in that the direction of the ultrashort transistor 102 itself is rotated by 90 degrees.

In this embodiment, since the position of the bonding section of the input / output bonding wire between the first and second stages can be moved to the center of the side of the chip, the bonding section spacing can be further increased (0.65 in Example (1) was 0.75 mm). Can further improve the isolation between the input and output.

As mentioned above, although this invention was demonstrated based on an Example, this invention is not limited to the said Example, The number of electrodes of a transistor, the number of bonding wires, etc. can be variously changed in the range which does not deviate from the well-known. In addition, the transistor is not limited to the MOSFET, and other field effect transistors, or a transistor such as a heterocoupled bipolar transistor (HBT), may be used.

According to the present invention, the high frequency characteristics of the high frequency power amplifier module can be further improved, and accordingly, the power amplifier module can be miniaturized, or the portable terminal using the same can be miniaturized and thinned.

Claims (35)

A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected to the input terminal of the first transistor, the output terminal of the amplifying circuit is connected to the output terminal of the second transistor, The first connection conductor extends from the input terminal of the amplifier circuit to the first electrode of the substrate such that one side of the first pair of opposing sides of the semiconductor chip intersects with the first connection conductor. Extends, The second connection conductor may be configured such that the second connection conductor and the second electrode of the substrate are connected at the output terminal of the amplifying circuit so that one side of the pair of second opposing sides of the semiconductor chip intersects each other. High frequency power amplifier module, characterized in that extending to. The method of claim 1, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 1, Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 1, Each of the first and second transistors is a bipolar transistor. The method of claim 1, And a distance between the input terminal and the output terminal of the amplifying circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and a second opposing pair and having an amplifying circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a plurality of second connection conductors electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected with the input terminal of the first transistor, the output terminal of the amplifying circuit is connected with the output terminal of the second transistor, The first connection conductor extends from the input terminal of the amplifier circuit to the first electrode of the substrate such that one side of the first pair of opposing sides of the semiconductor chip intersects with the first connection conductor. Extend, Each of the plurality of second connection conductors may be formed at the output terminal of the amplifying circuit such that each of the plurality of second connection conductors and one side of the pair of the second opposing sides of the semiconductor chip cross each other. A high frequency power amplifier module, characterized in that extending to the second electrode of the substrate. The method of claim 6, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 6, Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 6, Each of the first and second transistors is a bipolar transistor. The method of claim 6, And a distance between the input terminal and the output terminal of the amplifying circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected with the input terminal of the first transistor, the output terminal of the amplifying circuit is connected with the output terminal of the second transistor, The first connecting conductor extends in a first direction, and the second connecting conductor extends in a second direction different from the first direction, An angle formed between the first direction and the second direction is in a range of 72 to 180 degrees when the one surface of the substrate is viewed in plan view. The method of claim 11, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 11, Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 11, Each of the first and second transistors is a bipolar transistor. The method of claim 11, And a distance between the input terminal and the output terminal of the amplifying circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected with the input terminal of the first transistor, the output terminal of the amplifying circuit is connected with the output terminal of the second transistor, A first direction defined by an extension line from the first electrode to the input terminal of the amplification circuit and a second direction defined by an extension line from the second electrode to the output terminal of the amplification circuit The angle formed is in the range of 72 to 180 degrees high frequency power amplifier module. The method of claim 16, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 16, Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 16, Each of the first and second transistors is a bipolar transistor. The method of claim 16, And a distance between the input terminal and the output terminal of the amplifying circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected with the input terminal of the first transistor, the output terminal of the amplifying circuit is connected with the output terminal of the second transistor, The first connecting conductor extends in a first direction, and the second connecting conductor extends in a second direction different from the first direction, The angle formed between the first direction and the second direction is about 90 degrees when the one surface of the substrate is viewed in plan view. The method of claim 21, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 21, Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 21, Each of the first and second transistors is a bipolar transistor. The method of claim 21, And a distance between the input terminal and the output terminal of the amplifying circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected to the input terminal of the first transistor, the output terminal of the amplifying circuit is connected to the output terminal of the second transistor, And the distance between the first electrode and the input terminal of the amplifying circuit is longer than the distance between the second electrode and the output terminal of the amplifying circuit. The method of claim 26, And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 26, Each of the first and second transistors comprises a field effect transistor having a gate, a source and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 26, Each of the first and second transistors is a bipolar transistor. The method of claim 26, And a distance between the input terminal and the output terminal of the amplifier circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more. A substrate having first and second electrodes, A quadrilateral semiconductor chip mounted on one surface of the substrate, the semiconductor chip having a first and second opposing pairs and having an amplifier circuit having an input terminal and an output terminal; A first connection conductor electrically connecting the first electrode of the substrate and the input terminal of the amplification circuit of the semiconductor chip; And a second connection conductor electrically connecting the second electrode of the substrate and the output terminal of the amplification circuit of the semiconductor chip, The first and second electrodes are formed on the one surface; The amplifying circuit has first and second transistors, the first and second transistors having an input terminal and an output terminal, and the output terminal of the first transistor is connected to the input terminal of the second transistor. The input terminal of the amplifying circuit is connected to the input terminal of the first transistor, the output terminal of the amplifying circuit is connected to the output terminal of the second transistor, The first connecting conductor extending from the first electrode to the input terminal of the amplifying circuit is longer than the second connecting conductor extending from the second electrode to the output terminal of the amplifying circuit. High frequency power amplifier module. The method of claim 31, wherein And the output terminal of the first transistor and the input terminal of the second transistor are connected to each other via a matching circuit. The method of claim 31, wherein Each of the first and second transistors includes a field effect transistor having a gate, a source, and a drain, The input terminal of the first transistor is the gate of the field effect transistor of the first transistor, And said output terminal of said second transistor is said drain of said field effect transistor of said second transistor. The method of claim 31, wherein Each of the first and second transistors is a bipolar transistor. The method of claim 31, wherein And a distance between the input terminal and the output terminal of the amplifier circuit is 0.3 mm or more, and the stability coefficients of the first and second transistors are 1 or more.

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