KR100560868B1 - Plasma display panel - Google Patents

Abstract

A plasma display panel capable of reducing a driving voltage is disclosed.

A plasma display panel according to the present invention includes: an upper plate having a sustain electrode pair, an upper dielectric layer, and a protective film sequentially formed on an upper substrate; A lower plate having an address electrode, a lower dielectric layer, a partition wall, and a phosphor layer sequentially formed on the lower substrate; And a partition wall spaced apart from the upper plate and the lower plate by a predetermined distance, wherein a lower layer of the second electron emission material for reducing driving voltage may be formed on an upper surface of the lower dielectric layer below the phosphor layer and an inner surface of the partition wall.

Therefore, the present invention forms a material layer having a low work function under the phosphor of the lower plate, thereby not only improving luminous efficiency due to secondary electrons but also enabling low voltage driving, thereby reducing power consumption.

Plasma Display Panel, Work Function, Secondary Electronics, Low Voltage Driving

Description

Plasma display panel {Plasma display panel}             

1 is a perspective view showing a cell structure which is typically arranged in a matrix form on the AC PDP.

2 is a cross-sectional view illustrating a cell structure of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a cross-sectional view illustrating a cell structure of a plasma display panel according to another exemplary embodiment of the present invention.

4 is a view for explaining the secondary electron emission according to the work function.

<Name of the code for the main part of the drawing>

10: upper substrate 12: lower substrate

14, 16: sustain electrode pair 18: upper dielectric layer

20: protective layer 22: address electrode

24: lower dielectric layer 26: partition wall

28: phosphor layer 31, 33: material layer having a low work function

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of reducing a driving voltage.

Recently, as a flat panel display device, a plasma display panel (hereinafter, referred to as a 'PDP'), which is easy to manufacture a large panel, has attracted attention. The PDP normally displays an image by adjusting the discharge period of each pixel according to the digital video data. As such a PDP, an AC PDP having three electrodes as shown in FIG. 1 and driven by an AC voltage is representative.

1 is a perspective view showing a cell structure which is typically arranged in a matrix form on the AC PDP.

Referring to FIG. 1, a PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on an upper substrate 10, and an upper substrate 12. A lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28 formed sequentially on the substrate. At this time, the upper substrate 10 and the lower substrate 12 are spaced apart in parallel by the partition wall (26).

Each of the sustain electrode pairs 14 and 16 has a relatively wide width and is composed of transparent electrodes 14A and 16A made of transparent electrode material (ITO) for visible transmission, and has a relatively narrow width and transparent electrodes 14A and 16A. It consists of metal electrodes 14B and 16B for compensating for the resistive component. The sustain electrode pair includes a scan electrode 14 and a sustain electrode 16 according to a pulse applied thereto. The scan pulse for panel scanning and the sustain pulse for sustaining discharge are mainly supplied to the scan electrode 14, and the sustain pulse is mainly supplied to the sustain electrode 16.

Charges are accumulated in the upper dielectric layer 18 and the lower dielectric layer 24 during discharge.

The passivation layer 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used.

The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data pulse for selecting cells to be displayed.

The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells.

The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue.

Then, an inert gas for gas discharge is injected into the discharge space therein.

In the conventional plasma display panel configured as described above, one discharge cell is selected by the opposite discharge between the scan electrode 14 and the sustain electrode 16, and then between the scan electrode 14 and the address electrode 22. The data is displayed by the surface discharge.

At this time, the efficiency of visible light is determined according to the degree of excitation of the phosphor after the surface discharge. In this case, researches on high efficiency phosphors are actively conducted to improve the degree of excitation of the phosphors.

However, even when a high-efficiency phosphor is used, there is a limit in improving the degree of excitation of the phosphor, and there is a problem in that the driving voltage is increased to increase the degree of excitation of the phosphor, thereby increasing power consumption.

Therefore, there is an urgent need for research on a plasma display panel capable of driving a low voltage while improving the degree of excitation of the phosphor.

The present invention has been made to solve the above problems, an object of the present invention is to provide a plasma display panel that can improve the luminous efficiency and reduce the driving voltage.

According to a first preferred embodiment of the present invention for achieving the above object, a plasma display panel comprises: an upper plate having a sustain electrode pair, an upper dielectric layer and a protective film formed sequentially on the upper substrate; A lower plate having an address electrode, a lower dielectric layer, a partition wall, and a phosphor layer sequentially formed on the lower substrate; And a partition wall spaced apart from the upper plate and the lower plate by a predetermined distance, wherein the lower plate has a secondary electron emission material layer formed on an upper surface of the lower dielectric layer below the phosphor layer and an inner surface of the partition wall for reducing driving voltage. .

According to a second preferred embodiment of the present invention, a plasma display panel includes: an upper plate having a sustain electrode pair, an upper dielectric layer, and a protective film which are sequentially formed on an upper substrate; A lower plate having an address electrode, a lower dielectric layer, a partition wall, and a phosphor layer sequentially formed on the lower substrate; And a partition wall spaced apart from the upper plate and the lower plate by a predetermined distance, wherein the lower plate includes a lower layer of the lower portion of the phosphor layer except for an upper surface of the lower dielectric layer corresponding to the address electrode. And an upper surface of the dielectric layer and an inner surface of the partition wall.

According to the first and second embodiments of the present invention, the material having a low work function may be one of molybdenum and tungsten carbon nanotubes.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2 is a cross-sectional view illustrating a cell structure of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on the upper substrate 10, and on the lower substrate 12. A lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28 formed sequentially on the substrate. At this time, the upper substrate 10 and the lower substrate 12 are spaced apart in parallel by the partition wall (26).

Each of the sustain electrode pairs 14 and 16 has a relatively wide width and a transparent electrode made of transparent electrode material (ITO) for visible transmission, and has a relatively narrow width to compensate for the resistance of the transparent electrodes 14A and 16A. It consists of a metal electrode. The sustain electrode pair includes a scan electrode 14 and a sustain electrode 16 according to a pulse applied thereto. The scan pulse for panel scanning and the sustain pulse for sustaining discharge are mainly supplied to the scan electrode 14, and the sustain pulse is mainly supplied to the sustain electrode 16.

Charges are accumulated in the upper dielectric layer 18 and the lower dielectric layer 24 during discharge.

The protective film 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used.

The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data pulse for selecting cells to be displayed.

The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells.

The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue.

Then, an inert gas for gas discharge is injected into the discharge space therein.

In the plasma display panel provided as described above, a material having a low work function (31) as a material for emitting electrons for reducing driving voltage between the phosphor layer 28 and the lower dielectric layer 24 is used. A layer has been formed. Here, the material layer 31 having a low work function may be one of molybdenum (Mo), tungsten (W), and carbon nanotubes (CNT). In addition, the material layer 31 having a low work function may be a material included in a range of Φ = 10 eV or less of a normal work function.

The material layer 31 having the low work function may be formed on the upper surface of the lower dielectric layer 24 below the phosphor layer 28 and the inner surface of the partition wall 26.

For example, as shown in FIG. 4, in the case of a conventional material, secondary electrons are emitted only when a voltage of 100% or more of the work function φ1 is applied. Secondary electrons may be emitted even when a voltage equal to or less than the work function φ1 in the range of Φ = 10 eV is applied.

Thus, by forming the material layer 31 below the phosphor layer 28 within the range of Φ = 10 eV of the normal work function, sufficient secondary electrons are emitted even when a low driving voltage is applied. There is an effect that the discharge efficiency can be improved by increasing the degree of excitation of the layer 28.

3 is a cross-sectional view illustrating a cell structure of a plasma display panel according to another exemplary embodiment of the present invention.

The plasma display panel of FIG. 3 is also similar to the plasma display panel of FIG. 2. However, the position where the material layer 33 having a low work function is formed is different.

That is, in the plasma display panel according to another embodiment of the present invention, a work function as a material for emitting electrons to reduce driving voltage on the upper surface of the lower dielectric layer 24 under the phosphor layer 28 and the inner surface of the partition 26 is reduced. The lower material layer 33 is formed, but the lower work function material layer 33 is not formed on the upper surface of the lower dielectric layer 24 corresponding to the address electrode 22. That is, the material layer 33 having the low work function may be formed on the upper surface of the lower dielectric layer 24 and the partition wall below the phosphor layer 28 except for the upper surface of the lower dielectric layer 24 corresponding to the address electrode 22. 26) It is preferably formed on the inner surface.

As in the plasma display panel according to another exemplary embodiment of the present invention, the material layer 33 having a low work function is not formed in the portion corresponding to the address electrode 22, thereby preventing the address electrode 22 from being discharged. Damage to the address electrode 22 due to intensive ion bombardment can be prevented.

In general, one embodiment of the present invention and another embodiment of the present invention, one discharge cell is first selected by the counter discharge between the scan electrode 14 and the sustain electrode 16, the wall charge is the phosphor layer 28 ) Will be created on the surface.

The wall charges thus generated react with the material layers 31 and 33 having a low work function to emit a large amount of secondary tanks.

Accordingly, even when a low voltage is applied during the surface discharge between the scan electrode 14 and the address electrode 22, the phosphor layer 28 is excited more by the secondary electrons that are already generated, thereby improving the luminous efficiency. Can be. That is, since the secondary electrons as described above or higher than the conventional ones can be emitted with a lower voltage drive than the conventional ones, the low voltage driving and the luminous efficiency can be improved at the same time.

As described above, according to the present invention, by forming a material layer having a low work function that facilitates secondary electron emission under the phosphor layer, there is an effect of simultaneously improving low voltage driving and luminous efficiency.

Claims (4)

An upper plate having a sustain electrode pair, an upper dielectric layer, and a protective film sequentially formed on the upper substrate; A lower plate having an address electrode, a lower dielectric layer, a partition wall, and a phosphor layer sequentially formed on the lower substrate; And A partition wall spaced apart from the upper plate and the lower plate by a predetermined distance; And a second electron emission material layer on the lower plate is formed on an upper surface of the lower dielectric layer under the phosphor layer and an inner surface of the partition wall. An upper plate having a sustain electrode pair, an upper dielectric layer, and a protective film sequentially formed on the upper substrate; A lower plate having an address electrode, a lower dielectric layer, a partition wall, and a phosphor layer sequentially formed on the lower substrate; And And partition walls for separating the upper and lower plates by a certain distance. Including, The lower plate may include a second electron emission material layer formed on the upper surface of the lower dielectric layer and the inner surface of the barrier layer below the phosphor layer except for the upper surface of the lower dielectric layer corresponding to the address electrode. panel. The plasma display panel of claim 1 or 2, wherein the second electron emission material layer for reducing the driving voltage is one of molybdenum and tungsten carbon nanotubes. The plasma display panel as claimed in claim 1 or 2, wherein the secondary electron emission material layer for reducing the driving voltage is a material within a range of Φ = 10 eV or less of a normal work function.

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