KR100560802B1 - Flash memory device having partial copy back mode of operation - Google Patents

Abstract

The present invention relates to a NAND flash memory having a partial copy back mode of operation, comprising: a cell array consisting of unit pages; A page buffer comprising unit page buffers corresponding to the unit pages and storing data; A selection circuit for selecting one or more unit page buffers to be initialized among the unit page buffers during a partial copy back operation; And a controller for generating signals for controlling the page buffer and the selection circuit.

Description

Flash memory device having a partial copy back operation mode {FLASH MEMORY DEVICE HAVING PARTIAL COPY BACK MODE OF OPERATION}

1 is a conceptual diagram illustrating a general copy back operation.

2 is a conceptual diagram illustrating a read operation according to the present invention.

3 is a conceptual diagram illustrating a partial copy back operation according to the present invention.

4 is a block diagram illustrating a flash memory device having a partial copy back operation mode according to the present invention.

FIG. 5 is a circuit diagram illustrating the page buffer of FIG. 4.

6 is a circuit diagram illustrating the selection circuit of FIG. 4.

FIG. 7 is a circuit diagram illustrating the input device of FIG. 4.

FIG. 8 is a timing diagram illustrating an output signal of the first input buffer of FIG. 7.

FIG. 9 is a timing diagram illustrating an output signal of the second input buffer of FIG. 7.

10 is a timing diagram illustrating a partial copy back operation according to the present invention.

Explanation of symbols on the main parts of the drawings

100: memory controller 200: flash memory

210: cell array 220: page buffer

221, 222, 223, 224: unit page buffer

230: selection circuit 240: input device

241, 242: input buffer 243: decoder

250: page buffer controller 300: column decoder

The present invention relates to a flash memory, and more particularly to a flash memory device having a partial copy back operation mode.

An electrically erasable and programmable nonvolatile semiconductor memory device can electrically erase already written data and program new data. In particular, NAND flash memory devices provide higher densities than other well-known types of nonvolatile semiconductor memory devices.

NAND flash memory devices, which are useful for high-density and large capacity, are widely used in mobile communication environments, set-top boxes, or game machines, and their application range is gradually increasing. NAND flash memory devices can basically perform read, write (or program) and erase operations, and require a copy back function to meet new applications.

In a NAND flash memory device, a copy back operation refers to moving data stored in a source page to a target page. In other words, the copy back operation temporarily stores the data stored in the source page in the page buffer, and then immediately stores the data back in the target page without reading out of memory. By using the copyback function, the process of reading out the data of the source page to the outside and the loading of the external data can be omitted, thereby greatly improving the performance of the memory system.

Meanwhile, the NAND flash memory device may not support an overwrite mode due to a memory structure. Therefore, in order to store data on a specific page, you must select a page that is in an erased state. Therefore, in order to perform a write operation on a page where data is already written, an erase operation must be preceded.

However, since the erase time of the flash memory device is generally several msec, if the erase operation is performed before each write operation as described above, there is a problem in that performance is degraded. Therefore, the memory controller copies and moves the data of the page to be managed to a specific address in the erased state, and erases the area including the original data block by block at the time of spare time.

1 is a conceptual diagram illustrating a well-known copy back operation. Referring to FIG. 1, a flash memory device includes a memory controller 10 and a flash memory 20. The memory controller 10 applies an address and a control signal to the flash memory 20 according to an operation mode. The flash memory 20 includes a cell array 21 for storing data and a page buffer 22 for temporarily storing the data during a copy back operation.

The cell array 21 is composed of a plurality of pages. Each page consists of cells that share the same word line. One page is usually 512 bytes, and recently 2k bytes of large memory have emerged. The page becomes a basic unit of read and write operations.

The copy back operation consists of reading the data of the source page S into the page buffer 22 and programming the data stored in the page buffer 22 into the target page D.

When the copy command CMD and the address Addr corresponding to the source page S are input from the memory controller 10, the data Unit k stored in the source page S is stored in the page buffer 22. Copied. When the address corresponding to the copy back command CMD and the target page D is input, the data Unit k stored in the page buffer 22 is copied back to the target page D.

On the other hand, in recent years, research is being actively conducted to combine unit pages, which are basic units of read and write operations, into one large page unit in order to increase the operation speed and reduce the chip size. That is, in the copy back operation, data of a plurality of unit pages is simultaneously copied to the page buffer, and data stored in the page buffer is simultaneously copied back to the target page.

If the memory controller 10 can manage data (Unit k-3, Unit k-2, Unit k-1, Unit k) stored in a plurality of unit pages at the same time, the operation is not a big problem. . However, if the memory controller 10 can manage only unit pages, the operation causes a problem that data of unnecessary unit pages is also copied back together.

For example, even if only part of the data of the unit pages stored in the page buffer is copied, the data of the remaining unit pages that share the same word line is also copied together due to the operation principle of the flash memory device.

In particular, a page of a NAND flash memory device has recently been enlarged from 512 bytes to 2k bytes. However, most of the existing controllers manage data in units of 512 bytes, and thus face the above problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a flash memory capable of performing a copy back operation on a unit page basis.

According to an aspect of the present invention, there is provided a flash memory device including a cell array including pages including a source and a target page; A page buffer for storing data of the source page; And means for selecting data to be initialized among data stored in the page buffer during the partial copy back operation.

In this embodiment, each of the pages may be divided into unit pages which are basic units of a read and write operation.

In this exemplary embodiment, the page buffers may be divided into unit page buffers corresponding to the unit pages and being basic units of initialization.

Another aspect of the flash memory device according to the present invention includes a cell array consisting of unit pages; A page buffer comprising unit page buffers corresponding to the unit pages, and storing data; A selection circuit for selecting one or more unit page buffers to be initialized among the unit page buffers during a partial copy back operation; And a controller for generating signals for controlling the page buffer and the selection circuit.

In this embodiment, the unit page is a basic unit of read and write operations.

In this embodiment, the page buffer comprises: a latch for storing data; And a reset circuit for initializing the latch.

In this embodiment, the reset circuit is characterized in that the latch is initialized in response to a signal output from the selection circuit.

In this embodiment, the reset circuit is constituted by an NMOS transistor.

In this embodiment, the control device, the page buffer controller for controlling the signals input to the page buffer; And an input device for controlling signals input to the selection circuit.

In this embodiment, the page buffer controller is characterized in that for generating a control signal (LAT) for initializing the page buffer in accordance with the operation mode.

In this embodiment, the control signal LAT is supplied to the page buffer through the selection circuit.

In this embodiment, the input device comprises: a first input buffer for generating a first control signal SET in synchronization with the first and second command signals; And means for detecting an address input after the first command signal and generating a second control signal ADDR2.

In this embodiment, the means for generating the second control signal comprises: a second input buffer for generating a control signal ADDR by detecting a column address separating the unit page; And a decoder for decoding the control signal ADDR to generate the second control signal ADDR2.

In this embodiment, the control signal ADDR is sensed in synchronization with the write enable signal.

Another aspect of a flash memory device according to the present invention includes a cell array consisting of unit pages; A page buffer comprising unit page buffers corresponding to the unit pages, each unit page buffer including a latch for storing data and a reset circuit for initializing the latch; A page buffer controller for controlling signals input to the page buffer; A selection circuit for selecting one or more unit page buffers to be initialized during a partial copy back operation and enabling reset circuits of the selected unit page buffers; In the partial copy back operation, it characterized in that it comprises an input device for controlling the signals input to the selection circuit.

In this embodiment, the unit page is a basic unit of read and write operations.

In this embodiment, the reset circuit is constituted by an NMOS transistor.

In this embodiment, the page buffer controller is characterized in that for generating a control signal (LAT) for initializing the page buffer in accordance with the operation mode.

In this embodiment, the control signal LAT is supplied to the page buffer through the selection circuit.

In this embodiment, the input device comprises: a first input buffer for generating a first control signal SET in synchronization with the first and second command signals; And means for detecting an address input after the first command signal and generating a second control signal ADDR2.

In this embodiment, the means for generating the second control signal comprises: a second input buffer for generating a control signal ADDR by detecting a column address separating the unit page; And a decoder for decoding the control signal ADDR to generate the second control signal ADDR2.

In this embodiment, the control signal ADDR is sensed in synchronization with the write enable signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a conceptual diagram illustrating copying data of a source page into a page buffer. Referring to FIG. 2, a flash memory device includes a memory controller 100 and a flash memory 200. The flash memory 200 includes a cell array 210 for storing data and a page buffer 220 for temporarily storing data of the cell array 210 during a copy back operation.

The cell array 210 is composed of a plurality of pages sharing the same word line as is well known. Among the pages, a source page S and a target page D are included. Meanwhile, in the present invention, one page is composed of a plurality of unit pages that form a basic unit of a read and write operation. In FIG. 2, one page is composed of four unit pages.

The page buffer 220 temporarily stores data of the source page S during the copy operation. Data stored in the page buffer 220 is transferred to the target page D by a copy back operation.

When a command CMD0 for commanding a copy operation and an address Addr (S) corresponding to the source page S are applied from the memory controller 100, the data stored in the source page S (Unit k-3). , Unit k-2, Unit k-1, and Unit k are copied to the page buffer 220.

 3 is a conceptual diagram illustrating copying data stored in a page buffer to a target page. The core of the present invention is to copy back from the data (Unit k-3, Unit k-2, Unit k-1, Unit k) copied to the page buffer 220 before copying back to the target page (D) Copyback occurs after initializing the unused data (Unit k-1, Unit k). As a result, only the data (Unit k-3, Unit k-2) is copied back to the target page (D), and the previous data (Unit l-1, Unit l) is maintained as it is. Therefore, if the page buffer 220 can select the data to be copied and the data to be initialized, the copy back operation can be performed for each unit page.

After initializing data that is not desired to be copied, a command CMD1 for commanding a copy back operation and an address Addr (D) corresponding to a target page D are input from the memory controller 100. The command CMD1 and the address Addr (D) may be repeated, and the number of unit pages to be copied back is determined according to the number of repetitions. By the copy back operation, the data (Unit k-3, Unit k-2) stored in the page buffer 220 is copied back to the target page (D).

4 is a block diagram of a flash memory device showing the most preferred embodiment of the present invention. Referring to FIG. 4, a flash memory device performing a partial copy back operation may include data to be backed up and initialized during a partial copy back operation in addition to the cell array 210, the page buffer 220, and the page buffer controller 250. It further includes a selection circuit 230 for selecting a and an input device 240 for controlling the signals input to the selection circuit 230.

The cell array 210 is composed of a plurality of pages, and each page is composed of unit pages that share the same word line and form a basic unit of a read and write operation. For example, one page has a memory capacity of 2k bytes, and one unit page has a memory capacity of 512 bytes.

The page buffer 220 includes unit page buffers corresponding to the unit pages, respectively. One unit page buffer 221 includes a latch for storing data and a reset circuit for initializing the latch. The configuration and operation principle of the page buffer 220 will be described with reference to FIG. 5 to be described later.

The page buffer controller 250 controls signals PLOAD, BLSHF, and BLSLT input to the page buffer 220 and a signal LAT input to the page buffer 220 through the selection circuit 230. do. A timing diagram for the control signals is shown in FIG. 10. Details of the operation of the page buffer controller 250 and the control signals are obvious to those skilled in the art and thus will be omitted.

The selection circuit 230 provides a means for selecting data to be initialized and data to be copied during a partial copy back operation. The selection circuit 230 provides signals corresponding to a unit page buffer for storing data to be copied back and a unit page buffer for storing data to be initialized. The configuration and operation principle of the selection circuit 230 will be described with reference to FIG.

The input device 240, together with the selection circuit 230, forms the core of the present invention and generates signals for controlling the selection circuit 230 during the partial copy back operation. The input device 240 operates by receiving a command CMD, an address Addr, and a control signal ctrl from the memory controller 100, and operates the signals SET, which are input to the selection circuit 230. ADDR2). The configuration and operation principle of the input device 240 will be described with reference to FIG.

FIG. 5 is a circuit diagram illustrating an embodiment of the page buffer of FIG. 4. In FIG. 5, only four unit page buffers are illustrated as an example, and only the page buffers connected to one bit line are illustrated in each unit page buffer 221 to 224. In practice, however, the fact that there are a larger number of page buffers in one unit page buffer 221 and that they all have the same structure is obvious to those skilled in the art.

The unit page buffer 221 includes precharge means, a latch for temporarily storing data, a control transistor for controlling a bit line, and a reset circuit for initializing the state of the latch. The data temporarily stored in the latch is initialized when the selection signal Sel0 becomes 'H' while the PLOAD signal input to the gate of the precharge means is 'L'. When the data of the latch is initialized, the previous data is maintained as it is not programmed during the copy back operation.

However, when the selection signal Sel0 is 'L', the NMOS transistors constituting the reset circuit are turned off, and the data stored in the latch is retained. Thus, in the copy back operation, data stored in the latch is programmed in the target page.

As a result, the selection signal Sel0 determines whether the data stored in the latch is held or initialized.

6 is a circuit diagram illustrating an embodiment of the selection circuit of FIG. 5. Referring to FIG. 6, the selection circuit 230 may include a control signal LAT generated from the page buffer controller 250 and first and second control signals SET and ADDR2 generated from the input device 240. In response to).

The control signal LAT is a signal for initializing the page buffer 220 according to an operation mode. The control signal LAT is supplied to the page buffer 220 through the selection circuit 230.

As shown in FIG. 8, the first control signal SET is generated in synchronization with the first and second command signals. When the program command CMD2 is enabled while the partial copy back command CMD1 is enabled, the first control signal SET is generated. The second control signal ADDR2 will be described in detail with reference to FIGS. 7 and 9 to be described later.

Referring to FIG. 6, the decoded second control signal ADDR2 has 16 input means. In a state where the control signal LAT is disabled and the first control signal SET is enabled, when ADDR [1: 0] = 00, nADDR_0 [0] and nADDR_0 [1] are simultaneously applied to select signal Sel0. Becomes 'L', and the remaining selection signals Selk (k = 1 to 3) become 'H'. By the same principle, when ADDR [1: 0] = 01, only the selection signal Sel1 becomes 'L'. When ADDR [1: 0] = 10, only the selection signal Sel2 becomes 'L', and ADDR [1: If 0] = 11, only the selection signal Sel3 becomes 'L'.

For example, when only the unit page buffers 223 and 224 are to be initialized, the selection signals Sel0 and Sel1 may be 'L', and the selection signals Sel2 and Sel3 may be 'H'. All unit page buffers selected by 'H' are initialized.

FIG. 7 is a block diagram of the input device of FIG. 4. Referring to FIG. 7, the input device 240 includes a first input buffer 241 for generating a first control signal SET in synchronization with the first and second command signals CMD1 and CMD2, and the first input buffer 241. A second input buffer 242 for detecting the address Addr (D1) input after the command signal CMD1 and generating the control signal ADDR, and a decoder 243 for decoding the control signal ADDR Include.

As shown in FIG. 8, the first control signal SET is generated in synchronization with the first and second command signals. When the program command CMD2 is enabled while the partial copy back command CMD1 is enabled, the first control signal SET is generated. The first control signal is supplied to the selection circuit 230 during the partial copy back operation.

As shown in FIG. 9, when the nWE signal is moved while the ALE signal is activated, the control signal ADDR corresponds to the address of the target page (for example, A ₀ to A ₇ , in response to the rising of the nWE signal). A ₈ to A ₁₆ , A ₁₇ to A ₂₄ , and A ₂₅ to X, where X can be high or low) occur sequentially over four cycles. The ALE and nWE are control signals ctrl supplied from the memory controller 100.

In general, in the case of an address input in four cycles, the first and second cycles designate a column address, and the third and fourth cycles designate a row address. The first and second cycles store information about a column address specifying a main area and a spare area, a column address specifying a unit page, a column address specifying each bit line, and the like.

According to an embodiment of the present invention, the control signal ADDR is determined according to a column address that designates a unit page corresponding to the second cycle. If there are four unit pages per page, two bits of address are required. The two-bit address ADDR [1: 0] is input to the decoder 243. The decoded signal is input to the selection circuit 230 as described above.

10 is a timing diagram for explaining a copy back operation.

Referring to FIG. 10, a process of first reading data of a source page S is preceded. In the state where the command latch enable signal (CLE) is enabled, a command (CMD0; 00h) for commanding a copy operation is input through the input / output line IO. After the command CMD0 is input, an address Addr (S) corresponding to the source page S is input through an input / output line while an address latch enable signal ALE is enabled. . The address Addr (S) specifies column and row addresses of the source page. Here, CLE and ALE are control signals ctrl input to the flash memory 200 from the memory controller 100. When the input of the address Addr (S) is completed, the RnB signal becomes 'L' and data in the source page is simultaneously copied to the page buffer in the tR period.

Before performing the copy back operation, a process of initializing data that is not desired to be copied back is performed. Sel0 is selected if ADDR [1: 0] = 00, Sel1 is selected if ADDR [1: 0] = 01, Sel2 is selected if ADDR [1: 0] = 10, and ADDR [1: 0] = If 11, Sel3 is selected. Referring to FIG. 10, the selected signal Seln maintains 'L' to keep the data of the latch in a copied state, and the unselected signal Seli emits a pulse to initialize the data of the latch.

For example, to copy only Unit k-3 and Unit k-2 from the data of the unit page buffer copied to the page buffer 220, Sel0 (ADDR [1: 0] = 00) and Sel1 (ADDR [1). : 0] = 01) to 'L', respectively, Sel2 (ADDR [1: 0] = 10) and Sel3 (ADDR [1: 0] = 11) to 'H' to initialize the latch, then copy You can do the back operation.

10, a command CMD1 8Ah for commanding a copyback operation is input through the input / output line IO while the command latch enable signal CLE is enabled. After the command CMD1 is input, an address Addr (D1) corresponding to the unit target page D1 is input through an input / output line while an address latch enable signal ALE is enabled. do. The address Addr (D1) designates a column and row address of the unit target page.

As shown in FIG. 10, in the case of an address input in four cycles, first and second cycles designate a column address, and third and fourth cycles designate a row address. The first and second cycles store information about a column address specifying a main area and a spare area, a column address specifying a unit page, and a column address specifying each bit line.

After the address input to the unit target page D1 is completed, the copy back command CMD1 and the address Addr (D2) corresponding to the unit target page D2 are input again. After repeatedly inputting the copy back command CMD1 and the addresses (Addr (D1) and Addr (D2)) corresponding to the unit target pages D1 and D2, the program command CMD2 is input. As a result, the data in the page buffer is programmed to the target page at the same time in the tPROG section with the RnB signal 'L'.

However, in the copy operation, the address corresponding to the authorized source page is don't care processed by the column address separating the unit page, and the entire page is copied at once. However, at the address corresponding to the authorized target page during the copyback operation, a column address for dividing the unit page is accepted to distinguish the unit page to be copied from the unit page that is not.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

According to the present invention, the copy back operation can be performed for each unit page during the copy back operation. Therefore, when the partial copy back operation is performed using the flash memory device according to the present invention, one large page can be managed for each unit page without changing the existing memory controller used for the unit page.

Claims (22)

A cell array including a source page storing data to be copied and a target page to which data stored in the source page is to be programmed; A page buffer that reads and temporarily stores data stored in the source page, and programs the temporarily stored data as the target page; And And a selecting means for selecting data to be copied back and data to be initialized among data stored in the page buffer during the partial copy back operation. The method of claim 1, Each of the pages may be divided into unit pages, which are basic units of a read and write operation. The method of claim 2, The page buffer may be divided into unit page buffers, each corresponding to the unit pages and being a basic unit of initialization. A cell array consisting of unit pages; A page buffer comprising unit page buffers corresponding to the unit pages, and storing data; A selection circuit for selecting one or more unit page buffers to be initialized among the unit page buffers during a partial copy back operation; And And a controller for generating signals for controlling the page buffer and the selection circuit. The method of claim 4, wherein And the unit page is a basic unit of a read and write operation. The method of claim 4, wherein The page buffer includes a latch for storing data; And a reset circuit for initializing the latch. The method of claim 6, And the reset circuit initializes the latch in response to a signal output from the selection circuit. The method of claim 6, The reset circuit is composed of an NMOS transistor. The method of claim 4, wherein The control apparatus includes a page buffer controller for controlling signals input to the page buffer; And an input device for controlling signals input to the selection circuit. The method of claim 9, The page buffer controller generates a control signal (LAT) for initializing the page buffer according to an operation mode. The method of claim 10, The control signal (LAT) is supplied to the page buffer through the selection circuit. The method of claim 9, The input device includes: a first input buffer configured to generate a first control signal SET in synchronization with the first and second command signals; And means for detecting an address input after the first command signal and generating a second control signal ADDR2. The method of claim 12, The means for generating a second control signal includes: a second input buffer for generating a control signal ADDR by detecting a column address for dividing the unit page; And a decoder for decoding the control signal ADDR to generate the second control signal ADDR2. The method of claim 13, The control signal ADDR is sensed in synchronization with a write enable signal. A cell array consisting of unit pages; A page buffer comprising unit page buffers corresponding to the unit pages, each unit page buffer including a latch for storing data and a reset circuit for initializing the latch; A page buffer controller for controlling signals input to the page buffer; A selection circuit for selecting one or more unit page buffers to be initialized during a partial copy back operation and enabling reset circuits of the selected unit page buffers; And an input device for controlling signals input to the selection circuit during the partial copy back operation. The method of claim 15, And the unit page is a basic unit of a read and write operation. The method of claim 15, The reset circuit is composed of an NMOS transistor. The method of claim 15, The page buffer controller generates a control signal (LAT) for initializing the page buffer according to an operation mode. The method of claim 18, The control signal (LAT) is supplied to the page buffer through the selection circuit. The method of claim 15, The input device includes: a first input buffer configured to generate a first control signal SET in synchronization with the first and second command signals; And means for detecting an address input after the first command signal and generating a second control signal ADDR2. The method of claim 20, The means for generating a second control signal includes: a second input buffer for generating a control signal ADDR by detecting a column address for dividing the unit page; And a decoder for decoding the control signal ADDR to generate the second control signal ADDR2. The method of claim 21, The control signal ADDR is sensed in synchronization with a write enable signal.

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