KR100549059B1 - Unified power flow controller without series injection transformers - Google Patents

Abstract

The present invention aims to propose a Unified Power Flow Controller (UPFC) without a series injection transformer. The UPFC consists of at least one pair of full bridge modules in each phase, and each pair of full bridge modules is connected in parallel with at least one series inverter and at least one parallel inverter each composed of one H-bridge module. And a DC link capacitor connected in parallel with the series inverter and the parallel inverter, wherein at least one parallel inverter constituting the full bridge module pairs is connected in series with each other through a single phase multiple winding transformer, and the full bridge At least one series inverter constituting the pair of modules is characterized in that directly connected to the line.

UPFC, series inverter, parallel inverter, series injection transformer, inverter

Description

UNITED POWER FLOW CONTROLLER WITHOUT SERIES INJECTION TRANSFORMERS}

1 is a block diagram of a UPFC system according to the prior art.

2 is a vector diagram of the voltage in the UPFC system of FIG.

3 is a block diagram of a UPFC system according to the present invention.

4A and 4B are circuit diagrams respectively illustrating a parallel inverter and a series inverter according to the present invention.

5A and 5B are graphs illustrating the switching scheme of the inverter according to the present invention.

6A to 6C are graphs and circuit diagrams for explaining the principle of gate pulse generation during PWM operation of a multi-bridge inverter.

7A-7C are graphs and timing diagrams for explaining output voltage and harmonic analysis for an inverter of one phase.

8 is a block diagram showing a DC voltage unbalance controller used in the UPFC system according to the present invention.

9 is a table showing the circuit constants used in the simulation to verify the operation of the UPFC in accordance with the present invention.

10A to 10B are block diagrams respectively illustrating a serial inverter controller and a parallel inverter controller in an UPFC system according to the present invention.

FIG. 11 is a diagram illustrating a scenario considered in a simulation for verifying the operation (in a steady state) of the UPFC according to the present invention. FIG.

12A to 12G are graphs showing the results of simulating the operation (at normal state) of the UPFC according to the present invention.

Fig. 13 is a disconnected diagram at the time of a track accident in the UPFC according to the present invention.

Fig. 14 is a flowchart for explaining the operation during a line accident in the UPFC according to the present invention.

FIG. 15 is a diagram illustrating a scenario considered in a simulation for verifying the operation (in case of a line accident) of the UPFC according to the present invention. FIG.

16A to 16C are graphs showing the results of simulating the operation (at the time of a line accident) of the UPFC according to the present invention.

17 is a conceptual diagram of the UPFC according to the present invention implemented as a real system.

The present invention relates to a Unified Power Flow Controller (hereinafter referred to as "UPFC") in which a series inverter can be directly connected to a line without a series injection transformer.

UPFC is a FACTS (Flexible AC Transmission System) device of a large-capacity voltage source inverter type using GTO Thyristor (GTO Turn-Off Thyristor). It is a device that controls power flow by connecting two inverters directly and in parallel to the transmission line. to be. The UPFC is expected to have an excellent effect on current flow control, transient stability, and low frequency resonance attenuation in power systems.

1 is a block diagram showing a system of a UPFC according to the prior art. Hereinafter, a configuration and operation of a conventional UPFC will be described with reference to FIG. 1.

As shown in FIG. 1, in the UPFC, a parallel inverter 100 and a series inverter 110 are connected in parallel through DC link capacitors 120. In addition, the parallel inverter 100 and the series inverter 110 are three-level inverters composed of four modules, and are connected in parallel through a phase control transformer 130. The UPFC having the above-described configuration eliminates low frequency harmonics by allowing the output voltage to be formed in a multi-pulse form. In addition, each module is composed of 12 GTO switches, each switch has a low breakdown voltage of the semiconductor switch, so that several GTO switches are connected in series.

On the other hand, the structure of the UPFC is configured such that STATCOM and SSSC share a DC link capacitor. Accordingly, the UPFC can directly control the active and reactive power of the line.

UPFC's parallel inverter 100 has two functions. One is to supply the active power required by the series inverter 110 through a DC link capacitor. This function keeps the DC link voltage constant in order to minimize the variation of the output voltage of the series inverter. Another function is to improve the voltage stability of the connection point by controlling reactive current.

The series inverter 110 of the UPFC has a function of independently controlling the active and reactive power by injecting a voltage having an arbitrary magnitude and phase into the line. The injection voltage to the series inverter has the same frequency and proper magnitude and phase angle for the power system, and the phase angle of the injection voltage is determined by the _firing angle (α _pq ) of the inverter, in the range of 0 <α _pq <2π. Can be adjusted arbitrarily. Also, as shown in FIG. 2, the magnitude of the injection voltage V _pq is adjusted by controlling the magnitude of the DC link voltage or by controlling the arc angle ν of the output voltage of the series inverter within the maximum range of V _pq . . The calculated injection voltage (V _pq ) is vectorized by the transformer coupled in series to the power supply voltage (V) to generate the power receiving voltage (V + V _pq ).

However, the DC voltage of the currently developed UPFC is approximately 20 kV, which is much lower than the operating voltage of the power system. This is due to the limitations of power semiconductors, and the maximum rating of the GTO thyristor that is actually applicable is about 6000V.

Therefore, in order to increase the DC link voltage of the UPFC, a series operation technique of the GTO device has been proposed. However, the serial operation of the GTO device is very difficult, and there are many problems in that the number of devices capable of serial operation is limited. In order to solve this problem, Renz B.A., Gyugyi L. On Power Delivery, Vol. 14, No. 4, pp. 1372-1381, October 1999, published a paper entitled "AEP Unified Power Flow Controller Performance" and proposed a method of using a step-down transformer for smooth coupling with a power system.

Yiqiang Chen, Mwinyiwiwa, B, Z. Wwolanski, and Boon-Teck Ooi are the IEEE Trans. on Power Delivery, vol 12, No.2, pp.901-907, April 1997, published a paper entitled "Regulating and Equalizing DC Capacitance Voltage in Multilevel STATCOM" to avoid device series operation and increase the operating voltage of the system. It is proposed to use a multilevel inverter. However, the multi-level inverter has a problem in that the output voltage is complicated to form and requires a large number of reverse coupling diodes.

In order to solve this problem, F.Z.Peng and J.S.Lai have reviewed the IEEE / IAS Annual Meeting. pp.2541-2548, Orlando, FL, Oct. 8A, 1995, "A Multilevel Voltage-Source Inverter with Separate DC Sources for Static Var Generation" and IEEE / IAS Annual Meeting. pp. 1009-1015, San Diego, CA, Oct. By publishing a paper entitled "Dynamic performance and control of a static var compensator using cascade multilevel inverter" by 6-10, 1996, we propose a multi-bridge STATCOM consisting of five equivalent single-phase full bridges and reduce its behavior and performance. The experiment was analyzed through.

The present applicant intends to propose a new UPFC using a single-phase full bridge that can be directly coupled to a line without a series injection transformer and insulated by a single-phase multiple transformer.

It is an object of the present invention to provide a UPFC in which a series inverter is directly coupled to the line without a series injection transformer.

It is another object of the present invention to provide an UPFC using a single phase full bridge insulated by a single phase multiple transformer while the series inverter is directly coupled to the line without the series injection transformer.

A feature of the present invention for achieving the above-described technical problem relates to a UPFC is composed of at least one pair of full bridge modules for each phase, each pair of full bridge modules are connected in parallel with a series inverter and a parallel inverter And at least one parallel inverter constituting the full bridge module pairs is connected in series with each other through a single-phase multiple winding transformer, and at least one series inverter constituting the full bridge module pairs is directly connected to a line. It is a UPFC without a series injection transformer.

Here, the series inverter is composed of one H-bridge module, and the parallel inverter is preferably composed of one H-bridge module.

In addition, the UPFC further includes a thyristor switch and a breaker between one end of the series inverter and the line, and the thyristor switch preferably bypasses the overcurrent flowing in the line and operates the breaker.

The full bridge module pair may further include a DC link capacitor between the serial inverter and the parallel inverter, and each of the DC link capacitors may include three equivalent DC link capacitors.

More preferably, the DC link capacitor further includes a voltage unbalance controller to equalize the DC link capacitor voltage.

The series inverter further includes an LC filter at its output stage, and the LC filter preferably removes harmonics contained in the output waveform.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the UPFC according to the present invention.

3 is a block diagram showing the configuration of the UPFC according to the present invention. Referring to FIG. 3, the UPFC according to the present invention includes at least one pair of full bridge modules for each phase, and each pair of full bridge modules 300 constituting the UPFC is connected in parallel through a DC link capacitor 330. Inverter 320 and series inverter 310 are connected in parallel. The parallel inverter is composed of one H-bridge module, and the parallel inverters constituting each pair of full bridge modules are connected in series through a single-phase multiple winding transformer 340 for isolation. In addition, the series inverter is also composed of one H-bridge module, and the series inverters constituting each pair of full bridge modules are directly connected to a line.

Meanwhile, the UPFC according to the present invention further includes a thyristor switch and a breaker between one end of the series inverter and the line, so that the series inverter can be separated from the line when an accident occurs in the line. If overcurrent flows in the line, the overcurrent is bypassed by the thyristor switch and then the mechanical breaker is operated. However, when the maximum value of the fault current is smaller than the maximum current capacity of the series inverter switch, the bypass function through the control of the inverter may be applied rather than the bypass function by the thyristor switch. Therefore, the series inverter according to the present invention has two possible bypass functions by making a short circuit at the AC stage, the first of which turns on two upper switches of the series inverter at the same time, and the other is the lower switch of the series inverter. Turn both on at the same time.

Hereinafter, a structure and a switching method of an inverter of the UPFC according to the present invention will be described with reference to FIGS. 4A, 4B, 5A, and 5B. 4A and 4B are circuit diagrams illustrating a parallel inverter and a series inverter respectively connected to the parallel side and the serial side of the UPFC according to the present invention, respectively. 4A and 4B, the parallel inverter and the series inverter each consist of three equivalent single-phase H-bridge inverter modules.

5A and 5B are diagrams illustrating a method of operating a switch of each single-phase full bridge inverter to explain the switching method of the inverter. FIG. 5B illustrates the operation of the inverter switches S1, S2, S3, and S4 by dividing the output voltages into Vdc, 0, and -Vdc. FIG. 5A shows the switching operation for each state. .

6A to 6C illustrate a gate pulse generation principle during PWM operation of a multi-bridge inverter. FIG. 6A illustrates a carrier and a reference signal for generating a gate pulse of the first inverter of FIG. 4B. Referring to FIG. 6A, the frequencies of the carriers T1 and T2 are 360 Hz and have a phase difference of 180 degrees from each other. In addition, the carriers for generating the remaining two inverter gate pulses each have a phase difference of 120 degrees. 6B is a circuit diagram illustrating a logic circuit for generating a gate pulse using the above-described reference signal and carrier signal. In FIG. 6B, the carriers T1 and T2 are used as inputs for generating gate pulses of the inverter module. 6C is a timing diagram showing four gate pulses supplied to the switches S1, S2, S3, and S4, the output voltage of the inverter module INV1, and the reference signal Vref. 6C, it can be seen that the switching schemes of the switches S1 to S4 operate while satisfying the switching state of FIG. 5A. On the other hand, the gate pulse of the inverter module INV2 is generated through the same process.

7A to 7C are diagrams for describing output voltage formation and harmonic analysis results of one phase. FIG. 7A shows each output voltage V1, V2, V3 of the multi-bridge inverter, and VA which is finally injected into the line. As described above, the carrier shown in FIG. 6A is used to generate a gate pulse for forming the output voltage V1. That is, the three pairs of carriers have a phase difference of 120 degrees with each other. Each carrier frequency is 360 Hz and there are six carriers in total, resulting in a switching effect of about 3 kHz. Therefore, if the number of inverter modules is N, the output voltage can have a switching effect of N × 360 [Hz]. 7B is a graph illustrating a spectrum analysis result of one inverter module output voltage and three inverters connected in series. Referring to FIG. 7B, a large number of harmonics are included in one inverter module output voltage, but less harmonics are included in an output voltage in which three inverters are connected in series. 7C is a graph showing the THD analysis of the output voltage according to the number of inverter modules. Referring to FIG. 7C, it can be seen that as the number of inverter modules increases, the THD of the output voltage decreases. In the same number of inverter modules, if the modulation ratio MI is smaller than 0.4, it can be seen that the THD becomes relatively large. Therefore, the operating range of the modulation ratio is preferably between 0.5 and 1.0.

The UPFC according to the present invention has three equivalent DC link capacitors each. Since each capacitor is isolated from each other through the H-bridge module, an unbalanced voltage occurs. The DC link capacitor voltage is uneven due to various causes such as uneven capacitor leakage current, inverter dead time, asymmetrical operation during transients and disturbances, and the output voltage contains high levels of harmonics. In order to reduce this harmonic level of the inverter output voltage, the DC link capacitor voltage should be kept equal.

8 shows the structure of a voltage unbalance controller of a direct current capacitor. In addition, since each phase does not share a capacitor with each other, each phase separation control can be performed. The operation of the controller measures the voltage at the bus terminal connected to the parallel inverter and generates θ synchronized with the line voltage through the phase-locked loop, which is adjusted for each phase. Measure the DC capacitor voltage of one phase and divide the value by 3 to find the average value. The average value is compared with the voltage of each DC capacitor, and after passing through the PI controller, the phase angle correction Δα is obtained. The phase angle correction [Delta] [alpha] is added to [alpha], the output value of the parallel inverter controller, and generates reference signals Ref1, Ref2, Ref3 through a sine generator. The dc capacitor unbalance controller on the other phase repeats the same process.

In order to verify the operation of the UPFC composed of a multi-bridge inverter according to the present invention, a simulation was performed with EMTDC. The simulation model of the entire system is shown in FIG. The power system is modeled as a single infinite bus and the line inductance is modeled as a concentrated line constant. The circuit constant used in the simulation is as shown in FIG.

10A and 10B illustrate the structure of the UPFC controller used in the simulation, and show the controllers of the serial inverter and the parallel inverter, respectively, which perform automatic algae control. Automatic algae control is performed by vector control to control the line current using the control amount indicated by the DC signal in the steady state. The reference active and reactive power components i _q ^* and i _d ^* are determined by P _Ref and Q _Ref , which are required active and reactive power. This reference component is compared with the i _q and i _d components of the measured line current and produces Vpq and ρ that determine the magnitude and phase angle of the series inverter output voltage. In the controller of the parallel inverter, the magnitude of the output voltage depends on the magnitude of the DC voltage and only controls the phase angle of the output voltage. The external control loop of the controller regulates the line side bus terminal voltage and also controls the DC voltage. The external controller varies the phase angle α of the inverter output voltage with respect to the line side bus terminal voltage until a DC voltage is formed to the value necessary to compensate for the required reactive component.

In the scenario considered in the simulation, as shown in FIG. 11, the total simulation run time was set to 5.5 seconds, and the reference value of the active power P was initially set to 250 [MW], and the reference values were set at 1.5 seconds, 2.5 seconds, and 3.5 seconds. Changed. In addition, the reference value of reactive power Q was initially set to 0 [MVar], and the reference value was changed in 2.5 second, 3.5 second, and 4.5 second. The step characteristics of P _Ref and Q _Ref , which are reference values of active power and reactive power, were changed to confirm the dynamic characteristics of the UPFC according to the present invention.

12A to 12G show simulation results of EMTDC to analyze dynamic characteristics of the UPFC system according to the present invention. 12A and 12B show the tracking performance of the UPFC with respect to the reference values P _Ref and Q _Ref of the active and reactive power which change in steps. It can be seen that the series inverter controls the active and reactive power P and Q of the line according to the reference values P _Ref and Q _Ref of the active and reactive power by injecting an appropriate voltage into the transmission line. 12c shows that the parallel inverter maintains a constant bus terminal voltage by performing a STATCOM operation. 12d shows the voltage of the A phase DC capacitor of the UPFC. Although voltage deviation occurred due to PWM switching, it can be seen that each capacitor voltage is uniform. 12E shows the output voltage of the parallel inverter. In the parallel inverter, since each inverter module is connected to the coupling transformer, it can be seen that the waveform of the output voltage has a lower harmonic content than the output voltage waveform of the series inverter shown in FIG. 12H. By adding an LC filter to the output of the series inverter, the harmonics contained in the output waveform can be eliminated. 12f shows the change of the DC voltages Vdc1, Vdc2, Vdc3 and the average DC voltage Vdc ^* . Each DC capacitor voltage was initially assumed to be in equilibrium and randomly unbalanced the DC voltage at 1.4 seconds. FIG. 12G illustrates waveforms of reference signals Ref1, Ref2, and Ref3 which are final output values of the DC voltage unbalance controller shown in FIG. 8. Since the unbalance of DC voltage Vdc2 is larger than other DC voltages, the correction phase angle Δα ₂ is large. Therefore, as can be seen in FIG. 12G, when the DC voltage is in an unbalanced state, the phases of the reference signals Ref1, Ref2, and Ref3 are almost in phase.

Meanwhile, in order to confirm the operation of the protection circuit of the UPFC according to the present invention in the event of a line accident, a simulation was performed as shown in FIG. 13. It was assumed that a three-phase ground fault occurred on the front track where the UPFC was installed. As shown in FIG. 13, the measuring points of P and Q of the track were measured at the point immediately before the UPFC was installed. The proposed UPFC protects the parallel and series inverters from the fault current due to the operation of the protection circuit as shown in FIG. 14 when an accident occurs in the transmission line. The overcurrent detector detects overcurrent and generates a protection signal, which serves to switch the control of the series inverter from steady state control to transient control. Initially turn on the top switch of all full bridges at the same time to bypass the overcurrent, then close the mechanical breaker. The line voltage detector detects a low voltage on the line that may be caused by an accident and generates a protection signal to block the gate pulse of the parallel inverter. If the line fault is eliminated and the parallel inverter operates normally, the series inverter is operated by manually opening the mechanical breaker. At this time, since the serial inverter senses a reference value of active and reactive power of the controller operating in the automatic current control mode before the accident, the series inverter performs an operation of returning to the reference value normally after the accident is eliminated.

When a three-phase ground fault occurred on the track, simulation was performed in a simulation scenario as shown in FIG. 15 to confirm that the protection controller of the UPFC operates normally. The parallel inverter performs the reactive power control mode (Iq mode) and the series inverter operates in the voltage injection mode (Vpq mode) for time 0 to 0.6 seconds. The parallel inverter operates in the automatic voltage control mode (Vref mode) and the series inverter operates in the automatic current control mode (P, Q mode) for 0.6 ~ 1.2 seconds. After 1.2 seconds of accident and 1.3 seconds of elimination, the series inverter is returned to the track at 1.45 seconds.

16A to 16C are diagrams showing simulation results when an accident occurs on a track. 16A is a graph showing a change in line current. It can be seen that the line current rises to 2.4kA when an accident occurs on the track. 16B is a graph showing a change in active and reactive power of a line when the UPFC operates. As shown in FIG. 16B, it can be seen that a transient state occurs due to an accident, but the UPFC according to the present invention is not affected by the protection circuit operation of FIG. 13. FIG. 16C is a graph showing a DC capacitor voltage appearing in one inverter among three full bridge inverters configuring the A phase. Referring to FIG. 16C, although a slight transient state appears, it can be seen that the voltage is limited to a stable value due to the protection circuit operation of the UPFC.

FIG. 17 is a conceptual diagram illustrating an embodiment for implementing a system according to the present invention as a real system, and is intended to include commercially available elements. Hereinafter, the real system shown in FIG. 17 will be described in detail. H-Bridge's inverter devices are currently considered commercially available high-power GTO's FG6000AU-120D from Mitsubishi, whose rated voltage is 6kV (DC voltage 4.8kV) and rated current is 6kA (average rated current 1.5kA). )to be. Considering the stability of the device, the applicable device rating in system design can be estimated with a DC rated voltage of 4kV and an average rated current of 1.25kA.

In addition, assuming that the nominal voltage of the UPFC is 138kV, the inverter capacity is 150MVA, the H-bridges required for each phase are 6 pairs, and the maximum injection voltage on the series side is 50% of the operating voltage (phase voltage 40kV). Assume that In addition, the winding ratio of the primary side and the secondary side of the single phase multiple winding transformer is 24: 1. The RMS voltage of each H-bridge inverter is 3.33 kV. The DC rated voltage, which the two GTOs can reliably withstand, is 4kV, so each H-bridge can withstand a voltage of 3.33kV.

As shown in Fig. 17, the UPFC in the embodiment according to the present invention is composed of each equivalent pair of H-bridge modules. Since the H-bridge consists of a total of 36 pairs and each pair consists of 8 GTOs, the total number of GTOs used is 288.

The UPFC system according to the present invention is a new concept of UPFC system using a single phase full bridge inverter insulated by a single phase multiple winding transformer. The dynamic performance of the UPFC system according to the present invention was analyzed by EMTDC simulation, and the simulation model assumes that the UPFC system is connected to a 138kV transmission line, which is a first infinite bus power system.

In the conventional UPFC system, a series injection transformer must be provided. Since the series injection transformer has to be designed to have a low saturation region and a leakage impedance, it is regarded as a very important factor. However, the UPFC system according to the present invention proposes a new concept of UPFC without a series injection transformer. Accordingly, the UPFC system according to the present invention can be directly connected to a line without a series injection transformer and can flexibly increase the operating voltage by increasing the number of bridges of the inverter.

Claims (8)

Each phase consists of at least one full bridge module pair, Each of the full bridge module pairs includes at least one series inverter and at least one parallel inverter each configured as one H-bridge module, connected in parallel, and a DC link capacitor connected in parallel with the series inverter and the parallel inverter. , At least one parallel inverter constituting the full bridge module pairs are connected in series with each other through a single-phase multiple winding transformer, And at least one series inverter constituting the full bridge module pairs is directly connected to a line. delete delete The apparatus of claim 1, wherein the UPFC further includes a thyristor switch and a breaker between one end of the series inverter and a line, wherein the thyristor switch bypasses overcurrent flowing in the line and operates the breaker. UPFC without series injection transformer. delete The UPFC without a series injection transformer according to claim 1, wherein the DC link capacitors are provided with three corresponding DC link capacitors. 7. The UPFC of claim 1 or 6, wherein the DC link capacitor further includes a voltage imbalance controller to equalize the DC link capacitor voltage. 2. The UPFC of claim 1, wherein the series inverter further includes an LC filter at its output stage, and the LC filter removes harmonics contained in the output waveform.

Images