KR100546582B1 - Method Of Addressing Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel capable of compensating wall charge nonuniformity during an address discharge period.

The address method of the plasma display panel of the present invention can prevent the screen distortion by compensating the wall charge quantity nonuniformity in the address period by causing the address discharge to occur by the scanning order for each bit.

Description

Method of addressing plasma display panel {Method Of Addressing Plasma Display Panel}             

1 is a perspective view showing a discharge cell configured in a conventional high frequency plasma display panel.

FIG. 2 is a voltage waveform diagram supplied to each electrode shown in FIG. 1. FIG.

FIG. 3 is an overall electrode layout of the high frequency plasma display panel having the discharge cell of FIG. 1. FIG.

4 is a waveform diagram of voltages supplied to respective electrode lines shown in FIG. 3.

5A through 5D are diagrams illustrating address order of sub-fields of a high frequency plasma display panel according to an exemplary embodiment of the present invention.

6 is a drive waveform diagram corresponding to the address order of FIG. 5A;

FIG. 7 is a drive waveform diagram corresponding to the address order of FIG. 5B; FIG.

8 is a driving waveform diagram corresponding to the address order of FIG. 5C;

9 is a drive waveform diagram corresponding to the address order of FIG. 5D;

<Brief description of symbols for the main parts of the drawings>

2: upper substrate 4: high frequency electrode

6: lower substrate 8: data electrode

10: first dielectric layer 12: scanning electrode

13: second dielectric layer 14: partition wall

16: phosphor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display apparatus, and more particularly, to an address method of a plasma display panel capable of compensating wall charge nonuniformity in an address discharge period.

In recent years, as the demand for large flat panel display devices increases, studies on plasma display panels (hereinafter referred to as PDPs), which are easy to manufacture large-area panels, have been actively conducted. The PDP generally uses a gas discharge phenomenon to display an image using visible light generated by vacuum ultraviolet rays generated during gas discharge to emit phosphors. However, PDP is still in a state of low luminous efficiency compared to the cathode ray tube is required to improve it, and in order to improve the luminous efficiency, various researches on discharge method, cell structure, driving method, phosphor or protective film material and the like are in progress.

The PDP is usually composed of discharge cells corresponding to matrix pixels. Each of these discharge cells is selected by the address discharge according to the image data, and the vacuum ultraviolet rays generated by the continuous sustain discharge emit visible light by emitting the phosphor. In this case, since the PDP displays a gray scale necessary for displaying an image by adjusting the sustain discharge period, that is, the number of sustain discharges, the number of sustain discharges is an important factor in determining the luminous luminance and luminous efficiency of the PDP. However, when generating a sustain discharge using the existing low frequency alternating current (AC) voltage, the sustain discharge occurs only once at a short time for each applied voltage pulse, and most of the other time is a step for forming wall charges and preparing for the next discharge. By consuming the PDP, the light emission luminance and the light emission efficiency of the PDP were inevitably low.

In order to solve the low luminous luminance and luminous efficiency problems of the low frequency AC PDP, a method of applying a high frequency voltage as a discharge holding voltage has recently been introduced. When a high frequency voltage of several MHz to several hundred MHz is applied, a vibrating electric field is generated inside the discharge cell, and electrons are continuously vibrated to ionize and excite the discharge gas as it vibrates, thereby continuously discharging the electrons for most of the discharge time. Discharge, that is, high frequency discharge occurs. The high frequency discharge has a physical effect such as a positive column having a very high discharge efficiency when the distance between the electrodes is long in the glow discharge. Accordingly, there is an advantage that can significantly improve the discharge efficiency of the PDP when using a high frequency discharge.

Referring to FIG. 1, a perspective view of a discharge cell constructed in a conventional high frequency PDP is shown. The high frequency PDP discharge cell of FIG. 1 includes a high frequency electrode 4 disposed on the upper substrate 2, a data electrode 8 and a scanning electrode 12 disposed on the lower substrate 6.

In FIG. 1, the upper substrate 2 and the lower substrate 6 are spaced apart by the partition 14 and arranged in parallel. The high frequency electrode 4 supplies a high frequency voltage, and the data electrode 8 supplies a data voltage. The scan electrode 12 supplies a scan voltage and serves as a counter electrode of the high frequency electrode 4, that is, a ground electrode. The high frequency electrode 4 and the scan electrode 12 are arranged in parallel, and the data electrode 8 is arranged in the direction orthogonal to the scan electrode 12. A first dielectric layer 10 is disposed between the data electrode 8 and the scan electrode 12 for insulation and charge accumulation. The second dielectric layer 13 is disposed on the first dielectric layer 10 having the scan electrode 12 formed thereon to protect the scan electrode 12 and accumulate charge. The partition wall 14 is formed in a lattice structure in which all directions are blocked to block optical interference between discharge cells. In this case, the partition wall 14 has an increased height than the conventional low frequency AC type for smooth high frequency discharge between the high frequency electrode 4 and the scan electrode 12. On the surface of the partition wall 14, a phosphor 16 for generating visible light of red, green or blue color is applied. Discharge gas is filled in the discharge space provided by the upper and lower substrates 2 and 6 and the partition wall 14.

In the high frequency PDP discharge cell having such a structure, as shown in FIG. 2, an address discharge occurs due to the difference between the scan voltage (-Vs) and the data voltage (Vd) applied to each of the scan electrode 12 and the address electrode 8. As a result, charged particles are produced. Subsequently, high frequency discharge is initiated and maintained by the center particles Vc (ie, the ground voltage) of the high frequency voltage supplied to the high frequency electrode 4 and the scan electrode 12 and by the charged particles. The high frequency discharge is stopped by the erase voltage Ve supplied to the scan electrode 12.

However, when the high frequency voltage is continuously supplied as shown in FIG. 2, not only the interference and noise problems caused by the high frequency voltage are generated, but also the incorrect discharge is generated by the high frequency voltage. For this reason, the method of switching a high frequency signal and supplying only during a high frequency discharge period is used. In this case, the charged particles generated by the address discharge are formed and maintained as wall charges by the time required for the address period. However, the high frequency PDP has a problem that false discharge is likely to occur as the wall charges of the entire panel have a nonuniformity due to the small amount of wall charges and the different address time.

Referring to FIG. 3, an overall electrode arrangement diagram of a high frequency PDP constituting the discharge cell shown in FIG. 1 is shown.

In FIG. 3, the high frequency PDP includes data electrode lines X1 to Xm disposed corresponding to each column line, and scan electrode lines Y1 to parallel to each row line. Yn) and high frequency electrode lines RF. The discharge cell 34 is provided at each intersection of the data electrode lines X1 to Xm, the scan electrode lines Y1 to Yn, and the high frequency electrode lines RF.

FIG. 4 illustrates voltage waveforms supplied to respective electrode lines during an arbitrary subfield SFi when the PDP shown in FIG. 3 is driven by the ADS method.

During the address discharge period of FIG. 4, the scan voltage Vs is supplied to each of the scan electrode lines Y1 to Yn in line order, and data is transferred to the data electrode lines X1 to Xm in synchronization with the scan voltage Vs. Supply of the voltage Vd causes selective address discharge. Wall charges are accumulated in the discharge cells in which the address discharge is generated and are maintained for the address discharge period. Subsequently, high frequency voltage is commonly applied to the high frequency electrode RF so that high frequency discharge is started and maintained in the discharge cells in which the wall charge is formed. This high frequency discharge is stopped by turning off the high frequency voltage supply.

In the address period, however, a relatively long time is required as the entire panel needs to be scanned. Accordingly, the wall charge formed by the address of the first scan line decreases with time, which is inevitably different from the wall charge amount formed by the address of the last scan line. Due to the nonuniformity of the wall charges in the address period, there is a problem that the image quality is distorted because a difference occurs in the amount of light emitted during the next high frequency discharge. In particular, in the high-frequency PDP, the distance between the data electrode and the scan electrode for the address is extremely limited to about 1/10 as compared to the PDP of the conventional AC method, as shown in the discharge cell shown in FIG. 1, and the wall charge forming space is extremely small. For this reason, the high frequency PDP has more serious nonuniformity of wall charges due to a relatively long address period, causing problems such as mis-discharge.

Accordingly, it is an object of the present invention to provide a PDP address method which makes it possible to compensate for wall charge quantity nonuniformity in an address period.

In order to achieve the above objects, the PDP address method according to the present invention is characterized in that the address discharge is generated by different scanning order for each bit.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5A to 8.

5A to 5D illustrate an address order in bits, that is, in subfields, in the high frequency PDP address method according to an exemplary embodiment of the present invention.

In the PDP address method of the present invention, the wall charge quantity nonuniformity in the address period can be compensated by changing the address order according to the subfields. For example, in the address period of the first subfield SF1 corresponding to bit 0 of the 8-bit data, the address is sequentially scanned from the first scan line to the nth scan line as shown in FIG. 5A. In the address period of the second subfield SF2 corresponding to bit 1, alternately scanning from the beginning and the end of the panel as shown in FIG. 5B as the first, nth, second, n-1th, etc. Will be addressed. Next, the third subfield SF3 corresponding to bit 2 is addressed while scanning in a direction opposite to the address order of the first subfield SF1. In the address period of the fourth subfield SF4 corresponding to bit 3, the address is scanned while scanning in the opposite direction to the address order of the second subfield SF2. In the fifth to eighth subfields SF5 to SF8 corresponding to each of the bits 4 to 7, the address order of the above four cases is repeated. Accordingly, the unevenness of the wall charges generated in the address period of each subfield is compensated for by changing the address order in the next subfield, thereby preventing the screen distortion.

FIG. 6 illustrates driving waveforms supplied to the high frequency PDP illustrated in FIG. 3 in correspondence with the address order of the first subfield SF1 illustrated in FIG. 5A.

In FIG. 6, the scan signal is sequentially supplied from the first scan electrode line Y1 to the nth scan electrode line Yn during the address period, and the data electrode lines X1 to Xm are synchronized with the scan voltage Vs. By supplying the data voltage Vd, selective address discharge occurs. Wall charges are accumulated in the discharge cells in which the address discharge is generated and are maintained for the address discharge period. Subsequently, a high frequency discharge is started by activating charged particles by alternately supplying a plurality of triggering voltages Vt to the scan electrode lines Y1 to Yn and the data electrode lines X1 to Xm at the starting point between the discharge holding periods. To be possible. By the plurality of triggering voltages Vt, the nonuniformity in the amount of wall charges caused by the difference in discharge time in the address period can be made to be uniform to some extent. Activated charged particles are subjected to high frequency discharge by a high frequency voltage commonly supplied to the high frequency electrode lines RF and a high frequency center voltage Vc supplied to the scan electrode lines Y1 to Yn, so that the high frequency PDP displays an image. Done. The high frequency discharge is stopped by turning off the high frequency voltage supply.

FIG. 7 illustrates driving waveforms supplied to the high frequency PDP illustrated in FIG. 3 in correspondence with the address order of the second subfield SF2 illustrated in FIG. 5B.

In FIG. 7, the first scan electrode line Y1, the nth scan electrode line Yn, the second scan electrode line Y2, the n−1 th scan electrode line Yn-1, and the like during the address period are shown in FIG. 7. The scan voltage (-Vs) is alternately supplied from the beginning and the end of the panel and the data voltage (Vd) is supplied to the data electrode lines (X1 to Xm) in synchronization with the scan voltage (-Vs). Address discharge occurs. Wall charges are accumulated in the discharge cells in which the address discharge is generated and are maintained for the address discharge period. In the discharge sustain period, the high frequency discharge is started and maintained by the triggering voltage Vt and the high frequency voltage as described above.

FIG. 8 illustrates driving waveforms supplied to the high frequency PDP shown in FIG. 3 in correspondence with the address order of the third subfield SF3 shown in FIG. 5C.

In FIG. 8, scan signals are sequentially supplied from the nth scan electrode line Yn to the first scan electrode line Yn during the address period, and the data electrode lines X1 to Xm are synchronized with the scan voltage Vs. By supplying the data voltage Vd, selective address discharge occurs. Wall charges are accumulated in the discharge cells in which the address discharge is generated and are maintained for the address discharge period. Subsequently, in the discharge sustain period, as described above, the high frequency discharge is started and maintained by the triggering voltage Vt and the high frequency voltage.

FIG. 9 illustrates driving waveforms supplied to the high frequency PDP shown in FIG. 3 corresponding to the address order of the fourth subfield SF4 shown in FIG. 5B.

In Fig. 9, the n / 2th scan electrode line (Yn / 2), the n / 2 + 1th scan electrode line (Yn / 2 + 1), the second scan electrode line (Y2), and n / 2-1 during the address period. As in the order of the first scan electrode line (Yn / 2-1), the scan voltage (-Vs) is alternately supplied from the middle point of the panel to the beginning and the end of the panel, and is synchronized with the scan voltage (-Vs). As a result, the data voltage Vd is supplied to the data electrode lines X1 to Xm to generate a selective address discharge. Wall charges are accumulated in the discharge cells in which the address discharge is generated and are maintained for the address discharge period. In the discharge sustain period, the high frequency discharge is started and maintained by the triggering voltage Vt and the high frequency voltage as described above.

In the fifth to eighth subfields SF5 to SF8, the driving waveforms having the address order as shown in FIGS. 6 to 9 are repeated. In this way, by changing the address order for each subfield, that is, for each bit, the nonuniformity of the wall charges generated in the address period of each subfield can be compensated for in the address period of the next subfield, thereby preventing screen distortion.

As described above, according to the PDP addressing method according to the present invention, it is possible to prevent the screen distortion by changing the address order for each subfield to compensate for the wall charge quantity nonuniformity in the address period. In addition, although the present invention has been described using only the case where the PDP driving method is applied to the high frequency PDP, the same can be applied to the conventional AC PDP.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (2)

In the address method of the plasma display panel, An address discharge method of a plasma display panel, characterized in that address discharge is caused by a different scanning order for each subfield. The method of claim 1, The address of the plasma display panel is divided into a plurality of subfields, and the discharge order is generated by different scanning order for each subfield included in each group, and the scanning order for each subfield is repeated for each group. Way.

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