KR100529806B1 - Resistor of flash memory device and fabricating method therefor - Google Patents

Abstract

A resistance element in a flash memory device and a method of forming the same are provided. According to an aspect of the present invention, a first resistance layer formed on a semiconductor substrate, a second resistance layer formed on the first resistance layer via a first insulating layer, and a second insulating layer on the second resistance layer A resistive element including a formed wiring and connection contacts electrically connecting the resistive layers to the wiring through a second insulating layer is provided. In this case, the connection contacts may be selectively connected to the wiring and the first resistance layer or the second resistance layer, or the connection contacts may be electrically connected in parallel with the first resistance layer and the second resistance layer. By electrically connecting the resistance layer to the wiring, the range of resistance values that the resistance element can implement can be extended to a lower resistance area.

Description

Resistor of flash memory device and method of forming the same {Resistor of flash memory device and fabricating method therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to resistive elements in flash memory devices and methods of forming the same.

Among semiconductor devices, the use of flash memory devices, which are nonvolatile memory devices, is becoming more frequent. In particular, there is a need for an embedded flash memory device. The resistive element required in such a flash memory device is generally implemented using a polysilicon layer.

The resistance of the non-silicided polysilicon exhibits the property of changing the resistance and capacitance according to the bias, and most designers prefer to use it as a resistor. Most of the polysilicon layer for such a resistor uses a polysilicon layer used to implement a gate of a transistor.

1A is a schematic circuit diagram illustrating a resistive element in a typical memory device. FIG. 1B is a schematic cross-sectional view for describing a resistance element in a conventional memory device.

Referring to FIG. 1A, a typical memory device has a circuit configuration in which a resistance element 1 is introduced at a terminal to which Vcc is applied, and a memory cell transistor 2 is electrically connected to another end of the resistance element 1. It is becoming. At this time, Vout is electrically connected to the input terminal of the cell transistor 2. In this case, the resistive element 1 uses a polysilicon layer deposited over the semiconductor substrate to form the gate of the cell transistor 2, so that peripheral circuits other than the cell region in which the transistor 2 is implemented. Patterned in the region (peripherical region).

Referring to FIG. 1B, in the case of a memory device employing a general NMOS transistor, an element isolation region 15 is formed in a semiconductor substrate 10 and an active region of a semiconductor is set in the element isolation region 15. The gate 30 of the transistor via the gate oxide film 20 on the substrate 10 is implemented by forming and patterning a polysilicon layer. In this case, source / drain regions 31 and 35 are implemented in the semiconductor substrate 10 adjacent to the gate 30. First connection contacts 41 and 43 formed by a contact process connected to the source / drain regions 31 and 35, respectively, may be formed between the metal wire 50 and the source / drain regions 31 and 35. It is formed to implement an electrical connection.

At this time, on the semiconductor substrate 10 in the peripheral circuit region, the polysilicon layer deposited for the formation of the gate 30 is patterned so that the resistance pattern 37 is realized, and the resistance pattern 35 provides electrical connection to the resistance. It is connected to the metal wire 50 provided on the interlayer insulating layer 40 by a second connection contact 45, for example, a metal contact, to operate as a resistance element. Such a wiring 50 and connecting contacts 41, 43, 45 allow the circuit as shown in FIG. 1A to be implemented.

However, in the case of foundry compatible technology (FCT), it must be manufactured in compliance with the foundry leading company's electrical target, so that all designers can manufacture products in multiple foundry fabs with one circuit. May be allowed to produce.

In most cases of foundry companies, the parameters related to transistors, which are active devices, and the resistance parameters for conductivity such as metal wiring and contacts are exactly compatible, but the resistance related items due to doping are fab. There are many differences. In fact, even in the same company, the resistance value of the polysilicon layer used as a resistor may vary depending on the fab. As a result, when transferring masks between different fabs, additional resistances can be created or used to recreate the entire mask set.

When migrating from a fab implementing a low resistance polysilicon layer to a fab implementing a high resistance polysilicon layer, this can be compensated for by sufficiently changing the layout, i.e. In order to design with a lower resistance, longer poly resistors must be used, which leaves more room to change the layout, so a partial layout change of one or two layers makes this transition possible. However, when moving a mask of a fab designed to achieve high resistance to a fab having a low resistance, there is not enough free space to change the design, requiring a redesign of the layout of all layers, that is, a total design change.

In the devices shown in FIGS. 1A and 1B, if a 3500 ohm resistor is implemented, a polysilicon layer having a 1 μm line width of about 10 μm should be used if the resistivity determined in the fab is 350 ohm / unit area. do. In this layout-designed circuit, if you move your product to a fab that can achieve a specific resistivity of 240 ohms / unit, you can add a separate mask to the polysilicon layer to be used as a resistor to refresh the doping with an additional ion implantation process, or The layer line should be extended to 14.6 μm. However, in order to increase the existing polysilicon line of 10 μm to 14.6 μm, there is a lack of free area, and thus, the design of all layers needs to be redone.

Therefore, there is a demand for a structure of a resistance element that can be easily changed from a request for a high resistance value to a request for a low resistance value.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a resistive element structure and a method of forming the resistive element of a memory device, which may structurally have a wider range of resistance values.

One aspect of the present invention for achieving the above technical problem, a first resistance layer formed on a semiconductor substrate, a second resistance layer formed on the first resistance layer via a first insulating layer, the second resistance layer A resistive element of a memory device including a wiring formed on a second insulating layer through a second insulating layer and connecting contacts electrically connecting the resistance layers to the wiring through the second insulating layer.

In this case, the connection contacts may be selectively connected to the wiring and the first resistance layer or the second resistance layer, or the connection contacts may be electrically connected in parallel with the first resistance layer and the second resistance layer. The first resistor layer and the second resistor layer may be electrically connected to the wiring.

The first resistance layer or the second resistance layer may be formed of a polysilicon layer.

The second resistive layer may be formed to have a length shorter than the length of the first resistive layer to allow any one of the connection contacts to be selectively connected to the first resistive layer.

Any one of the connection contacts connects the first resistance layer and the wire, and another one of the connection contacts electrically connects the second resistance layer to the wire connected to the first resistance layer. It may be to connect.

One of the connection contacts is a connection contact between the first resistance layer and the second resistance layer at the same time as a butting contact to connect the first resistance layer and the second resistance layer at the same time. Can be.

Another aspect of the present invention for achieving the above technical problem, a first resistance layer formed on a semiconductor substrate, a second resistance layer formed on the first resistance layer via a first insulating layer, the second resistance The connection contacts of the resistance element including a wire formed on the layer via a second insulating layer, and connecting contacts electrically connecting the resistance layers to the wire through the second insulating layer. Selectively connecting the first resistive layer and the second resistive layer to the first resistive layer or the second resistive layer, or the connection contacts to electrically connect the first resistive layer and the second resistive layer in parallel. A resistance element forming method of a memory device which electrically connects to the wiring to change a resistance value of the resistance element is provided.

Another aspect of the present invention for achieving the above technical problem is that a first polysilicon layer for a floating gate of a flash memory cell on a semiconductor substrate is a cell region where the memory cell is to be formed and other regions other than the cell region. Forming an interlayer dielectric layer of the memory cell on the first polysilicon layer; patterning the interlayer dielectric layer and the first polysilicon layer to pattern the interlayer dielectric layer; Forming a resistive layer, forming a second polysilicon layer for the control gate to be introduced onto the floating gate on the interlayer dielectric layer, and patterning the second polysilicon layer to form a portion of the peripheral circuit region. Forming a second resistive layer on the first resistive layer, forming an interlayer insulating layer covering the second resistive layer, and Forming connection contacts penetrating through an interlayer insulating layer and connected to the first or second resistance layer, and selectively connected to the first or second resistance layer through the connection contacts; or Forming a wire electrically connected to the first resistor layer and the second resistor layer such that the first resistor layer and the second resistor layer are electrically connected in parallel. present.

Forming a tunnel oxide film on the semiconductor substrate prior to forming the first polysilicon layer, and preliminary for the floating gate before forming the interlayer dielectric layer on the first polysilicon layer The method may further include patterning the first polysilicon layer in a pattern.

The second polysilicon layer, the interlayer dielectric layer, and the prepatterned first polysilicon layer of the cell region are formed before the forming of the second resistive layer on the first resistive layer by patterning the second polysilicon layer. Patterning sequentially to form the floating gate including the first polysilicon layer and the control gate including the second polysilicon layer.

The method may further include forming a junction in the semiconductor substrate near the control gate and forming a spacer on the sidewall of the control gate before forming the interlayer insulating layer.

The interlayer dielectric layer may include an oxide-nitride-oxide (ONO) layer.

And forming the connection contact such that any one of the connection contacts is simultaneously connected to the first resistance layer and the second resistance layer as a butting contact.

Another aspect of the present invention for achieving the above technical problem, formed by including a first polysilicon layer for the floating gate of the flash memory cell to be formed in the cell region of the semiconductor substrate on the peripheral circuit region of the semiconductor substrate A first resistive layer, a first insulating layer formed on the first resistive layer including an interlayer dielectric layer of the memory cell, and a second polysilicon layer on the first insulating layer for a control gate of the memory cell A memory device including a formed second resistive layer, a wiring formed on the second resistive layer through a second insulating layer, and connecting contacts electrically connecting the resistive layers to the wiring through the second insulating layer. The resistive element of.

The connection contacts may be selectively connected to the wiring and the first resistance layer or the second resistance layer, or the connection contacts may be electrically connected in parallel with the first resistance layer and the second resistance layer. The layer and the second resistance layer may be electrically connected to the wiring.

Any one of the connection contacts connects the first resistance layer and the wire, and another one of the connection contacts electrically connects the second resistance layer to the wire connected to the first resistance layer. It may be to connect.

One of the connection contacts is a connection contact between the first resistance layer and the second resistance layer at the same time as a butting contact to connect the first resistance layer and the second resistance layer at the same time. Can be.

According to the present invention, it is possible to provide a resistive element structure and a method of forming the resistive element of the memory device which can structurally have a wider range of resistance values.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, and should be understood by those skilled in the art. It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2A and 2B are cross-sectional views schematically illustrating a resistive element and a method of manufacturing the same in a flash memory device according to an embodiment of the present invention.

2A and 2B, a resistive element in a flash memory device according to an embodiment of the present invention may include a first resistive layer 311 formed on a semiconductor substrate 100 and the first resistive layer ( A second resistance layer 331 formed on the third insulating layer 250 through the first insulating layer 250, a wiring 500 formed on the second resistance layer 331 via the second insulating layer 400, and It may be configured to include connection contacts 410 and 450 penetrating the second insulating layer and electrically connected to the wiring 500.

In this case, the connection contacts 410 and 450 may be selectively connected to the wiring 500 and the first resistance layer 311 or the second resistance layer 331 or the connection contacts 410 and 450. The first resistor layer 311 and the second resistor layer 331 are electrically connected to the wiring so that the first resistor layer 311 and the second resistor layer 331 are electrically connected in parallel. It may be.

In this case, the second resistance layer 331 is formed to have a length shorter than the length of the first resistance layer 311 so that any one of the connection contacts 410 and 450 of the connection contacts 410 is the first resistance layer. Selectively connect to the 311 and allow the other connection contact 450 to be connected to the second resistance layer 331.

In this case, as shown in FIG. 2B, the connection contacts 410 and 450 may be formed to connect the resistance layers 311 and 331 and the wiring 500, respectively, but are not shown butting contact. The first and second resistive layers 311 and 331 may be formed to be in contact with one connection contact at the same time.

When the resistive element is configured as described above, the connection contacts 410 and 450 may be selectively connected to the wiring 500 and the first resistive layer 311 or the second resistive layer 331, or The first and second resistive layers 311 and 311 may be electrically connected to each other in parallel with the first and second resistive layers 311 and 331. 331 may be electrically connected to the wiring 500. Accordingly, if necessary, some or all of the connection contacts 410 and 450 may be omitted or present, that is, the first or / and second resistance layers 311 and 331 may be used as a single resistor. Alternatively, it is possible to implement a change in the resistance value by allowing it to be used in parallel.

On the other hand, the resistive layers 311 and 331 of the structure arranged in such a parallel state are formed on the peripheral circuit region as shown in FIG. 2B on the semiconductor substrate 100, which is shown in FIG. 2A of the semiconductor substrate 100. A first polysilicon layer for gates of a flash memory device, such as a floating gate 310 or / and a control gate 330, formed on a cell region as described above or / And a second polysilicon layer.

Specifically, the device isolation region 150 is formed on the semiconductor substrate 100 by STI technology, and the memory cell forms the first polysilicon layer for the floating gate of the flash memory cell on the semiconductor substrate 100. It is formed to extend on the cell region to be and the peripheral circuit region other than the cell region.

In this case, a process of forming a tunnel oxide layer 210 on the semiconductor substrate 100 may be performed before forming the first polysilicon layer. In addition, a preliminary pattern for the floating gate is formed on the first polysilicon layer before the interlayer dielectric layer 250 formed of an oxide nitride (ONO) layer is formed between the floating gate 310 and the control gate 330. In order to implement the first polysilicon layer may be patterned.

The interlayer dielectric layer 250 is formed on the preliminarily patterned first polysilicon layer, and the interlayer dielectric layer 250 extending to the peripheral circuit region may include the first resistive layer 311 and the second resistive layer 331. It may be used as the first insulating layer 250 therebetween.

Afterwards, the interlayer dielectric layer 250 and the first polysilicon layer are patterned to form a first resistive layer 311 in the peripheral circuit region.

In addition, a second polysilicon layer is formed on the interlayer dielectric layer 250 for the control gate 330 to be introduced on the floating gate 310. After that, the second polysilicon layer is patterned to form a second resistive layer 331 on the first resistive layer 311 of the peripheral circuit region. In this case, the second polysilicon layer and the interlayer dielectric layer 250 of the cell region are formed before the forming of the second resistive layer 331 on the first resistive layer 311 by patterning the second polysilicon layer. The patterned first polysilicon layer is sequentially patterned to form a control gate 330 including the floating gate 310 including the first polysilicon layer and the second polysilicon layer.

Thereafter, an interlayer insulating layer 400 covering the second resistance layer 331 is formed. Prior to forming the interlayer insulating layer 400, sidewalls of junctions such as source / drain regions 301 and 305 and control gates 330, and the like, are formed in the semiconductor substrate 100 near the control gate 330. Spacers (not shown) may be formed in the spacers.

After that, contact holes 410 and 450 are formed through the interlayer insulating layer 400 and connected to the first resistive layer 311 or the second resistive layer 331, and a contact hole is formed. It forms by forming a conductive layer which fills a gap, planarization of a conductive layer, etc.

Is selectively connected to the first resistive layer 311 or the second resistive layer 331 through the connection contacts 410 and 450, or the first resistive layer 311 and the second resistive layer 331 are electrically parallel to each other. A wire 500 electrically connected to the first resistive layer 311 and the second resistive layer 331 is formed through a metal layer deposition and patterning process.

As described above, in the process of forming the polysilicon layers for the floating gate 310 and the control gate 330 during the flash memory device manufacturing process, a parallel stacked structure of the first and second resistor layers 311 and 331 may be implemented. . Accordingly, the selective formation of the connection contacts 410 and 450 enables the resistance values required for the device to be implemented over a wider range.

For example, if only the first resistance layer 311 is connected to the wiring 500, that is, only the first connection contact 410 is formed and the second connection contact 450 is not formed, so that the second resistance layer 331 is formed. ), The resistance implemented can thus be approximately 600 ohm / unit area to 1000 ohm / unit area. That is, a relatively high resistance region may be realized by using only the first polysilicon layer constituting the first resistance layer 311.

By the way, for example, if only the first resistance layer 311 can implement a resistance of approximately 800ohm / unit area, and only the second resistance layer 331 can implement a resistance of approximately 350ohm / unit area, as shown in Figure 2b As described above, when both of the connection contacts 410 and 450 are formed to connect the first and second resistance layers 311 and 331 in parallel, the total resistance is (350 × 800) / (350 + 800). A low resistance value of approximately 244 ohms / unit area is achieved. That is, the resistance can be lowered. Thus, when moving production to another fab, a slight layout modification can overcome the differences in resistance values implemented for each fab.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, it is possible to further extend the range of resistance values that can be realized in the resistance element, thereby facilitating such low resistance values by the selective formation of connection contacts even when a very low resistance value range is required. Can be implemented.

FIG. 1A is a schematic circuit diagram illustrating a resistive element in a typical memory element.

FIG. 1B is a schematic cross-sectional view for describing a resistance element in a conventional memory device.

2A and 2B are cross-sectional views schematically illustrating a resistive element and a method of forming the same in a flash memory device according to an embodiment of the present invention.

Claims (15)

A first resistive layer formed on the semiconductor substrate; A second resistance layer formed on the first resistance layer via a first insulating layer; A wiring formed on the second resistance layer via a second insulating layer; And Connecting contacts electrically connecting the resistor layers to the wiring through the second insulating layer; The connection contacts may be selectively connected to the wiring and the first resistance layer or the second resistance layer, or the connection contacts may be electrically connected in parallel with the first resistance layer and the second resistance layer. And a layer and the second resistive layer are electrically connected to the wiring. The method of claim 1, The resistor of claim 1, wherein the first resistor layer or the second resistor layer is formed of a polysilicon layer. The method of claim 1, The second resistive layer is formed to have a length shorter than the length of the first resistive layer to allow any one of the connection contacts to be selectively connected to the first resistive layer. . The method of claim 1, Any one of the connection contacts connects the first resistance layer and the wire, and another one of the connection contacts electrically connects the second resistance layer to the wire connected to the first resistance layer. A resistance element of the memory device, characterized in that for connecting. The method of claim 1, Any one of the connection contacts is simultaneously connected as a butting contact to the first resistance layer and the second resistance layer to simultaneously connect the wire between the first resistance layer and the second resistance layer. A resistive element of a memory device. A first resistive layer formed on the semiconductor substrate; A second resistance layer formed on the first resistance layer via a first insulating layer; A wiring formed on the second resistance layer via a second insulating layer; And A connection element for connecting the resistor layers to the wiring through the second insulating layer. The first connecting portion to be selectively connected to the wiring and the first resistive layer or the second resistive layer, or the connecting contacts to be electrically connected in parallel with the first resistive layer and the second resistive layer. And electrically connecting the resistive layer and the second resistive layer to the wiring to change the resistance of the resistive element. Forming a first polysilicon layer for a floating gate of a flash memory cell on a semiconductor substrate so as to extend on a cell region where the memory cell is to be formed and a peripheral circuit region that is other than the cell region; Forming an interlayer dielectric layer of the memory cell on the first polysilicon layer; Patterning the interlayer dielectric layer and the first polysilicon layer to form a first resistive layer of the peripheral circuit region; Forming a second polysilicon layer on the interlayer dielectric layer for the control gate to be introduced on the floating gate; Patterning the second polysilicon layer to form a second resistive layer on the first resistive layer in the peripheral circuit region; Forming an interlayer insulating layer covering the second resistance layer; Forming connection contacts penetrating the interlayer insulating layer and connected to the first resistive layer or the second resistive layer; And The first resistive layer and the second resistor selectively connected to the first resistive layer or the second resistive layer through the connection contacts or to electrically connect the first resistive layer and the second resistive layer in parallel; Forming a wiring electrically connected to the layer. The method of claim 7, wherein Forming a tunnel oxide film on the semiconductor substrate prior to forming the first polysilicon layer; And patterning the first polysilicon layer in a preliminary pattern for the floating gate prior to forming the interlayer dielectric layer on the first polysilicon layer. The method of claim 8, The second polysilicon layer, the interlayer dielectric layer, and the prepatterned first polysilicon layer of the cell region are formed before the forming of the second resistive layer on the first resistive layer by patterning the second polysilicon layer. And patterning sequentially to form the floating gate including the first polysilicon layer and the control gate including the second polysilicon layer. The method of claim 9, And forming a junction in the semiconductor substrate near the control gate and a spacer on the sidewall of the control gate prior to forming the interlayer insulating layer. Forming method. The method of claim 7, wherein And the interlayer dielectric layer comprises an oxide-nitride-oxide (ONO) layer. The method of claim 7, wherein Forming the connection contact such that any one of the connection contacts is simultaneously connected to the first and second resistance layers as a butting contact. A first resistive layer formed on a peripheral circuit region of a semiconductor substrate, the first resistive layer including a first polysilicon layer for a floating gate of a flash memory cell to be formed in a cell region of the semiconductor substrate; A first insulating layer formed on the first resistance layer, including an interlayer dielectric layer of the memory cell; A second resistor layer formed on the first insulating layer, the second resistor layer including a second polysilicon layer for a control gate of the memory cell; A wiring formed on the second resistance layer via a second insulating layer; And Connecting contacts electrically connecting the resistor layers to the wiring through the second insulating layer; The connection contacts may be selectively connected to the wiring and the first resistance layer or the second resistance layer, or the connection contacts may be electrically connected in parallel with the first resistance layer and the second resistance layer. And a layer and the second resistive layer are electrically connected to the wiring. The method of claim 13, Any one of the connection contacts connects the first resistance layer and the wire, and another one of the connection contacts electrically connects the second resistance layer to the wire connected to the first resistance layer. A resistance element of the memory device, characterized in that for connecting. The method of claim 13, Any one of the connection contacts is simultaneously connected as a butting contact to the first resistance layer and the second resistance layer to simultaneously connect the wire between the first resistance layer and the second resistance layer. A resistive element of a memory device.