KR100524979B1 - Clock signal generating system and method thereof - Google Patents

Abstract

Disclosed are a clock signal generator and a method thereof. The clock signal generating apparatus according to the present invention sets an initial value of a control bit of (m + n) bits, and the LSB is connected to the MSB in response to an area signal indicating whether the DCO clock signal is equal to, or faster or slower than, the reference clock signal. SAR controller that adjusts each bit of control bit in order, DCO to generate DCO clock signal with oscillation frequency corresponding to control bit, counts DCO clock signal using internal i-bit counter, and input data A counter value that outputs the counter value at the time as a sample counter value. The value obtained by counting the DCO clock signal by the counter value sample unit based on the current sample counter value and the current sample counter value. Each area is divided into an area with a slower frequency and a lower area with the same frequency.If the next sample counter value is input, the next sample counter value And a FAST / SLOW determination unit for outputting an area signal indicating whether the signal belongs to a certain area, and each time the USB data is input, while determining whether the current DCO clock signal DCO_CLK is faster or slower than the reference clock signal. Control bits for adjusting the frequency of the DCO clock signal DCO_CLK are sequentially adjusted one bit at a time. Therefore, the required DCO clock signal DCO_CLK can be easily recovered without using a high speed clock signal as in the related art.

Description

Clock signal generating device and method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating apparatus, and more particularly, a clock required for data transmission from data in which a function that does not receive a clock signal from a host, such as a USB smart card, in a full speed USB serial communication system A clock signal generating device for recovering a signal, and a method thereof.

A typical smart card operates by receiving a clock signal through a card reader, but a USB smart card does not receive a clock signal because the host is a PC, not a reader. In other words, the USB communication protocol is a serial data communication using only DATA (D +, D-) lines. Therefore, the USB smart card needs to restore the 12 MHz ± 0.25% clock specified in Specification 1.1 through the received USB data.

On the other hand, like the other packet communication, the USB communication protocol, before transmitting a signal to the host, a function (Function or slave), such as a smart card, there is a section for receiving the signal. As such, if there is a clock signal having a speed of more than twice the data transmission rate during the data receiving section (RX), the correct data can be recovered. During this section, the correct clock for transmitting and receiving the data is recovered to correct the data rate. You can send data with. In addition, since the clock signal for data transmission is restored at each time in the continuously existing RX section, the transmission clock can be controlled so as not to be sensitive to various environmental changes.

1 is a connection diagram of a host PC and a smart card used in USB communication.

As shown in FIG. 1, data is transmitted and received via DP and DM in the USB communication protocol, and a reset signal is generated. If a circuit that functions as a USB function is applied to a system other than a smart card, there is no problem because a typical system has an accurate crystal oscillator clock. However, since a smart card generally provides a clock reader, a clock must be generated inside the smart card to communicate with a system that does not provide a clock, such as USB communication shown in FIG. 1. do. In other words, if the smart card is in Rx (Receiving) mode in USB communication, the data can be received by over sampling without using the correct clock, but in the case of TX (Transmission), the correct clock is used. Data must be transmitted at the transmission rate.

The specification specified in the USB protocol 1.1 specification shall transfer data at 1.5MHz ± 1.5% when USB is low speed, and at 12MHz ± 0.25% when full speed. Must be transmitted. In terms of time, it should have 666.6ns ± 10ns at low speed and 83.3ns ± 200ps at full speed. As shown in the above specification, USB full speed communication requires a much more accurate clock than low speed communication.

 In the USB protocol, when a function is first contacted with a host, there is a control transfer interval between the host and the function that sends initial data to endpoint0, which is the setup phase, the data phase. It is divided into data phase and handshake phase. Here, only the simple concept will be described, except for the detailed description of the USB protocol.

2 shows transmission and reception of a setup phase among the three phases described above. The host starts sending an SOF token, sending a setup token and a setup data packet. Since this is necessarily data sent by the host to a function such as a smart card, the function is an RX section. Also, as shown in FIG. 3, even when data is input / output in a bulk transfer period, the function FUNCTION receives a token packet (IN PACKET, OUT PACKET) from the host. As the host is the master, the IN PACKET, OUT PACKET, and SOF PACKET must be transmitted before any transaction starts. Therefore, the function always has RX first, and the data is received using the data received in this RX section. Restore the clock signal for transmission.

4 is a diagram illustrating a conventional clock recovery technique used for low speed communication in a full speed protocol. In this method, RXDD4 and RXDD8 signals are generated by using the 8-bit sync pattern and the first 1 bit of the setup token before the set-up token, and sampled to generate a clock of ± 1.5% error.

FIG. 5 is a diagram illustrating a general ring oscillator. The clock cycle of the ring oscillator illustrated in FIG. 5 is 2 (7d + 2 * d / 2) = 16d. Here, d is a delay time of the inverter forming the ring oscillator. Using this ring oscillator, designing it for 50MHz will oscillate to 50MHz ± 30%. Using this as the clock signal CLKOSC of FIG. 4, sampling is performed during the RXDD4 and RXDD8 periods, and the number of samples divided by 8 is used as a clock. In other words, assuming that the oscillator actually oscillates at 50 MHz and has a 20 ns period, the interval of RXDD8 is 5332 ns, so it is sampled 266 times. When divided by 8, one clock period is 33 clocks of the clock signal CLKOSC, 660ns. In this case, since the sampling may be 265 when the phase is out of phase, it is necessary to determine the maximum number of sampling using the FL1, FL2, and FL3 signals in FIG. If the oscillation frequency is 50MHz-30%, it is 35MHz. In this case, 186 times are sampled, so dividing by 8 will give 23 clocks of clock signal CLKOSC, that is, 599.4ns. If the oscillation frequency is 50MHz + 30%, it is 65MHz, so if you use the above method, it will be sampled 346 times, so dividing by 8 will give 43 clocks of clock signal CLKOSC, that is, 661.3ns. As a result, the error range is within ± 10ns, so it is realized within ± 1.5%. However, this method cannot be implemented within ± 200 ps (specification 1.1 specification: 12 MHz ± 0.25%) that satisfies the full speed, which makes it difficult to apply the full speed.

In order to apply the conventional clock recovery technique at full speed, a very high frequency clock signal (CLKOSC) is required and high speed logic is required. In addition, most of the existing PC peripherals are low speed, so there is almost no clock generator for high speed. Therefore, there is a need for a clock signal generating apparatus that satisfies full speed and falls within an error range so as to be suitable for a smart card.

The present invention has been made in an effort to provide a clock signal generating apparatus and method for satisfying a full speed and falling within an error range so as to be suitable for a USB smart card in a USB communication system.

Another object of the present invention is to provide a recording medium in which the clock signal generation method is recorded by program code executable by a computer.

In order to achieve the above object, during the receiving period of the input data, to restore the DCO clock signal synchronized with the reference clock signal required for data transmission, and to restore the DCO clock signal in the communication device for transmitting data using the restored DCO clock signal The clock signal generator according to the present invention sets an initial value of a control bit of (m + n) bits, and responds to the MSB in response to an area signal indicating whether the DCO clock signal is equal to, or faster or slower than, the reference clock signal. The SAR control unit adjusts each bit of the control bit in the order of LSB, the DCO generating a DCO clock signal having an oscillation frequency corresponding to the control bit, and counts the DCO clock signal using an internal i-bit counter. A counter value sample based on a counter value sample section for outputting a counter value at the time of transition as a sample counter value and the current sample counter value The DCO clock signal is divided into FAST areas where the DCO clock signal has a higher frequency than the reference clock signal, SLOW area where the frequency is slower, and normal areas with the same frequency.The next sample counter value is entered when the next sample counter value is input. It is preferable to include a FAST / SLOW determination section which outputs an area signal indicating which area belongs to.

In order to achieve the above object, a method of generating a DCO clock signal synchronized with a target reference clock signal by adjusting the internal delay time of the DCO, the initializing the control bit, the DCO clock having a frequency corresponding to the set control bit In step (a), the signal is counted using an i-bit counter, and a count value when the input data transitions is generated as the current sample count value. Is the DCO clock signal the same frequency as the reference clock signal using the current sample count value? Step (b) of determining whether a bit is a fast bit or a slow bit, and determining a pseudo bit of a control bit according to the determination result, wherein the area indicating whether the DCO clock signal is the same frequency as the reference clock signal, is fast or slow, using the current sample count value. Step (c) of setting, randomly setting the remaining bits of the control bit again, the frequency corresponding to the set control bits The DCO clock signal having the DCO clock signal is counted using an i-bit counter, and the current sample generated in the steps (d) and (d) generates a count value when the input data transitions as a current sample count value. It is determined whether the count value belongs to one of the areas set in step (c), and it is determined whether the DCO clock signal is the same frequency as the reference clock signal, fast or slow, and according to the determination result, bits of the next control bit are determined. In step (e), it is determined whether the determination is completed to the least significant bit of the control bit. If there are bits of the control bit that have not yet been determined, repeat steps (d) to (g) to determine all the bits of the control bit. (G) step of outputting the DCO clock signal having a frequency corresponding to the step (f) of the completion and the finally determined control bit as a DCO clock signal synchronized with the reference clock signal. It is preferable to include a system.

Hereinafter, a clock signal generator and a method thereof according to the present invention will be described with reference to the accompanying drawings.

6 is a block diagram schematically illustrating an apparatus for generating a clock signal according to the present invention. Referring to FIG. 6, a clock signal generator according to the present invention includes a counter value sample unit 110, a digital control oscillator (DCO) 120, a FAST / SLOW determination unit 140, and a SAR control unit 130. If necessary, the clock-data synchronization unit 100, the N / M filter 150, and the reset controller 160 may be further provided.

Referring to FIG. 6, the SAR controller 130 determines an initial control bit and then, in response to the area signal S1 and the sustain signal S2 output from the N / M filter 150, the MSB to LSB. It adjusts sequentially and generates a control bit (CON_BIT) to output to the DCO (120). Here, the area signal S1 is a signal indicating whether the DCO clock signal DCO_CLK is faster or slower than the reference clock signal, and the SAR controller 130 is currently adjusting the control bit CON_BIT according to the area signal S1. Adjust the beat The holding signal S2 is a signal for controlling the SAR controller 130 so as not to perform bit adjustment in the current adjustment. When the sustain signal S2 is generated, the SAR controller 130 adjusts the bit adjustment of the current adjustment order in response to the next input area signal S1. When the N / M filter 150 is not configured, the SAR controller 130 generates a control bit CON_BIT in response to the area signal S1 output from the FAST / SLOW determination unit 140 to generate the DCO 120. ) Ultimately, the SAR controller 130 causes the DCO clock signal DCO_CLK to become a target reference clock signal. Here, the reference clock signal REF_CLK may be arbitrarily set at a data transfer rate of USB, for example, an integer multiple of 12 Mbps. Hereinafter, for convenience of description, the reference clock signal is 96 MHz, which is 8 times the USB data transfer rate of 12 MHz. The operation of the SAR controller 130 will be described in more detail with reference to FIGS. 8 and 9.

The DCO 120 adjusts an internal delay time according to the control bit CON_BIT and outputs a DCO clock signal DCO_CLK such that the frequency corresponding to the control bit CON_BIT becomes 96 MHz, which is a reference clock signal. DCO 120 will be described in more detail with reference to FIGS. 11 and 12.

The clock-data synchronizing unit 100 synchronizes the input USB data USB DATA with the DCO clock signal DCO_CLK and outputs data synchronized with the DCO clock signal DCO_CLK.

The counter value sample unit 110 repeatedly counts the DCO clock signal DCO_CLK using an internal i-bit counter, and the synchronized USB data is shifted from low logic to high logic or from high logic to low logic. The counter value is output as a sample counter value (SMP_CNT). Substantially, the counter value sample unit 110 outputs a counter value when the USB data USB DATA transitions from low logic to high logic or from high logic to low logic as a sample counter value SMP_CNT. However, if the USB data DATA and the DCO clock signal DCO_CLK are not synchronized, an incorrect sample counter value SMP_CNT may be output. To prevent this, the counter value sample unit 110 outputs the sample counter value SMP_CNT by using the USB data synchronized with the DCO clock signal DCO_CLK by the clock-data synchronization unit 100.

The FAST / SLOW determination unit 140 has a FAST region in which the DCO clock signal DCO_CLK has a faster frequency than the reference clock signal REF_CLK based on the current sample counter value SMP_CNT output from the counter value sample unit 110. The low frequency SLOW region and the normal frequency region having the same frequency are divided, and a signal for the region to which the next sample counter value to be input is output as the region signal S1. 7 (a) to 7 (c) are diagrams for explaining a basic operation concept of the FAST / SLOW determination unit 140. FIG. 7 (a) shows synchronized USB data and FIG. 7 (b) shows a DCO clock. The signal DCO_CLK is shown, and FIG. 7C illustrates a value obtained by counting the DCO clock signal DCO_CLK in the counter value sample unit 110. For example, if the target DCO clock signal DCO_CLK is 96 MHz and the USB data transfer rate is 12 Mbps, the counter value sample unit 110 counts eight DCO clock signals per one bit of USB data. That is, if the frequency of the DCO clock signal (DCO_CLK) is exactly eight times as large as the USB data, the USB data transition occurs for each value obtained by adding 8 clocks to the counted value of the DCO clock signal (DCO_CLK) when the USB data first transitions. do. If the DCO clock signal (DCO_CLK) is faster than 96 MHz, the transition of USB data occurs after 8 clocks, and if the DCO clock signal (DCO_CLK) is slower than 96 MHz, the USB data transition is earlier than 8 clocks. Occurs. In the case of FIG. 7, the first USB data transition occurs when the value of counting the DCO clock signal DCO_CLK is 7 and the next transition occurs when 13 is only 6 clocks. Therefore, the DCO clock signal DCO_CLK is greater than 96 MHz. You can see that it is slow. In this way, the sample counter value counting the DCO clock signal DCO_CLK when the USB data transitions can be used to determine whether the DCO clock signal DCO_CLK is faster or slower than 96 MHz or exactly 96 MHz. In addition, the FAST / SLOW determiner 140 divides the FAST region, the SLOW region, and the normal region based on a sample counter value currently input. Then, it is determined to which area the next input sample counter value belongs, and an area signal S1 indicating whether the current DCO clock signal DCO_CLK is equal to, or faster or slower than the reference clock signal 96 MHz is output. As shown in FIG. 7, when the current sample counter value is 7, the FAST / SLOW determination unit 140 determines that the DCO clock signal DCO_CLK is a normal region at 96 MHz when the next sample counter value is 15. Here, 15 is a value obtained by adding 2 ^i-1 clocks to the current sample counter value and generalizing to n for convenience of description. And i is the number of bits of the counter which counts a DCO clock signal as mentioned above, and it is assumed that i = 4. If the current sample counter value is a value between 8 and 14, that is, a value counted 1 to 7 (= 2 ^i-1 -1) clocks before n, the DCO clock signal DCO_CLK is a SLOW region slower than 96 MHz, and 0 to If the value is 6, that is, a value counted after 1 to 7 (= 2 ^i-1 -1) clocks than n, the DCO clock signal DCO_CLK is divided into FAST regions faster than 96 MHz, respectively. In the case of Figure 7, the next sample counter value is 13, which can be seen that belongs to the SLOW region. Accordingly, the FAST / SLOW determination unit 140 outputs an area signal S1 indicating that the DCO clock signal DCO_CLK is slower than 96 MHz, which is a reference clock signal.

Subsequently, the N / M filter 150 is a filter for increasing the reliability of the control bit ON_BIT, where N represents the number of continuously generated FAST or SLOW region signals S1, and M represents a determination section. For example, when N = 4 and M = 6, the N / M filter 150 performs the FAST (or SLOW) region before the region signal S1 is generated six times from the FAT / SLOW determination unit 140. It is checked whether or not the area signal S1 indicating 4 has appeared four or more times in succession. If the area signal S1 indicating the FAST (or SLOW) area is displayed four or more times before the area signal S1 is generated six times, the current DCO clock signal DCO_CLK is faster (or slower) than the reference clock signal 96 MHz. The control signal CON_BIT is adjusted by outputting the corresponding region signal S1 to the SAR controller 130. That is, even if the area signal S1 indicating the FAST (or SLOW) region appears four times in succession, or the area signal S1 indicating the SLOW (or FAST) appears once in the middle, the area signal S1 is six. Since the area signal S1 indicating the FAST (or SLOW) area appears four or more times before being generated, it is determined that the current DCO clock signal DCO_CLK is faster (or slower) than the reference clock signal 96MHz. However, if the area signal S1 indicating the FAST (or SLOW) region does not appear more than four times before the area signal S1 is generated six times, for example, the area signal S1 indicating the SLOW (or FAST) is generated twice. If it appears as above, it is determined to be an error and the N / M filter 150 outputs the maintenance signal S2 to the SAR control unit 130 so that the SAR control unit 130 does not adjust the current control bit. In this case, the SAR controller 130 does not adjust the control bit CON_BIT in order to be adjusted, and the N / M filter 150 sets the FAST (or SLOW) area before the area signal S1 is generated six times. If the indicated area signal S1 appears four times or more consecutively, it is checked once again, and if it appears normally, the area signal S1 is output to the SAR controller 150 to adjust the control bit CON_BIT. As described above, the DCO clock is determined using the area signal S1 more than a predetermined time without determining the FAST or SLOW of the DCO clock signal DCO_CLK using the one area signal S1 using the N / M filter 150. Since FAST or SLOW of the signal DCO_CLK is determined, reliability can be improved.

The reset control unit 160 finds a DCO clock signal synchronized with the reference clock signal during the USB data receiving period, and resets each part when transmission of the USB data is completed using the DCO clock signal (DCO clock signal) during the next USB receiving period. DCO_CLK).

FIG. 8 is a diagram illustrating an example of a frequency relationship between a control bit CON_BIT and a DCO clock signal DCO_CLK for controlling the DCO 120 in the apparatus of FIG. 6. The slope of the function of the frequency curve of the DCO clock signal DCO_CLK shown in FIG. 8 has a negative value. This is because the DCO 120 is designed such that the frequency of the DCO clock signal DCO_CLK decreases as the value of the control bit CON_BIT increases. If the frequency of the DCO clock signal DCO_CLK increases as the value of the control bit CON_BIT increases, the slope has a positive value.

FIG. 9 is a diagram illustrating an example of a process in which the SAR controller 130 searches for the optimal control bit CON_BIT in the apparatus of FIG. 6.

A method of tracking the control bit CON_BIT by the SAR controller 130 to control the DCO clock signal DCO_CLK to have a frequency of 960 MHz will now be described with reference to FIGS. 8 and 9. Hereinafter, for convenience of description, it is described that the control bit CON_BIT is 3 bits as shown in FIGS. 8 and 9.

First, when the control bit CON_BIT is 011, it is assumed that the DCO clock signal DCO_CLK is 96MHz. The control bit CON_BIT is arbitrarily set to 100 and tracked from the first MSB. In this case, referring to FIG. 9, since the frequency of the DCO clock signal DCO_CLK is slower than 96 MHz, the SAR controller 130 determines that the first MSB of the control bit CON_BIT is zero. Next, in order to find the second MSB, the SAR controller 130 sets the control bit CON_BIT to 010 as shown in FIG. 10. As shown in FIG. 9, in this case, since the frequency of the DCO clock signal DCO_CLK is faster than 96 MHz, the SAR controller 130 determines that the second MSB is 1 in order to be slow. Next, the SAR controller 130 sets 011 to determine the third bit. In this case, since the frequency of the DCO clock signal DCO_CLK is 96 MHz, as illustrated in FIG. Set the control bit (CON_BIT) to 011. As described above, when the DCO clock signal DCO_CLK reaches 960 MHz, the USB data may be mutated at a constant sample count value. If the frequency of the DCO clock signal (DCO_CLK) is tracked in the same way as above, even if the frequency of the DCO clock signal (DCO_CLK) changes with temperature, the frequency is corrected every RX section and used as the TX transmission clock. A clock generation circuit having a transmission rate can be made.

FIG. 10 is a flowchart illustrating a process in which the DCO 120 generates a target reference clock signal according to adjustment of the control bit CON_BIT in FIG. 6.

6 to 10, the operation of the counter value sample unit 110, the DCO 120, the FAST / SLOW determination unit 140, and the SAR control unit 130 will be described. For convenience of description, the counter value sample unit 110 counts the DCO clock signal DCO_CLK using an internal 4-bit counter.

6 to 10, the SAR controller 130 first determines a control bit CON_BIT as 100 as shown in FIGS. 8 and 9 (step 200). The DCO 120 outputs a DCO clock signal DCO_CLK having a frequency corresponding to the control bit CON_BIT 100.

The count value sample unit 110 counts the DCO clock signal DCO_CLK output from the DCO 120 and generates a count value when the inputted synchronized USB data first transitions as the current sample count value (210). step).

The FAST / SLOW determination unit 140 uses the current sample count value output from the count value sample unit 110 to determine whether the current DCO clock signal DCO_CLK is a normal region such as 96 MHz, a FAST region faster than 96 MHz, or 96 MHz. An area setting for applying a slower SLOW area is made (step 220). For example, as described above with reference to FIG. 7, when the current sample counter value is 7, the FAST / SLOW determination unit 140 has a normal DCO clock signal DCO_CLK of 96 MHz when the next sample counter value is 15. If the value is between 8 and 14, the DCO clock signal DCO_CLK may be divided into a SLOW region slower than 96 MHz, and if the value is between 0 and 6, the DCO clock signal DCO_CLK may be divided into a FAST region faster than 96 MHz.

After operation 220, the FAST / SLOW determination unit 140 compares whether the current sample count value of operation 210 is 8 (operation 230).

In operation 230, when the current sample count value is 8, the current DCO clock signal DCO_CLK is close to 96 MHz, and the FAST / SLOW determination unit 140 indicates an area signal S1 indicating that the current sample count value is in a normal region. ) Is output to the SAR controller 130. Then, the SAR controller 130 maintains the first MSB of the control bit CON_BIT 100 initially set in step 200 as '1' (step 240). In contrast, in operation 230, if the current sample count value is not equal to eight, it is determined whether the current sample count value is greater than eight (operation 250).

In operation 250, if the current sample count value is greater than 8, since the current DCO clock signal DCO_CLK is faster than 96 MHz, the FAST / SLOW determiner 140 indicates an area signal indicating that the current sample count value is in the FAST region. (S1) is output to the SAR control unit 130. Then, the SAR controller 130 adjusts the first MSB of the control bit CON_BIT set in step 200 such that the DCO clock signal DCO_CLK is slowed (step 260). In this case, the first bit of the control bit CON_BIT initially set in step 200 is '1'. Therefore, the first MSB cannot be changed so that the frequency of the DCO clock signal DCO_CLK is slower. Keep it at 1 '. On the other hand, in step 230, if the current sample count value is less than 8, since the current DCO clock signal DCO_CLK is slower than 96 MHz, the FAST / SLOW determination unit 140 determines that the current sample count value is in the SLOW region. The area signal S1 indicated is outputted to the SAR controller 130. Then, the SAR controller 130 adjusts the first MSB of the control bit CONT_BIT set in step 200 to speed up the DCO clock signal DCO_CLK (step 270). In this case, the DCO clock signal DCO_CLK may be faster by converting the first MSB of the control bit CON_BIT set in step 200 from '1' to '0'.

As described above, when the first MSB of the control bit CON_BIT is determined, the SAR controller 130 arbitrarily sets the remaining bits of the control bit CON_BIT (step 280). In this case, as in step 240, when the previous DCO clock signal DCO_CLK is close to 96 MHz, the SAR controller 130 maintains the control bit CON_BIT as 100 set in step 200. On the other hand, as in steps 260 and 270, when the DCO clock signal DCO_CLK is in the FAST region or the SLOW region, the SAR controller 130 arbitrarily sets the second MSB to '1'. That is, as in step 260, if the DCO clock signal DCO_CLK is in the FAST region, the SAR controller 130 sets the control bit CON_BIT to 110. On the other hand, as in step 270, if the DCO clock signal DCO_CLK is in the SLOW region, the SAR controller 130 sets the control bit CON_BIT to 010. The DCO 120 outputs a DCO clock signal DCO_CLK having a frequency corresponding to the control bit CON_BIT determined in step 280 of the control bit CON_BIT. Hereinafter, for convenience of description with reference to FIGS. 8 and 9, as in step 260, the DCO clock signal DCO_CLK is in the FAST region, and therefore the SAR controller 130 outputs the control bit CON_BIT of 010. Focus on that.

The count value sample unit 110 counts the DCO clock signal DCO_CLK output from the DCO 120. The count value sample unit 110 generates a count value when the inputted synchronous USB data is transitioned again as a current sample count value and performs FAST / SLOW. Output to the determination unit 140 (step 290).

After operation 290, the FAST / SLOW determination unit 140 determines whether the input current sample count value belongs to a normal region of the region set in operation 220 (operation 300).

In operation 300, when it is determined that the input current sample count value belongs to the normal region, the current DCO clock signal DCO_CLK is close to 96 MHz, and the FAST / SLOW determination unit 140 determines that the current sample count value is in the normal region. The area signal S1 indicating the presence of the signal is output to the SAR controller 130. Then, the SAR controller 130 maintains the second MSB of the control bit CON_BIT 010 initially set in operation 280 as '1' (operation 310). In contrast, in operation 300, if the current sample count value is not in the normal region, it is determined whether the current sample count value is in the FAST region (operation 320).

In operation 320, if the current sample count value is in the FAST region, since the current DCO clock signal DCO_CLK is faster than 96 MHz, the FAST / SLOW determination unit 140 may indicate that the current sample count value is in the FAST region. The signal S1 is output to the SAR controller 130. Then, the SAR controller 130 adjusts the second MSB of the control bit CON_BIT set in step 280 to slow down the DCO clock signal DCO_CLK (step 330). In this case, since the second bit of the control bit CON_BIT initially set in step 280 is '1', the second MSB may not be adjusted so that the frequency of the DCO clock signal DCO_CLK becomes slower by changing the first MSB. Leave at '1'. On the other hand, in step 320, if the current sample count value is in the SLOW region, since the current DCO clock signal DCO_CLK is slower than 96 MHz, the FAST / SLOW determination unit 140 determines that the current sample count value is in the SLOW region. The area signal S1 indicated is outputted to the SAR controller 130. Then, the SAR controller 130 adjusts the second MSB of the control bit CONT_BIT set in step 280 to speed up the DCO clock signal DCO_CLK (step 340). In this case, the DCO clock signal DCO_CLK may be faster by converting the first MSB of the control bit CON_BIT set in operation 280 from '1' to '0'.

After operation 340, the FAST / SLOW determination unit 140 resets the region setting by using the current sample counter value in operation 290 so as to determine which region the sample count value input next belongs. (Step 350). For example, referring to FIG. 7, when the second inputted current sample counter value is 13, the FAST / SLOW determination unit 140 determines that the next inputted sample counter value is 5, the DCO clock signal DCO_CLK. Is 96MHz, 0 ~ 4 and 14 ~ 15, the DCO clock signal (DCO_CLK) is slower than 96MHz. If the value is 6 ~ 12, the DCO clock signal (DCO_CLK) is faster than 96MHz. Each can be divided.

After operation 350, it is determined whether the determination of the control bit CON_BIT is completed (operation 360). When the determination of the control bit CON_BIT is completed, the control bit CON_BIT is determined and there is still a control bit to be determined. In order to determine next MSBs and LSBs, steps 280 to 350 are repeated to sequentially determine remaining MSBs and LSBs. That is, the control bit CON_BIT is composed of the upper n bits and the lower m bits. At this time, the upper n bits are divided into MSBs and the lower m bits are divided into LSBs. Reference will be made to 12 below.

FIG. 11 is a view schematically showing an embodiment of the DCO 120 shown in FIG. 6 and includes inverters 400, 410, 420, switches 460, 470, 480, LSB cells 430, 440, and a NAND gate 450. do.

FIG. 12 is a diagram illustrating an embodiment of an LSB cell shown in FIG. 11.

FIG. 11 controls the on / off of the switches 460, 470, 480 to adjust the frequency of the DCO clock signal DCO_CLK by controlling the on / off of the upper two bits of the control bit CON_CLK. As shown in FIG. 12, the W / L of the LSB cells 430 and 440 is adjusted to finely adjust the frequency of the DCO clock signal DCO_CLK by adjusting the remaining LSBs of the control bit CON_BIT.

For example, if the control bit CON_BIT consists of the upper n bits and the lower m bits, the upper n bits are divided into MSBs and the lower m bits are divided into LSBs. Specifically, FIG. 12 is a case where n = 2, when the switch 460 is turned on by the most significant bit MSB1, the switch 480 is turned on by the next higher bit MSB2, and the delay of the DCO is turned off. The longest time is generated, and the slowest frequency DCO clock signal DCO_CLK is generated. On the other hand, when the switch 460 is turned off by the most significant bit MSB1, the switch 480 is turned off by the next higher bit MSB2 and the switch 470 is turned on, the delay time of the DCO is shortest and the DCO clock of the fastest frequency is present. The signal DCO_CLK is generated. In this way, the MSBs of the control bit (CON_BIT) can be adjusted to adjust the frequency of the delay stage of the DCO.

On the other hand, the LSB cells 430 and 440 adjust the frequency of the DCO clock signal DCO_CLK by adjusting the W / L of the LSB cells 430 and 440 by the LSBs of the lower m bits of the control bit CON_BIT. Specifically, in the case of m = 3 in FIG. 12, the LSB cells 430 and 440 have transistors having different W / L, and the LSB cells 430 and 440 control the on / off of these transistors by 3-bit LSBs. Adjust the delay time of the LSB cell and adjust the frequency of the DCO clock signal DCO_CLK.

As described above, the full-speed USB clock signal generating apparatus and method thereof according to the present invention determine whether the current DCO clock signal DCO_CLK is faster or slower than the reference clock signal whenever the USB data is input. Control bits for adjusting the frequency of the clock signal DCO_CLK are sequentially adjusted one bit at a time. Therefore, the required DCO clock signal DCO_CLK can be easily recovered without using a high speed clock signal as in the related art.

 In addition, since most of the DCO 120 is composed of digital circuits and calculated, an accurate value can be obtained. The analog circuit DCO 120 has a frequency linearity and a tuning range according to the control bit CON_BIT. Regardless, the correct 12MHz ± 0.25% can be restored. Applying such a clock recovery method can be usefully applied not only to USB communication but also to synchronous communication through packet transmission.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, which are also implemented in the form of a carrier wave (for example, transmission over the Internet). It also includes. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the clock signal generating apparatus and method thereof according to the present invention determine whether the current DCO clock signal DCO_CLK is faster or slower than the reference clock signal whenever the USB data is input, while the DCO clock signal DCO_CLK is determined. Control bits to adjust the frequency of each bit in order. Therefore, the required DCO clock signal DCO_CLK can be easily recovered without using a high speed clock signal as in the related art.

1 is a connection diagram of a host PC and a smart card used in USB communication.

2 shows transmission and reception of a setup phase among three phases used in USB communication.

3 is a diagram illustrating input / output of data in a bulk transfer period.

4 is a diagram illustrating a conventional clock recovery technique used for low speed communication in a full speed protocol.

5 is a diagram illustrating a general ring oscillator.

6 is a block diagram schematically illustrating an apparatus for generating a clock signal according to the present invention.

7 (a) to 7 (c) are diagrams for explaining a basic operation concept of the FAST / SLOW determination unit 140.

FIG. 8 is a diagram illustrating an example of a frequency relationship between a control bit CON_BIT and a DCO clock signal DCO_CLK for controlling the DCO 120 in the apparatus of FIG. 6.

FIG. 9 is a diagram illustrating an example of a process in which the SAR controller 130 searches for the optimal control bit CON_BIT in the apparatus of FIG. 6.

FIG. 10 is a flowchart illustrating a process in which the DCO 120 generates a target reference clock signal according to adjustment of the control bit CON_BIT in FIG. 6.

FIG. 11 is a diagram schematically showing an embodiment of the DCO 120 shown in FIG. 6.

FIG. 12 is a diagram illustrating an embodiment of an LSB cell shown in FIG. 11.

Claims (12)

A clock signal generator for restoring the DCO clock signal in a communication device that restores the DCO clock signal synchronized with the reference clock signal required for data transmission and transmits data using the restored DCO clock signal during the reception period of the input data. To An initial value of a control bit of (m + n) bits is set, and each of the control bits in order of LSB to MSB in response to an area signal indicating whether the DCO clock signal is equal to, faster, or slower than the reference clock signal. A SAR controller for adjusting bits; A DCO generating the DCO clock signal having an oscillation frequency corresponding to the control bit; A counter value sample unit for counting the DCO clock signal using an internal i-bit counter and outputting a counter value when the input data transitions as a sample counter value; And The DCO clock signal counts the DCO clock signal based on the current sample counter value, and the DCO clock signal has a faster frequency than the reference clock signal, a SLOW region with a slower frequency, and the same frequency. And a FAST / SLOW determination unit for dividing each area into a normal area and outputting the area signal indicating which area the next sample counter value belongs to when a next sample counter value is input. The method of claim 1, A clock-data synchronizer for synchronizing the input data with the DCO clock signal to provide input data synchronized with the DCO clock signal to the counter value sample unit; And When an area signal is generated between the FAST / SLOW determining unit and the SAR control unit and the area signal representing the same area is generated N or more times before the area signal is generated M (> 0) times from the FAST / SLOW determining unit. And an N / M filter for outputting an area signal generated N (0 <N <M) times or more, and a maintenance signal to the SAR control unit. The SAR control unit maintains the control bit of the current adjustment turn in response to the holding signal without adjusting it, and then adjusts the control bit of the current adjustment turn in response to an area signal input from the N / M filter. Clock signal generator characterized in that. The method according to claim 1 or 2, And a reset control unit for restoring the DCO clock signal synchronized with the reference clock signal during the reception period of the input data and then resetting the respective units before the reception period of the next input data. Generating device. The apparatus of claim 1, wherein the reference clock signal is an integer multiple of a speed at which the input data is transmitted. The apparatus of claim 1, wherein the SAR controller adjusts each bit of the control bit by one bit in order of LSB to the MSB in response to the area signal. The method of claim 1, wherein the DCO is a plurality of delay stages that are connected corresponding to each of the MSBs of the upper n bits of the control bit of (n + m) bits and output the DCO clock signal having a frequency corresponding to the adjusted delay time. ; And The DCO is connected between the plurality of delay stages, and finely adjusts a delay time while adjusting a width / length (W / L) ratio of a cell corresponding to each of LSBs of the lower m bits of the control bit. A clock signal generator comprising a plurality of delay cells for fine-tuning the frequency of the clock signal. In the method for generating a DCO clock signal synchronized with the target reference clock signal by adjusting the internal delay time of the DCO, (a) initializing a control bit, counting a DCO clock signal having a frequency corresponding to the set control bit with an i-bit counter, and generating a count value when the input data transitions as a current sample count value; (b) determining whether the DCO clock signal is the same frequency as the reference clock signal or faster or slower by using the current sample count value, and determining a pseudo bit of the control bit according to a determination result; (c) setting an area indicating whether the DCO clock signal is the same frequency as the reference clock signal, faster or slower using the current sample count value; (d) randomly setting the remaining bits of the control bit again, counting the DCO clock signal using the i-bit counter with a DCO clock signal having a frequency corresponding to the set control bit, and when the input data is transitioned. Generating a count value as a current sample count value; (e) It is determined whether the current sample count value generated in step (d) belongs to one of the areas set in step (c), and whether the DCO clock signal is the same frequency as the reference clock signal or fast or slow. Determining and determining the bits of the control bit in the next order according to the determination result; (f) It is determined whether the determination is completed to the least significant bit of the control bit, and if there are bits of the control bit that have not yet been determined, repeating steps (d) to (g) to determine all the bits of the control bit. Completing; And and (g) outputting a DCO clock signal having a frequency corresponding to a finally determined control bit as a DCO clock signal synchronized with the reference clock signal. The clock signal generation method of claim 7, wherein the input data is data synchronized with the DCO clock signal. The method of claim 7, wherein each step of determining whether the DCO clock signal is the same frequency as the reference clock signal, fast or slow, And if the current sample counter value belongs to the same area at least N (0 &lt; N < M times or more times during the transition of the input data M (&gt; 0) times, determining the corresponding area. The method of claim 7, wherein step (b) (b1) comparing whether the current sample count value is 2 ^i-1 ; (b2) determining that the DCO clock signal is close to the reference clock signal when the current sample count value is 2i ^-1 , and maintaining the most significant bit of the control bit set in the step (a); (b3) If the current sample count value is a value between 0 and 2 ^i-1 -1, it is determined that the DCO clock signal is slower in frequency than the reference clock signal, so that the DCO clock signal is faster than the current frequency. Changing the most significant bit of the control bit set in step (a) so that it is; And (b4) If the current sample count value is a value between (2 ^i-1 +1) and (2 ¹ -1), it is determined that the DCO clock signal is faster in frequency than the reference clock signal, and the DCO clock signal And changing the most significant bit of the control bit set in the step (a) so that is lower than the current frequency. 8. The method of claim 7, wherein the area setting in step (C) is If the value of counting the DCO clock signal is a value counted 1 to 2 ^1-1 -1 clock before n, set to the SLOW region, If the value of counting the DCO clock signal is n, set to the normal region, If the value of counting the DCO clock signal is a value counted after 1 to 2 ^1-1 -1 clock than n, respectively, it is set to the FAST region. Wherein n is a value obtained by adding 2 ¹ clocks to the current sample count value. A recording medium which records the method of claim 7 to 11 as program code executable on a computer.