KR100523647B1 - Method for improving adhesion rate of photo-resist - Google Patents

Method for improving adhesion rate of photo-resist Download PDF

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KR100523647B1
KR100523647B1 KR10-2003-0006923A KR20030006923A KR100523647B1 KR 100523647 B1 KR100523647 B1 KR 100523647B1 KR 20030006923 A KR20030006923 A KR 20030006923A KR 100523647 B1 KR100523647 B1 KR 100523647B1
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photoresist
oxide film
adhesion
etching
concave
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KR10-2003-0006923A
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Korean (ko)
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KR20040070740A (en
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이대근
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동부아남반도체 주식회사
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자 제조시 옥사이드막의 CMP 공정 수행 후, 옥사이드막과 포토레지스트간 접착도를 향상시키는 포토레지스트 접착 개선 방법에 관한 것이다. 즉, 본 발명은 반도체 소자 제조시 층간 절연막 CMP 진행 후 옥사이드막 표면을 요철 형태로 형성시킴으로써, 포토레지스트와 옥사이드막 간의 접착력을 향상시켜 포토레지스트 크랙을 방지시킬 수 있게 된다. The present invention relates to a method for improving adhesion of a photoresist for improving adhesion between an oxide film and a photoresist after performing a CMP process of an oxide film in manufacturing a semiconductor device. That is, according to the present invention, by forming the surface of the oxide film in the form of irregularities after the progress of the interlayer insulating film CMP in manufacturing the semiconductor device, the adhesion between the photoresist and the oxide film can be improved to prevent photoresist cracking.

Description

포토레지스트 접착 개선 방법{METHOD FOR IMPROVING ADHESION RATE OF PHOTO-RESIST}METHOD FOR IMPROVING ADHESION RATE OF PHOTO-RESIST

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 옥사이드(Oxide)막의 CMP(Chemical Mechanical Polishing) 공정 수행 후 포토레지스트(Photo-resist) 증착시 옥사이드막과 포토레지스트간 접착도를 향상시키는 포토레지스트 접착 개선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to improve adhesion between an oxide film and a photoresist when a photoresist is deposited after performing a chemical mechanical polishing (CMP) process of an oxide film. It is about a method.

최근 들어 반도체 집적 회로가 고집적화 됨에 따라 반도체 소자의 크기가 점점 소형화되는 추세에 있으며, 반도체 공정에서 소자의 크기가 작아질수록 미세한 패턴을 구현하기 위해 포토레지스트의 두께 또한 얇아지고 있다.Recently, as semiconductor integrated circuits have been highly integrated, the size of semiconductor devices has become smaller and smaller, and as the size of devices becomes smaller in semiconductor processes, the thickness of the photoresist is also thinned to realize fine patterns.

도 1은 종래 포토레지스트 패턴 형성을 위한 공정 처리 흐름도로서, 상기 도 1을 참조하면, 종래에는 먼저 옥사이드막 상부에 포토레지스트와 웨이퍼 표면의 접착력을 높이기 위한 접착 강화제인 HMDS를 웨이퍼에 도포한다(S100). 이어 옥사이드막 상부에 포토레지스트를 코팅 도포시킨 후(S102), 에지 비드(Edge bead)를 제거하거나 웨이퍼 에지 노광(Wafer edge exposure)을 통해 웨이퍼 에지 부분에 있는 포토레지스트를 제거한다(S104). 그리고 소프트 베이크(Soft bake)를 수행하여 포토레지스트를 경화시켜 접착력을 증가시킨다(S106). 이어 노광(Post exposure bake)(S018) 및 현상(Development)(S110)을 통해 포토레지스트 패턴을 형성시키게 된다.1 is a flowchart illustrating a process for forming a conventional photoresist pattern. Referring to FIG. 1, in the related art, first, an HMDS, which is an adhesion enhancer for increasing adhesion between a photoresist and a wafer surface, is coated on a wafer (S100). ). Subsequently, after the photoresist is coated on the oxide layer (S102), the edge bead is removed or the photoresist on the wafer edge is removed through wafer edge exposure (S104). Then, soft bake is performed to cure the photoresist to increase the adhesion (S106). Subsequently, a photoresist pattern is formed through post exposure bake S018 and development S110.

그러나 상기한 종래 포토레지스트 패턴 형성 방법에서는 일반적으로, 건식 식각전 층간 절연막(Inter Metal Dielectric) CMP 전 패턴을 구현하는 경우에는 게이트 CD(Critical Dimension)가 0.21μm 정도인 소자에서는 IMD 패턴 후, 홀 패턴을 구현하는데 문제가 없지만, 게이트 CD가 0.18μm 정도로 소형화되는 경우에는 포토레지스트의 두께가 0.6μm 정도로 낮아져서 도 2a, 도 2b에서 보여지는 바와 같이 포토레지스트(PR)에 크랙(crack)이 발생하는 문제점이 있었다.However, in the above-described conventional photoresist pattern forming method, when implementing the entire inter-metal dielectric CMP pattern, the hole pattern after the IMD pattern in the device having a gate CD (Critical Dimension) of about 0.21 μm However, when the gate CD is downsized to about 0.18 μm, the thickness of the photoresist decreases to about 0.6 μm so that cracks occur in the photoresist PR as shown in FIGS. 2A and 2B. There was this.

즉, 종래 도 3에서 보여지는 바와 같이 옥사이드(302)의 표면이 매끄러운 상태에서 공정이 진행되는 경우 라인 공정에는 문제가 되지 않으나, 홀 공정의 경우 패턴시 전체면적의 5%정도에만 홀이 불규칙한 간격으로 형성되기 때문에 홀 생성 부위로 스트레스가 집중돼 포토레지스트(306)상에 크랙이 발생하였다.That is, as shown in FIG. 3, when the process is performed in a state where the surface of the oxide 302 is smooth, the process is not a problem in the line process. Since the stress is concentrated to the hole generation site, cracks are generated on the photoresist 306.

따라서, 본 발명의 목적은 옥사이드막의 CMP 공정 수행 후 포토레지스트 증착시 옥사이드막과 포토레지스트간 접착도를 향상시키는 포토레지스트 접착 개선 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a photoresist adhesion improving method for improving adhesion between an oxide film and a photoresist when performing a photoresist deposition after performing the CMP process of the oxide film.

상술한 목적을 달성하기 위한 본 발명은 반도체 소자 제조시 포토레지스트 접착을 개선시키는 방법에 있어서, (a)층간 절연막 증착 형성 후 CMP를 통해 평탄화를 수행하는 단계와; (b)상기 평탄화된 옥사이드막 표면을 RF플라즈마를 사용하여 상기 옥사이드막상 도포될 물질과의 접착력을 향상시키는 요철 형태로 식각시키는 단계와; (c)상기 요철 형태로 형성된 옥사이드막 상부에 포토레지스트를 도포시키는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of improving photoresist adhesion in manufacturing a semiconductor device, the method comprising: (a) performing planarization through CMP after forming an interlayer insulating film deposition; (b) etching the planarized oxide film surface into a concave-convex shape using RF plasma to improve adhesion to the material to be applied on the oxide film; (c) applying a photoresist on the oxide film formed in the concave-convex shape.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.

도 4는 본 발명의 실시 예에 따른 포토레지스트 접착 개선방법을 예시한 공정 단면도이다. 이하 상기 도 4를 참조하여 본 발명의 포토레지스트 접착 개선 공정을 설명하기로 한다.4 is a cross-sectional view illustrating a method of improving photoresist adhesion according to an embodiment of the present invention. Hereinafter, the photoresist adhesion improving process of the present invention will be described with reference to FIG. 4.

먼저 종래에는 전술한 상기 도 3의 설명에서와 같이 옥사이드의 표면이 매끄러운 상태에서 공정이 진행되는 경우 라인 공정에는 문제가 되지 않으나, 홀 공정의 경우 패턴시 전체면적의 5%정도만 홀이 군데 군데 만들어지기 때문에 홀 생성 부위로 스트레스가 집중돼 포토레지스트 크랙이 발생하게 되는 문제점이 있었다.First, when the process proceeds in a state where the surface of the oxide is smooth as in the above description of FIG. 3, the line process is not a problem, but in the case of the hole process, only about 5% of the total area of the pattern is made of holes. There was a problem in that the stress is concentrated to the hole-generating site to cause photoresist cracks.

이에 따라 본 발명에서는 IMD CMP후, 옥사이드 표면을 상기 도 4에서 보여지는 바와 같이 요철 형태(400)로 형성되도록 처리하여 포토레지스트(306)와 옥사이드(302)간 접착력을 개선시킴으로써, 후속 공정에서 포토레지스트(306)가 옥사이드(302) 표면에 잘 접착되도록 하여 상기 도 2a, 도 2b에서와 같은 포토레지스트 크랙이 발생하지 않도록 한다. Accordingly, in the present invention, after the IMD CMP, the oxide surface is treated to be formed into the concave-convex shape 400 as shown in FIG. 4, thereby improving the adhesion between the photoresist 306 and the oxide 302, thereby improving the photoresist in a subsequent process. The resist 306 adheres well to the oxide 302 surface so that photoresist cracks as shown in FIGS. 2A and 2B do not occur.

이때, 상기 옥사이드 표면을 상기 도 4에서와 같이 요철 형태로 형성하는데 있어서는 먼저 RF 플라즈마를 사용하는 경우 300±100W 전압과 100±50mt 압력 상태에서 100±50sccm의 AR가스와 10±5sccm의 CF4 가스를 이용하여 상기 옥사이드막을 30±20초간 200±100Å만큼 수행하여 옥사이드막 표면을 요철 형태로 형성시키며,At this time, in forming the oxide surface in the form of irregularities as shown in FIG. 4, when using RF plasma, 100 ± 50 sccm AR gas and 10 ± 5 sccm CF 4 gas at 300 ± 100 W voltage and 100 ± 50 mt pressure. By using the oxide film is performed by 200 ± 100Å for 30 ± 20 seconds to form an oxide film surface in the form of irregularities,

마이크로 웨이브 소스를 사용하는 경우에는 1000±400W 전압과 1000±550mt 압력 상태에서 3000±15000sccm의 O2가스와 10±5sccm의 C2F6가스를 이용하여 상기 옥사이드막을 250±100℃의 바닥 온도(Bottom Temp)에서 200±100Å만큼 수행하여 옥사이드막 표면을 요철 형태로 형성시키게 된다.In the case of using a microwave source, the oxide film was subjected to a bottom temperature of 250 ± 100 ° C. by using 3000 ± 15000 sccm O 2 gas and 10 ± 5 sccm C 2 F 6 gas at 1000 ± 400 W voltage and 1000 ± 550 mt pressure. Bottom Temp) is performed by 200 ± 100Å to form the surface of the oxide film in the form of irregularities.

한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

이상에서 설명한 바와 같이, 본 발명은 반도체 소자 제조시 층간 절연막 CMP 진행 후 옥사이드막 표면을 요철 형태로 형성시킴으로써, 포토레지스트와 옥사이드막 간의 접착력을 향상시켜 포토레지스트 크랙을 방지시킬 수 있는 이점이 있다. As described above, the present invention has the advantage of preventing the photoresist crack by improving the adhesion between the photoresist and the oxide film by forming an oxide film surface after the progress of the interlayer insulating film CMP during semiconductor device manufacturing.

도 1은 종래 포토레지스트 패턴 형성을 공정 처리 흐름도,1 is a process flow chart of conventional photoresist pattern formation;

도 2a 내지 도 2b는 종래 옥사이드 CMP 후, 포토레지스트 크랙의 발생을 예시한 도면,2a to 2b is a view illustrating the generation of photoresist cracks after the conventional oxide CMP,

도 3은 종래 포토레지스트 접착 방법을 도시한 공정 단면도,3 is a process cross-sectional view showing a conventional photoresist bonding method;

도 4는 본 발명의 실시 예에 따른 포토레지스트 접착 방법을 도시한 공정 단면도.Figure 4 is a cross-sectional view showing a photoresist adhesion method according to an embodiment of the present invention.

Claims (9)

삭제delete 반도체 소자 제조시 포토레지스트 접착을 개선시키는 방법에 있어서,In the method for improving photoresist adhesion in the manufacture of semiconductor devices, (a)층간 절연막 증착 형성 후 CMP를 통해 평탄화를 수행하는 단계와;(a) performing planarization through CMP after the interlayer insulating film deposition is formed; (b)상기 평탄화된 옥사이드막 표면을 RF플라즈마를 사용하여 상기 옥사이드막상 도포될 물질과의 접착력을 향상시키는 요철 형태로 식각시키되, 상기 옥사이드막 식각 시 300±100W 전압과 100±50mt 압력 상태에서 100±50sccm의 AR가스와 10±5sccm의 CF4 가스를 이용하여 식각시키는 단계와;(b) The surface of the planarized oxide film is etched into an uneven shape to improve adhesion to the material to be applied on the oxide film using RF plasma, and the oxide film is etched at a pressure of 300 ± 100W and 100 ± 50mt at 100 ± 50mt. Etching with AR gas of ± 50 sccm and CF 4 gas of 10 ± 5 sccm; (c)상기 요철 형태로 형성된 옥사이드막 상부에 포토레지스트를 도포시키는 단계;를 포함하는 것을 특징으로 하는 포토레지스트 접착 개선 방법.(c) applying a photoresist on the oxide film formed in the concave-convex shape. 제2항에 있어서,The method of claim 2, 상기 옥사이드막 식각은, 30±20초간 200±100Å만큼 수행하는 것을 특징으로 하는 포토레지스트 접착 개선방법.The oxide film etching, photoresist adhesion improvement method characterized in that performed for 30 ± 20 seconds by 200 ± 100 Å. 반도체 소자 제조시 포토레지스트 접착을 개선시키는 방법에 있어서,In the method for improving photoresist adhesion in the manufacture of semiconductor devices, (a)층간 절연막 증착 형성 후 CMP를 통해 평탄화를 수행하는 단계와;(a) performing planarization through CMP after the interlayer insulating film deposition is formed; (b)상기 평탄화된 옥사이드막 표면을 마이크로 웨이브 소스를 사용하여 상기 옥사이드막상 도포될 물질과의 접착력을 향상시키는 요철 형태로 식각시키는 단계와;(b) etching the planarized oxide film surface into a concave-convex shape using a microwave source to improve adhesion to the material to be applied on the oxide film; (c)상기 요철 형태로 형성된 옥사이드막 상부에 포토레지스트를 도포시키는 단계;를 포함하는 것을 특징으로 하는 포토레지스트 접착 개선 방법.(c) applying a photoresist on the oxide film formed in the concave-convex shape; photoresist adhesion improvement method comprising a. 제4항에 있어서,The method of claim 4, wherein 상기 (b)단계에서, 상기 옥사이드막의 식각시에는, 1000±400W 전압과 1000±550mt 압력 상태에서 3000±15000sccm의 O2가스와 10±5sccm의 C2F6가스를 이용하여 식각시키는 것을 특징으로 하는 포토레지스트 접착 개선 방법.In the step (b), when the oxide film is etched, it is etched using 3000 ± 15000sccm O 2 gas and 10 ± 5sccm C 2 F 6 gas at 1000 ± 400W voltage and 1000 ± 550mt pressure Photoresist adhesion improvement method. 제5항에 있어서,The method of claim 5, 상기 옥사이드막 식각은, 250±100℃의 바닥 온도에서 200±100Å만큼 수행하는 것을 특징으로 하는 포토레지스트 접착 개선 방법.The oxide film etching, the photoresist adhesion improvement method, characterized in that performed by 200 ± 100Å at a bottom temperature of 250 ± 100 ℃. 반도체 소자 제조시 포토레지스트 접착을 개선시키는 방법에 있어서,In the method for improving photoresist adhesion in the manufacture of semiconductor devices, (a)층간 절연막 증착 형성 후 CMP를 통해 평탄화를 수행하는 단계와;(a) performing planarization through CMP after the interlayer insulating film deposition is formed; (b)상기 평탄화된 옥사이드막 표면을 RF플라즈마를 사용하여 상기 옥사이드막상 도포될 물질과의 접착력을 향상시키는 요철 형태로 식각시되, 상기 요청 식각은 포토레지스트의 두께를 5000±1000Å로 사용하는 홀 공정에서 포토레지스트 패턴 형성 전에 RF 전압원을 이용하여 수행하는 단계와;(b) the surface of the planarized oxide film is etched in an uneven form to improve adhesion to the material to be applied on the oxide film using RF plasma, the request etching is a hole process using a thickness of the photoresist 5000 ± 1000Å Performing an RF voltage source prior to forming the photoresist pattern at; (c)상기 요철 형태로 형성된 옥사이드막 상부에 포토레지스트를 도포시키는 단계;를 포함하는 것을 특징으로 하는 포토레지스트 접착 개선 방법.(c) applying a photoresist on the oxide film formed in the concave-convex shape; photoresist adhesion improvement method comprising a. 제4항에 있어서,The method of claim 4, wherein 상기 (b)단계에서의 옥사이드막의 요철 식각은, 상기 포토레지스트의 두께를 5000±1000Å로 사용하는 홀 공정에서 포토레지스트 패턴 형성 전에 마이크로 웨이브 소스를 이용하여 수행하는 것을 특징으로 하는 포토레지스트 접착 개선방법.The uneven etching of the oxide film in the step (b) is performed by using a microwave source before forming the photoresist pattern in the hole process using the thickness of the photoresist to 5000 ± 1000 Å . 반도체 소자 제조시 포토레지스트 접착을 개선시키는 방법에 있어서,In the method for improving photoresist adhesion in the manufacture of semiconductor devices, (a)층간 절연막 증착 형성 후 CMP를 통해 평탄화를 수행하는 단계와;(a) performing planarization through CMP after the interlayer insulating film deposition is formed; (b)상기 평탄화된 옥사이드막 표면을 RF플라즈마를 사용하여 상기 옥사이드막상 도포되는 나이트 라이드 또는 실리콘 물질과의 접착력을 향상시키는 요철 형태로 식각시키는 단계와;(b) etching the planarized oxide film surface into a concave-convex shape using RF plasma to improve adhesion to the nitride or silicon material applied on the oxide film; (c)상기 요철 형태로 형성된 옥사이드막 상부에 포토레지스트를 도포시키는 단계;를 포함하는 것을 특징으로 하는 포토레지스트 접착 개선 방법.(c) applying a photoresist on the oxide film formed in the concave-convex shape; photoresist adhesion improvement method comprising a.
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