KR100520445B1 - Method for fabricating integrated circuit on both sides of wafer and wafer holder thereof - Google Patents

Method for fabricating integrated circuit on both sides of wafer and wafer holder thereof Download PDF

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KR100520445B1
KR100520445B1 KR1019980055790A KR19980055790A KR100520445B1 KR 100520445 B1 KR100520445 B1 KR 100520445B1 KR 1019980055790 A KR1019980055790 A KR 1019980055790A KR 19980055790 A KR19980055790 A KR 19980055790A KR 100520445 B1 KR100520445 B1 KR 100520445B1
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wafer
sides
integrated circuit
holding tool
forming
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KR20000040215A (en
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유철준
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68792—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

본 발명은 웨이퍼 양쪽 면에 대해서 웨이퍼 처리 공정을 진행하여 웨이퍼 양쪽 면에 집적 회로를 형성하는 방법 및 이에 사용하는 웨이퍼 고정 도구에 관한 것이다. 따라서, 본 발명의 목적은 웨이퍼 양면에 집적 회로를 형성하여 반도체 칩의 크기를 줄이고 수율을 증가시키는데 있다. 이러한 목적을 달성하기 위하여 본 발명은 (1) 양면이 연마된 웨이퍼를 준비하는 단계, (2) 웨이퍼의 제1면에 대해서 웨이퍼 처리 공정을 진행하여 제1면에 집적 회로를 형성하는 단계, (3) 제1면 위에 보호막을 형성하는 단계, (4) 웨이퍼의 제2면에 대해서 웨이퍼 처리 공정을 진행하여 제2면에 집적 회로를 형성하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법과, (1) 양면이 연마된 웨이퍼를 준비하는 단계, (2) 웨이퍼의 양면에 대해서 동시에 웨이퍼 처리 공정을 진행하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법 및 웨이퍼의 가장자리를 고정시키기 위한 접지면, 진공 흡착구, 회전축을 구비하는 것을 특징으로 하는 웨이퍼 고정 도구를 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an integrated circuit on both sides of a wafer by performing a wafer processing process on both sides of the wafer, and a wafer holding tool for use therein. Accordingly, an object of the present invention is to form integrated circuits on both sides of a wafer to reduce the size of semiconductor chips and increase yields. In order to achieve the above object, the present invention provides a method for manufacturing an integrated circuit on a first surface by (1) preparing a wafer on which both surfaces are polished, (2) performing a wafer processing process on a first surface of a wafer, 3) forming a protective film on the first surface, and (4) forming an integrated circuit on the second surface by performing a wafer processing process on the second surface of the wafer. Method of forming an integrated circuit on both sides of the wafer, characterized in that for forming a wafer, (1) preparing a wafer polished on both sides, (2) simultaneously processing the wafer on both sides of the wafer Provided is a wafer holding tool comprising a ground plane, a vacuum suction port, and a rotating shaft for securing an edge.

Description

웨이퍼 양면에 집적 회로를 형성하는 방법 및 이에 사용하는 웨이퍼 고정 도구{Method for fabricating integrated circuit on both sides of wafer and wafer holder thereof}Method for fabricating integrated circuit on both sides of wafer and wafer holder etc}

본 발명은 웨이퍼 양면에 집적 회로를 형성하는 방법 및 이에 사용하는 웨이퍼 고정 도구에 관한 것으로서, 보다 구체적으로는 웨이퍼 양쪽 면에 대해서 웨이퍼 처리 공정을 진행하여 웨이퍼 양쪽 면에 집적 회로를 형성하는 방법 및 이에 사용하는 웨이퍼 고정 도구에 관한 것이다.The present invention relates to a method for forming integrated circuits on both sides of a wafer and a wafer holding tool used therein, and more particularly, to a method of forming integrated circuits on both sides of a wafer by performing a wafer processing process on both sides of a wafer. A wafer holding tool is used.

반도체 소자는 웨이퍼 위에 집적 회로를 형성하여 제조되는데, 웨이퍼 위에 집적 회로를 형성하기 위해서는 광 리소그래피 공정(Photolithographic Process), 산화 공정(Oxidation Process), 확산 공정(Diffusion Process), 이온 주입 공정(Ion Implantation), 금속 배선 공정(Metallization Process) 등의 웨이퍼 처리 공정을 거치게 된다. 그런데, 종래에는 웨이퍼의 한쪽 면에만 집적 회로를 형성하고, 반대쪽 면은 웨이퍼 상태 그대로 사용하였다. 그러나, 반도체 칩의 용량 증가와 함께 반도체 칩의 크기가 커지면서 하나의 웨이퍼에서 얻을 수 있는 반도체 칩의 수율(Yield)이 감소하여 효율이 떨어지게 되었다. 또한, 반도체 칩의 대형화로 인해서 반도체 패키지의 성형에도 많은 제약이 따르게 되었다.Semiconductor devices are fabricated by forming integrated circuits on a wafer. In order to form integrated circuits on a wafer, a photolithographic process, an oxidation process, a diffusion process, and an ion implantation process are formed. And a wafer processing process such as a metallization process. In the past, integrated circuits were formed only on one side of the wafer, and the opposite side was used as it is. However, as the size of the semiconductor chip increases with the increase of the capacity of the semiconductor chip, the yield of the semiconductor chip obtained from one wafer decreases and the efficiency decreases. In addition, due to the large size of the semiconductor chip, there are many restrictions in forming the semiconductor package.

따라서, 본 발명의 목적은 웨이퍼 양면에 집적 회로를 형성하여 반도체 칩의 크기를 줄이고 수율을 증가시키는데 있다.Accordingly, an object of the present invention is to form integrated circuits on both sides of a wafer to reduce the size of semiconductor chips and increase yields.

이러한 목적을 달성하기 위하여 본 발명은 (1) 양면이 연마된 웨이퍼를 준비하는 단계, (2) 웨이퍼의 제1면에 대해서 웨이퍼 처리 공정을 진행하여 제1면에 집적 회로를 형성하는 단계, (3) 제1면 위에 보호막을 형성하는 단계, (4) 웨이퍼의 제2면에 대해서 웨이퍼 처리 공정을 진행하여 제2면에 집적 회로를 형성하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법과, (1) 양면이 연마된 웨이퍼를 준비하는 단계, (2) 웨이퍼의 양면에 대해서 동시에 웨이퍼 처리 공정을 진행하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법 및 웨이퍼의 가장자리를 고정시키기 위한 접지면, 진공 흡착구, 회전축을 구비하는 것을 특징으로 하는 웨이퍼 고정 도구를 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing an integrated circuit on a first surface by (1) preparing a wafer on which both surfaces are polished, (2) performing a wafer processing process on a first surface of a wafer, 3) forming a protective film on the first surface, and (4) forming an integrated circuit on the second surface by performing a wafer processing process on the second surface of the wafer. Method of forming an integrated circuit on both sides of the wafer, characterized in that for forming a wafer, (1) preparing a wafer polished on both sides, (2) simultaneously processing the wafer on both sides of the wafer Provided is a wafer holding tool comprising a ground plane, a vacuum suction port, and a rotating shaft for securing an edge.

이하, 도면을 참조하여 본 발명의 실시예를 상세히 설명하고자 한다. 도면 전반에 걸쳐서 동일한 도면 부호는 동일한 구성 요소를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout.

도 1은 본 발명의 실시예에 따른 웨이퍼 양면에 집적 회로를 형성하는 공정을 나타내는 공정 진행도이다.1 is a process flow diagram illustrating a process of forming integrated circuits on both sides of a wafer according to an embodiment of the present invention.

도 1을 참조하면, 웨이퍼 양면에 집적 회로를 형성하기 위해서는 웨이퍼의 양면이 연마되어 양면 모두 유리면이 형성된 웨이퍼를 준비한다(100). 이러한 웨이퍼의 한쪽 면인 제1면에 광 리소그래피 공정, 산화 공정, 확산 공정, 이온 주입 공정, 금속 배선 공정 등의 웨이퍼 처리 공정을 진행하여 집적 회로를 형성한다(110). 웨이퍼의 제1면에 집적 회로가 형성되면 반대쪽 면인 제2면에 웨이퍼 처리 공정을 진행하는 동안 제1면에 형성된 집적 회로를 보호하기 위해서 제1면 위에 보호막을 형성한다(120).Referring to FIG. 1, in order to form integrated circuits on both sides of a wafer, both sides of the wafer are polished to prepare a wafer on which both surfaces have a glass surface (100). An integrated circuit is formed on the first surface, which is one side of the wafer, by performing a photolithography process, an oxidation process, a diffusion process, an ion implantation process, a metal wiring process, or the like, in a wafer processing process (110). When the integrated circuit is formed on the first surface of the wafer, a protective film is formed on the first surface to protect the integrated circuit formed on the first surface during the wafer processing process on the second surface that is the opposite surface (120).

보호막은 화학 기상 증착 등의 방법으로 형성하는데, 제2면에 대해서 웨이퍼 처리 공정이 진행되는 동안 제1면의 집적 회로를 보호하기 위해서는 내열성을 갖는 실리콘 산화막 등으로 형성한다. 제1면에 보호막이 형성되면 제2면에 대해서 웨이퍼 처리 공정을 진행하여 제2면에 집적 회로를 형성한다(130). 이때, 제1면과 제2면 모두 메모리 소자를 형성할 수도 있고, 제1면에는 메모리 소자, 제2면에는 논리 소자(Logic)를 형성한 시스템 칩(System Chip)을 구현할 수도 있다.The protective film is formed by a chemical vapor deposition method or the like, and is formed of a silicon oxide film having heat resistance or the like to protect the integrated circuit on the first surface while the wafer processing process is performed on the second surface. When the protective film is formed on the first surface, a wafer processing process is performed on the second surface to form an integrated circuit on the second surface (130). In this case, both the first and second surfaces may form a memory device, and a system chip including a memory device on a first surface and a logic device on a second surface may be implemented.

제1면과 제2면에 대해서 웨이퍼 처리 공정이 완료되어 반도체 소자가 형성되면 제1면에 입힌 보호막을 제거한다(140). 이때, 보호막 전체를 제거하지 않고 반도체 소자의 접속 단자 역할을 하는 본딩 패드(Bonding Pad) 부분만 선택적으로 제거할 수 있다. 또한, 웨이퍼 양면에 집적 회로를 형성할 때 위와 같이 제1면과 제2면에 대해서 순차적으로 웨이퍼 처리 공정을 진행하지 않고 웨이퍼 양면에 웨이퍼 처리 공정을 동시에 진행하여 집적 회로를 형성할 수도 있다.When the wafer processing process is completed on the first and second surfaces to form a semiconductor device, the protective layer on the first surface is removed (140). In this case, only a portion of the bonding pad serving as a connection terminal of the semiconductor device may be selectively removed without removing the entire protective film. In addition, when the integrated circuit is formed on both surfaces of the wafer, the integrated circuit may be formed by simultaneously performing the wafer processing process on both sides of the wafer without sequentially performing the wafer processing process on the first and second surfaces as described above.

웨이퍼 양면에 대해서 집적 회로를 동시에 형성하기 위해서는 웨이퍼 처리 공정을 진행할 때 공정이 진행되는 분위기에 대해서 웨이퍼 양면이 노출되어야 하므로 특별한 웨이퍼 고정 도구가 필요하다. 아래에서는 이러한 웨이퍼 고정 도구에 대해서 설명한다.In order to simultaneously form integrated circuits on both sides of the wafer, a special wafer holding tool is required because both sides of the wafer must be exposed to the atmosphere in which the process proceeds during the wafer processing process. Hereinafter, such a wafer holding tool will be described.

도 2는 본 발명의 실시예에 따른 상부 웨이퍼 고정 도구를 나타내는 사시도이고, 도 3은 본 발명의 실시예에 따른 웨이퍼 고정 도구가 웨이퍼를 고정시킨 모습을 나타내는 측면도이고, 도 4는 본 발명의 실시예에 따른 웨이퍼 고정 도구가 웨이퍼를 고정시킨 모습을 나타내는 평면도이다.Figure 2 is a perspective view showing an upper wafer holding tool according to an embodiment of the present invention, Figure 3 is a side view showing a state in which the wafer holding tool according to an embodiment of the present invention fixed the wafer, Figure 4 is an embodiment of the present invention It is a top view which shows the state which fixed the wafer by the wafer fixing tool which concerns on an example.

도 2 내지 도 4를 참조하면, 웨이퍼 고정 도구는 웨이퍼(40) 가장자리만을 고정시켜서 웨이퍼(40) 양면에 대해서 동시에 웨이퍼 처리 공정을 진행할 때 웨이퍼(40) 안쪽 부분에 집적 회로가 형성될 수 있다. 웨이퍼 고정 도구는 상부 웨이퍼 고정 도구(10), 하부 웨이퍼 고정 도구(20), 진공 흡착구(12), 회전축(30)으로 구성된다.2 to 4, the wafer holding tool fixes only the edge of the wafer 40 so that an integrated circuit may be formed inside the wafer 40 when the wafer processing process is simultaneously performed on both sides of the wafer 40. The wafer holding tool is composed of an upper wafer holding tool 10, a lower wafer holding tool 20, a vacuum suction hole 12, and a rotating shaft 30.

상부 웨이퍼 고정 도구(10)와 하부 웨이퍼 고정 도구(20)는 동일한 형상이므로 상부 웨이퍼 고정 도구(10)를 위주로 설명한다. 상부 웨이퍼 고정 도구(10)의 고정 도구 몸체(13)에는 진공 흡착구(12)가 형성된다. 고정 도구 몸체(13)는 안쪽에 구멍이 뚫린 고리 형상의 원판으로서, 웨이퍼(40)의 가장자리를 고정시키기 위해서 원판의 평평한 한 면이 웨이퍼(40)의 가장자리와 접하는 접지면(14)이 된다. 고정 도구 몸체(13)의 안쪽에 뚫린 구멍의 지름은 웨이퍼(40)의 지름보다 작은 값을 갖는데, 웨이퍼(40) 상에 집적 회로가 형성된 반도체 소자(15)를 제조하는 수율(Yield)을 고려하여 고정 도구 몸체(13)의 안쪽 지름을 정한다.Since the upper wafer holding tool 10 and the lower wafer holding tool 20 have the same shape, a description will be mainly given of the upper wafer holding tool 10. The vacuum suction hole 12 is formed in the fixing tool body 13 of the upper wafer holding tool 10. The fixing tool body 13 is an annular disk having a hole formed therein, and a flat surface of the disk is a ground plane 14 contacting the edge of the wafer 40 in order to fix the edge of the wafer 40. The diameter of the hole drilled inside the fixing tool body 13 has a smaller value than the diameter of the wafer 40, taking into account the yield of manufacturing the semiconductor device 15 having the integrated circuit formed on the wafer 40. The inner diameter of the fixing tool body (13).

고정 도구 몸체(13)의 접지면(14)에는 다수의 진공 흡착구(12)가 형성되어 진공에 의해서 웨이퍼(40)를 흡착한다. 상부 웨이퍼 고정 도구(10)와 하부 웨이퍼 고정 도구(20)는 각각의 접지면(14) 서로 마주 보며 웨이퍼 양쪽 면의 가장자리를 고정시킨다. 이때, 상부 웨이퍼 고정 도구(10) 또는 하부 웨이퍼 고정 도구(20) 하나만 이용하여 웨이퍼(40)를 고정시킬 수도 있다. 고정 도구 몸체(13)에는 회전축(30)이 결합되어 있어서 회전축(30)을 회전시킬 수 있는 외부 장치(도시되지 않음)에 의해서 웨이퍼(40)의 양면을 뒤집을 수 있다. 회전축(30)은 상부 웨이퍼 고정 도구(10)와 하부 웨이퍼 고정 도구(20)에 동시에 결합되거나, 어느 하나에만 결합된다.A plurality of vacuum suction holes 12 are formed in the ground plane 14 of the fixing tool body 13 to suck the wafer 40 by vacuum. The upper wafer holding tool 10 and the lower wafer holding tool 20 hold the edges of both sides of the wafer facing each ground surface 14. In this case, the wafer 40 may be fixed using only the upper wafer holding tool 10 or the lower wafer holding tool 20. The rotating tool 30 is coupled to the fixed tool body 13 to flip both sides of the wafer 40 by an external device (not shown) capable of rotating the rotating shaft 30. The rotating shaft 30 is coupled to the upper wafer holding tool 10 and the lower wafer holding tool 20 at the same time or to only one.

이상 설명한 바와 같이 본 발명에 의하면, 동일한 기능을 수행하는 반도체 소자를 더 작은 크기의 반도체 칩에 형성할 수 있다.As described above, according to the present invention, a semiconductor device having the same function can be formed on a smaller size semiconductor chip.

또한, 동일한 웨이퍼로 제조할 수 있는 반도체 칩의 수율을 증가시킬 수 있다.It is also possible to increase the yield of semiconductor chips that can be manufactured from the same wafer.

도 1은 본 발명의 실시예에 따른 웨이퍼 양면에 집적 회로를 형성하는 공정을 나타내는 공정 진행도,1 is a process progress diagram illustrating a process of forming integrated circuits on both sides of a wafer according to an embodiment of the present invention;

도 2는 본 발명의 실시예에 따른 상부 웨이퍼 고정 도구를 나타내는 사시도,2 is a perspective view showing an upper wafer holding tool according to an embodiment of the present invention;

도 3은 본 발명의 실시예에 따른 웨이퍼 고정 도구가 웨이퍼를 고정시킨 모습을 나타내는 측면도,3 is a side view illustrating a state in which a wafer fixing tool fixes a wafer according to an embodiment of the present invention;

도 4는 본 발명의 실시예에 따른 웨이퍼 고정 도구가 웨이퍼를 고정시킨 모습을 나타내는 평면도이다.Figure 4 is a plan view showing a state in which the wafer holding tool fixed the wafer in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 설명>Description of the main parts of the drawing

10; 상부 웨이퍼 고정 도구 12; 진공 흡착구10; Upper wafer holding tool 12; Vacuum suction port

13; 고정 도구 몸체 14; 접지면13; Fixed tool body 14; Ground plane

15; 반도체 소자 20; 하부 웨이퍼 고정 도구15; Semiconductor device 20; Lower wafer holding tool

30; 회전축 40; 웨이퍼30; Axis of rotation 40; wafer

100; 웨이퍼 준비 단계 110, 130; 웨이퍼 처리 단계100; Wafer preparation steps 110, 130; Wafer processing steps

120; 보호막 형성 단계 140; 보호막 제거 단계120; Passivation layer forming step 140; Shield removal step

Claims (5)

웨이퍼 양면에 집적 회로를 형성하는 방법에 있어서,In a method for forming integrated circuits on both sides of a wafer, (1) 양면이 연마된 웨이퍼를 준비하는 단계와,(1) preparing a wafer with both surfaces polished, (2) 상기 웨이퍼의 제1면에 대해서 웨이퍼 처리 공정을 진행하여 상기 제1면에 집적 회로를 형성하는 단계와,(2) performing a wafer processing process on the first surface of the wafer to form an integrated circuit on the first surface; (3) 상기 제1면 위에 보호막을 형성하는 단계와,(3) forming a protective film on the first surface; (4) 상기 웨이퍼의 제2면에 대해서 웨이퍼 처리 공정을 진행하여 상기 제2면에 집적 회로를 형성하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법.(4) forming an integrated circuit on both sides of the wafer, by performing a wafer processing process on the second surface of the wafer to form an integrated circuit on the second surface. 제 1항에 있어서, 상기 웨이퍼 양면에 집적 회로를 형성하는 방법은The method of claim 1, wherein the integrated circuit is formed on both sides of the wafer. (5) 상기 보호막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법.(5) A method for forming integrated circuits on both sides of a wafer, further comprising removing the protective film. 제 1항에 있어서, 상기 보호막은 내열성을 갖는 것을 특징으로 하는 웨이퍼 양면에 집적 회로를 형성하는 방법.The method of claim 1, wherein the passivation layer has heat resistance. 웨이퍼 고정 도구에 있어서,In the wafer holding tool, (1) 상기 웨이퍼의 가장자리를 고정시키기 위해서 평평한 접지면과 상기 웨이퍼의 지름보다 작은 안쪽 지름을 갖는 고리 형상의 고정 도구 몸체와,(1) an annular fixing tool body having a flat ground plane and an inner diameter smaller than the diameter of the wafer to fix the edge of the wafer, (2) 상기 접지면에 형성되는 복수 개의 진공 흡착구와,(2) a plurality of vacuum suction ports formed on the ground plane, (3) 상기 고정 도구 몸체에 부착되는 회전축을 포함하는 것을 특징으로 하는 웨이퍼 고정 도구.(3) a wafer holding tool comprising a rotating shaft attached to the holding tool body. 제 4항에 있어서, 상기 웨이퍼 고정 도구는 동일한 형상의 두 개의 상기 고정 도구 몸체가 각각의 상기 접지면이 서로 마주 보며 상기 웨이퍼의 양쪽 면 가장자리를 고정시키는 것을 특징으로 하는 웨이퍼 고정 도구.The wafer holding tool of claim 4, wherein the two holding tool bodies of the same shape hold edges on both sides of the wafer with their respective ground planes facing each other.
KR1019980055790A 1998-12-17 1998-12-17 Method for fabricating integrated circuit on both sides of wafer and wafer holder thereof KR100520445B1 (en)

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