KR100517257B1 - Memory array test circuit and method - Google Patents

Abstract

Circuitry for testing the memory cell array 100 is provided. This circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a fault signal output line 108. The shift register 110 includes a plurality of latches, a clock signal input 114, and an output line 116 and is connected to a fault signal output line of the test circuit. This circuit includes a tri-state output buffer driver 118, which includes a data input line, a fault signal input line, and a data output line. The fault signal line of the buffer driver is connected to the output line of the shift register 110. When detecting a defective memory cell in the array, the test circuit generates a fault signal on the fault signal output line 116 of the test circuit. Next, a fault signal is sent to the shift register causing the buffer driver 118 to enter a high impedance state in response to the fault signal. The shift register 110 includes a different number of latches depending on the desired latency of the system or test equipment using the test circuit.

Description

Memory Array Test Circuit {MEMORY ARRAY TEST CIRCUIT AND METHOD}

TECHNICAL FIELD The present invention relates to memory integrated circuits, and more particularly, to dynamic random access memory integrated circuits.

Dynamic random access memory is used in computers and other electronic machines that require temporary storage of data. These circuits have advantages over other types of memory circuits in that they provide the highest memory cell density, low relative cost per bit of stored data, and relatively high speed for a given area of semiconductor. DRAM has grown in both size and speed to meet the needs of system designers using modern microprocessors with clock speeds above 100 MHz. In fact, with each new generation of DRAM, the number of memory cells on the integrated circuit increases by four times. In an effort to accommodate systems that require more and faster data, the industry has turned to DRAM that synchronizes data transfer, address, and control signals with clock signals.

Tie the function of the memory to an external clock is desirable to speed up data transfers and synchronize data inputs and outputs, but the complexity and size of the circuits that must be accessed to store or retrieve data in the DRAMs make the memory circuits This makes it difficult to respond to every cycle of the clock. The solution to this problem is to delay the memory operation by a given number of cycles, but eventually have a memory that stores or retrieves data on the clock cycle as desired by the system designer. This delay in synchronous DRAM is called "latency". It is a common design practice that the latency of a memory circuit is selectable by the system designer, for example, by one, two, or three clock cycles, depending on the operating frequency of the microprocessor on which the computer system is based.

DRAM stores information in cell arrays of addressable rows and columns. During the manufacture of these devices, one or more defects may occur or interfere with proper operation of the memory circuit. Defects may be randomly distributed. Defects of this type can be analyzed and corrected on the circuit die, while for other defects the circuit must be destroyed. Testing of the memory circuit to find these defects can represent a significant share of the final cost of the device, and the problem becomes complicated as the capacity of the memory circuit increases. Thus, the industry must make a significant effort to create an efficient technique for testing these circuits.

Traditional test methods write known information such as, for example, a fully high value to a completely low value in a memory cell array, so that if the output of the cell is different from the known fully high value or completely low value written in the cell, It is characterized by comparing the data read from the cells in such a way that the difference is detected. In this two-state test method, the test data output is high or low, one indicating that all cell data is the same, and the other indicating that at least one cell has generated other data. The problem with this two-state approach is that some kind of defect pattern may not be found. For example, if the test data written into the array were all 1 (high) and the data read from the array were all 0 (low), this simple two-state comparator approach would be " Will pass. " In other words, this simple two-state approach only notices the differences in the data. If all the data is wrong, it will pass if all the data is the same.

The test techniques described later have been developed to minimize this pattern sensitivity. See "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Model" by M. Kumanoya et al., IEEE J. of Solid-State Circuits, vol. SC-20, no. 5, Oct. 1985. In this initial three-state approach, the same data (both high or low) was written into the memory cell array. Next, a plurality of data bits are sampled from the array and given to AND logic designed to output a high signal if all inputs are high and output a low signal if all inputs are low. If all data is the same, as in a two-state, it is either high or low, and the memory cell is passed and considered to be free of defects. However, if one bit is different, the output of the AND logic is in high-impedance state. Thus, this approach can detect not only conventional single cell defects but also pattern defects that are not detected in a simple two-state technique, such as when an entire zero is generated by an array when an entire one should be generated.

Synchronous DRAM complicates the testing procedure in that after the test mode is triggered, the system, microprocessor, or test device expects test data to be output after a certain number of cycles have elapsed. Uncertainty in the timing of the test data output can incorrectly indicate a fault, resulting in passing the memory producing the faulty data. There is a need in the industry for how to implement latency control in test circuits.

According to a first preferred embodiment of the present invention, a circuit for testing a memory cell array is disclosed. The circuit includes a test circuit coupled to the array and includes a data output line and a fault signal output line. A shift register including a plurality of latches, a clock signal input, and an output line are connected to the defect signal output line of the test signal. The circuit includes a three-state output buffer driver, which includes a data input line, a fault signal input line, and a data output line. The fault signal line of the buffer driver is connected to the output line of the shift register. Upon detecting a defective memory cell in the array, the test circuit outputs a fault signal on the fault signal output line of the test circuit. Next, a fault signal is sent to the shift register to cause the buffer driver to be in high impedance in response to the fault signal. The shift register includes a number of latches depending on the desired latency variability of the test equipment using the system or test circuit. By using two latches in the shift register, nothing is driven for one cycle of latency, one latch for two cycles of latency, and two latches for three cycles of latency. For example, latency of 1, 2, or 3 cycles can be achieved.

The advantage of the circuit is that the test results of the memory cell array can be synchronized through appropriate selection of latency such that they appear at the output of the test circuit when expected by the system or test equipment including the memory cell array.

1 is a generalized block diagram of a first embodiment of the present invention. The diagram shows a design for a test circuit for the memory cell array 100. The test circuit is typically located on the very semiconductor die from which the memory cell array is fabricated. As part of the testing of the array, data is written into the array (typically all high (logical 1) or all low (logical 0)) in a particular pattern. Data is read from array 100 via line 102 to line 106. Comparator circuit 104 compresses data on line 106. Line 108 carries a 3-state fault signal from the comparator when one of the bits read from array 100 differs from the expected value (either all 1's or 0's). Shift register block 110 controls the latency in the data path, while shift register 112 controls the latency in the three-state path. The shift register operates in conjunction with the clock signal on line 114. Those skilled in the art will appreciate that other types of programmable delay circuits may be used in place of the shift registers to implement latency. An example of such a circuit is shown in FIG. 20. After the data in the data path and the three-state path undergo the desired latency periods in the shift registers 110 and 112, respectively, the data is sent along the line 116 to the output circuit block 118. Output circuit block 118 includes circuitry for disabling data output when a 3-state fault signal is output from shift register 112 along line 120.

FIG. 2 is a timing diagram showing the function of the circuit shown in FIG. Line a is the clock signal on line 114 of FIG. A read command is given on line b to clock data out of the array on line 102. Line c is the data to be read from the array. Line d is the output of comparator circuit block 104. Line e represents a 3-state fault signal on line 108 of the circuit of FIG. Line f is the output of shift register 110 on line 116 (one cycle delayed, ie the latency period is "1" for this timing diagram). Line g is the output of shift register 112 and is also delayed by one cycle. The output of the output circuit block 118 is shown in line h, where the effect of the three-state fault signal is on disabling the data stream sent to the output circuit block 118 along the line 116. It becomes clear by By holding the three-state fault signal in the shift register 112 for the desired latency period, the circuit ensures that the system or test equipment prepares for the disabled output when the signal is transmitted. If for some reason the output is disabled by the 3-state fault signal when it is not when expected by the system or test equipment, the fault may not be detected.

Line h of FIG. 2 shows that the output of the test circuit is at an intermediate voltage level when the output is disabled by the delayed three-state fault signal “T” on line g of FIG. 2. The intermediate voltage is achieved by adding as a load a circuit having a relatively small time constant as shown in FIG. 19 at the output of the circuit block 118. The circuit of FIG. 19 makes the output of the buffer driver (for example shown in FIG. 18) to an intermediate voltage of approximately 1.4 volts when a fault signal "T" appears at the input of the buffer driver. Load circuits with small time constants preferably allow their output to achieve intermediate levels in one cycle.

A more detailed description of the test method will be given below with reference to 64Mb synchronous DRAM. Those skilled in the art will appreciate that the method is equally applicable to other memory configurations and capacities than described. The test method described herein includes two modes of a simple two-state test operation as well as a three-state test operation.

3 is a simplified block diagram illustrating each of the three test modes. The memory array is divided into eight sections. Each of the main amplifiers 300 provides data bits from a particular cell within one of eight sections. Only four main amplifier blocks 300 are shown in FIG. 3. However, it should be understood that the circuit is duplicated for the remaining four sections of the memory array. During a read operation in test mode, data in main amplifier 300 is sent to comparator circuit 302 along line MOTJ 301. The comparator circuit 302 is the same for all three modes of operation of the test operation, namely the rapid three-state test, the full three-state laser probe test, and the simple two-state test. The three-state laser probe test is represented by circuit 304 in FIG. 3. The quick three-state test is indicated by circuit 306. And, a simple two-state test is represented by circuit 308. No matter which test circuit is selected by the user, the test output is sent to an IDOLT circuit block 310 that includes a shift register that produces the desired latency. Next, the data goes to the DDOC circuit 312, which puts the three-state output buffer into high impedance if the fault signal DOCKB is output by one of the three-state test modes 304 or 306. If no fault signal is generated by the circuit 304 or 306, or if a two-state test circuit 308 is used, the [line TCMP ( Output buffer is enabled to transfer the data on [309]. It is to be understood that the circuit shown herein is a dedicated test circuit in parallel with the operating circuit of the memory array. By using this parallel approach, no signal delay is introduced in the data path used for normal operation of the memory circuit.

FIG. 4 is a more detailed view of the comparator circuit shown in elements 304, 306, and 308 of FIG. 3, showing only half of the test circuit for eight sections of memory cells comprising the entire 64 Mb array. Each of lines 400, 402, 404, and 406 refers to eight data lines from the main amplifier of the four sections of the memory cell array described above with reference to FIG. These lines correspond to the line MOTJ 301 of FIG. Block 410 is the first stage for data comparison on MOT lines 400, 402, 404, and 406. The circuit including block 410 shown above is common to all three test mode circuits. The circuit appearing after block 410 is divided into two three-state test modes, a laser probe test circuit and a rapid test circuit. Circuitry for a simple two-stage test is included in each three-state test circuit as will be clearly explained later.

Block 420 is a dedicated circuit for testing laser probes, while block 430 is a quick test dedicated circuit. These tests are similar except that the rapid test circuit compresses data from block 410 with less circuitry than that performed in the laser test circuit. This difference becomes apparent when comparing the number of lines 432 entering each block 430 with the number of input lines 422 to block 420. Regardless of which test circuit comparator the user uses, the output of each circuit is coupled to output line 440, which includes both 3-state line TRIS0 and data line TCMP0. These outputs are compared and sent to IDOLT 310 and DDOC 312 shown in FIG. 3 for latency implementation and disabling of data at fault detection. Selection of the two-state test circuit is made by providing a suitable signal on line 450, referred to as "T2ST". Line 452, referred to as " TPRW ", controls power to the fast test circuit 430 to power off to save power when the memory circuit is not in test mode.

5 is a schematic diagram of block 410 shown in FIG. Line 500 is one of the sets of lines 400, 402, 404, and 406 shown in FIG. 4. Eight data lines, including line 500, are sent to true data circuit block 510 and its complementary, or complementary, or bar, data circuit block 520. Dividing the data into raw data and complementary data provides redundancy for the test, resulting in a more robust testing procedure than when only the raw data is compared and tested.

6 is a schematic diagram of the original data circuit block 510 shown in FIG. The data on four lines 610 is compressed into a single bit of data on output line 612 corresponding to one of the complementary data lines 512 of FIG. 5. Similarly, FIG. 7 is a schematic diagram of the complementary data circuit block 520 shown in FIG. The data on four lines 710 is compressed into a single bit of data on output line 712 corresponding to one of the complementary data lines 512 of FIG. 5. The logic circuit of FIG. 7 outputs the complement of the data on line 612 on output line 712. This, of course, assumes that all data on lines 610 and 710 are the same. This is typical of array testing. If one of the lines contains other data, the fact will be detected in subsequent circuitry, so that a defect in the memory array will be indicated to the system or test equipment.

8 is a schematic diagram of one of the laser test circuit blocks 420 shown in FIG. The raw data from block 410 enters original data circuit block 830 and the complementary data block from block 410 enters complementary data block 840 via line 822. The output of block 830 is then sent along line 832 to three-state fault signal driver circuit block 850 and two-state signal driver circuit block 870. The output of block 840 is sent along line 840 to three-state fault signal driver circuit block 850, three-state data driver circuit block 860, and two-state signal driver circuit block 870. . The signal on line 852 controls which of the three-state test circuits in blocks 850 and 860 will be used, or whether the simple two-state circuit in block 870 will be used. Line 862 is a three-state fault signal output, while line 864 is a data output. TPTLSN line 854 allows driver circuits 850, 860, and 870 to be turned off to save power when the memory circuit is not in test mode.

9 is a schematic diagram of the logic circuit of blocks 830 and 840 shown in FIG. Data input on line 922 is simply compressed using NOR gate 924 and inverter 926. Output line 928 corresponds to lines 832 and 842 of FIG. 8.

10 is a schematic diagram of the three-state fault signal driver circuit block of FIG. 8. Input 1022 corresponds to circle and complementary data lines 832 and 842 of FIG. The signal is compressed into one signal by the NAND gate 1024 whose output is the input of the driver buffer 1030. Driver buffer 1030 is disabled by appropriate signals on lines T2ST 1040 and TPT 1041 to generate logic 1 at node N1 and turn off transistors MP1 and MN1. This function is used, for example, if the system or test equipment wants a simple two-state test mode and an appropriate signal is placed on line 1040 to disable driver buffer 1030. It will be appreciated that when output driver buffer 1030 is enabled, it produces the inverse of the signal on line 1026 on line 1032.

FIG. 11 is a schematic diagram of the three-state data driver circuit block 860 shown in FIG. Line 1142 corresponds to line 842 of FIG. 8. The buffer driver 1130 functions in the same manner as the driver 1030 described above.

12 is a schematic diagram of the two-state signal driver circuit block 870 of FIG. 8. Lines 1232 and 1242 correspond to lines 832 and 842 respectively. Block 1250 is an exclusive OR gate that compresses the signals on lines 1232 and 1242 into a single signal that is the input of buffer driver 1260. The buffer driver 1260 functions similarly to the drivers 1030 and 1130.

FIG. 13 is a schematic diagram of one of the quick test circuit blocks 430 shown in FIG. 4. Line 1332 corresponds to line 432 of FIG. 4. Logic circuit block 1340 compresses the signals on the four raw data input lines and the signals on the four complementary data input lines into a single raw data output and a single complementary data output on lines 1342 and 1352, respectively. Lines 1342 and 1352 lead to three-state fault signal driver circuit block 1350 and two-state signal driver circuit block 1370. Line 1352, i.e., the complementary data line, also goes to the 3-state data driver circuit block 1360. The signal on line 1362 controls whether one of the three-state test circuits in blocks 1350 and 1360 will be used, or whether the simple two-state circuit in block 1370 will be used. Line 1372 carries the read / write test signal, which shuts off power to the driver circuit block when the memory circuit is not in test mode. Line 1382 is a three-state fault signal output, while line 1348 is a data output. The 3-state fault signal driver circuit block 1350, the 3-state data signal driver block 1360, and the simple 2-state circuit block 1370 are the blocks 850 described above with reference to Figures 10, 11, and 12, respectively. , 860, and 870).

14 is a schematic diagram of the logic circuit block 1340 of FIG. Line 1432 corresponds to line 1332 of FIG. 13, and line 1442 corresponds to line 1342 or 1352.

Referring back to FIG. 4, the TRIS0 and TRIS1 three-state signal lines 440 are further compressed by the NAND gate. The signal is then inverted. The NAND gate is shown as element 305 in FIG. 3 and the inverter is shown as element 307. These elements are shown as appearing at the outputs of both the laser probe test circuit 304 and the rapid test circuit 306, which is shown in FIG. 4, which is a schematic of the actual circuit, on the line 440 which is common in a three-state circuit. Because they are combined. After exiting the inverter 307, the three-state signal enters the circuit described in FIG.

FIG. 15 is a schematic diagram of the IDOLT shift register block 310 shown in FIG. 3. The circuit of FIG. 15 allows the user or system to select the latency of one, two or three clock cycles to ensure that the three-state fault signal generation is synchronized when the system or test equipment expects such a signal. Two latches 1502 and 1504. Line 1500 corresponds to the output of inverter 307 of FIG. 3. The operation of latch 1502 or 1504 is controlled by the edge of the system clock signal. The system turns on first latch 1502 by sending a pulse on line 1510 that is synchronized with the edge of the clock signal. The latch 1504 is controlled by pulses from the circuit of FIG. 16 entering the circuit of FIG. 15 on lines 1520 referred to as MOEJB and MOEJ. Line 1512 carries a signal that bounds the latch for incoming data.

The latency of one cycle is achieved by turning off both latches 1502 and 1504 to allow data to flow through it. Due to the delay cycles involved in extracting data from the array, the latency is 1 and not 0. Two cycles of latency are achieved by turning off the first latch 1502 and keeping the second latch 1504 off while allowing data to flow through it. Turning on the first latch results in storing the 3-state fault signal for one extra cycle or for a total of two cycles. Turning on both latches results in storing a 3-state fault signal for two extra cycles or for three cycles. Once the three-state fault signal is stored for the desired latency period, the signal is sent to the output enable circuit shown in FIG.

16 is a schematic diagram of a circuit for generating a signal MOEJB and a MOEJ that turns on the second latch 1504. System signals for implementing three cycles of latency are carried on line 1602 and the operation of latch 1504 is synchronized by the clock signal on line 1604.

FIG. 17 is the DDOC circuit block 312 of FIG. 3. The 3-state fault signal enters the circuit along line 1702. Two three-state fault signal lines 1702 are shown because the memory circuit has two outputs. One is for each half of the memory array dedicated to this test mode. The three-state fault signal travels along line 1704 to NOR gate 1710 and then to inverter 1712.

The output of the DDOC circuit shown in FIG. 17 is the DOCKB signal shown in FIG. Upon detection of a defect in the memory array, a three-state fault signal, i.e., a DOCKB signal, is generated by the circuit of FIG. 17 to disable data output from the memory circuit as described with reference to the timing diagram of FIG. . Disabling the output is accomplished by putting the three-state output buffer (shown in FIG. 18) into a high impedance state. The DOCKB signal generated by the circuit of FIG. 17 is a triggering signal on line 1802 that places buffer 1800 in high impedance state. In the absence of a DOCKB signal, that is, when no memory cell fault is detected, the DOCKB signal is in a state that does not activate the high impedance state of the 3-state output buffer 1800. Next, the output buffer 1800 outputs the data retrieved from the array (typically all 1s or 0s) and is compressed by the comparator circuit described with reference to FIGS. Data from the comparator circuit enters the buffer on line 1804 and exits after being inverted on line 1806. That is, if the comparator circuit produces a "pass", the output circuit generates a high or low signal depending on the data loaded into the test array. If the comparator circuit produces a "fault", the output circuit generates a "high impedance" state. In other words, unlike a high or low pass state, it is "3-state" or floating (no current draw or current source). The output indicates that a pass data or fault signal is expected by the system or test equipment. 15 is synchronized by the latency control circuit of FIG. 15 to appear at the output.

FIG. 19 is a load circuit for the output of the buffer driver (eg, line 1806 of FIG. 18) that forces the output to a specific voltage when the buffer driver is in a three-state or high impedance state. The load circuit is typically off-chip in test equipment, but may alternatively be located on the die where the memory circuit is fabricated. The load depends on the time constant that determines, in particular, how quickly the circuit can respond to the voltage on the line 1900, but can take many forms. The output of the buffer driver is connected to line 1900. The desired voltage of the high impedance buffer driver is located at node 1902. Typical intermediate voltage on node 1902 is 1.4 volts. Resistor 1904 and capacitor 1906 are selected to exhibit the desired load characteristics and time constant. For example, resistor 1904 may be approximately 50 ohms, while capacitor 1906 may be approximately 50 kohms. This selection of device values allows the load circuit to force the output of the buffer driver to intermediate voltage levels even within the fastest clock cycles used in modern fast microprocessors.

20 is an example of a programmable delay circuit that can be used to implement a latency cycle without using the shift register described above. Data is read from position 0 to position 7 in the sequence indicated by circuit block 2000. Circuit block 2000 may include a counter or other decoder circuit to select a sequence for driving pass transistor 2002 to pass data to output node 2004. By simply including a counter in circuit block 2000 to continuously release data from position 0 to position 7, the circuit of FIG. 20 can be made to operate as a shift register. These operations can be synchronized by inputting a clock signal to the circuit block 2000. Other types of programmable delay circuits include multiplexers and demultiplexers that allow sequencing of data transmissions.

Although the present invention has been described with reference to exemplary embodiments, this description is not to be understood in a limiting sense. Various modifications and combinations of example embodiments will be apparent to those skilled in the art. For example, the number of latency cycles can be increased by inserting additional latches in the circuit of FIG. 15. In addition, in the embodiment shown in FIG. 1, the programmable delay circuit shown by the shift register 12 may be located between the memory cell array and the comparator, not between the comparator and the output buffer driver as shown. Accordingly, the appended claims include any such modifications and embodiments.

Circuitry is provided that can be synchronized through appropriate selection of latency such that the test results of the memory cell array appear at the output of the test circuit when expected by a system or test equipment including the memory cell array.

1 is a generalized block diagram of a first preferred embodiment circuit.

2 is a timing diagram for the circuit of FIG.

3 is a generalized block diagram illustrating three test circuits.

4 is a schematic diagram of the circuit shown in FIG.

5 is a schematic diagram of the generalized circuit block of FIG.

6 is a detailed view of the generalized circuit block of FIG.

7 is a detailed view of the generalized circuit block of FIG.

8 is a detailed view of the generalized circuit block of FIG.

9-12 are detailed views of the generalized circuit block of FIG.

13 is a detailed view of the generalized circuit block of FIG.

14 is a detailed view of the generalized circuit block of FIG.

15 is a detailed view of the generalized circuit block 310 of FIG.

FIG. 16 is a schematic diagram of a control circuit for the second latch 1504 of FIG. 15.

FIG. 17 is a schematic diagram of the generalized circuit block 312 of FIG. 3.

18 is a schematic diagram of an output buffer driver.

19 is a load circuit diagram for the output of a buffer driver.

20 is an illustration of a programmable delay circuit.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array

104: comparator

110, 112: shift register

118: output buffer driver

Claims (10)

In a circuit for testing a memory cell array, A test circuit coupled to the array, the test circuit comprising a data output line and a fault signal output line; A programmable delay circuit connected to said fault signal output line of said test circuit, said programmable delay circuit comprising a clock signal input and an output line; And An output buffer driver comprising a data input line, a fault signal input line connected to the output line of the programmable delay circuit, and a data output line Including; Upon detection of a defective memory cell in the array, the test circuit generates a fault signal on the fault signal output line of the test circuit, the fault signal enters the programmable delay circuit so that the buffer driver causes the fault. Having high impedance in response to signal Circuit for testing a memory cell array. 2. The circuit of claim 1, wherein the programmable delay circuit is a shift register. 3. The circuit of claim 2, wherein the shift register comprises two latches. 2. The circuit of claim 1, wherein the buffer driver is a three-state buffer driver. 2. The memory of claim 1, further comprising a load, wherein the load forces the voltage on the data output line of the buffer driver to an intermediate voltage level in response to the buffer driver entering a high impedance state. Circuit for testing a cell array. 4. The memory cell array of claim 3, wherein the latch in the shift register can be activated or deactivated to delay the fault signal for a predetermined number of cycles of clock signals on the clock signal input. Circuit. 3. The shift register of claim 2, wherein the shift register comprises two latches, each activation of the latches being independent of each other, the fault in achieving one, two, or three cycles of the buffer driver in response to an external input. Circuit for testing a memory cell array characterized in producing a delay of the signal. In a circuit for testing a memory cell array, A test circuit coupled to the array, the test circuit comprising a data input line and a fault signal output line; A shift register coupled to the fault signal output line of the test circuit, the shift register including a plurality of latches, clock signal inputs, and output lines; And A 3-state output buffer driver comprising a data input line, a fault signal input line coupled to the output line of the shift register, and a data output line Including; Upon detecting a faulty memory cell in the array, the test circuit generates a fault signal on the fault signal output line of the test circuit, the fault signal enters the shift register so that the buffer driver may pass on the fault signal. In response to a high impedance state Circuit for testing a memory cell array. 10. The memory cell array of claim 8, wherein the latch in the shift register can be activated or deactivated to delay the fault signal during a predetermined number of cycles of a clock signal on the clock signal input. Circuit. 9. The method of claim 8, wherein the shift register comprises two latches, each activation of the latches being independent of each other, the fault in achieving one, two, or three cycles of the buffer driver in response to an external input. Circuit for testing a memory cell array characterized in producing a delay of the signal.

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