KR100513423B1 - Apparatus processing Video signal in source device and in display device in transmitting Video signal through optical fiber - Google Patents

Abstract

When the video signal is transmitted from the source device to the optical fiber connected display device, the source device synchronizes the video signal to the clock used in the optical fiber according to the mode, and also displays the video signal synchronized to the clock used in the optical fiber. By synchronizing with the display clock of the device, a problem of synchronization between the source device and the display device generated when the source device and the display device are connected by optical fibers is solved.

Description

Apparatus processing Video signal in source device and in display device in transmitting Video signal through optical fiber}

According to the present invention, when a video signal is transmitted from a source device to a display device connected with an optical fiber, the source device transmits the video signal in synchronization with a clock used in the optical fiber according to a corresponding mode, and also an image signal synchronized with the clock used in the optical fiber. The present invention relates to a source device and an image signal processing apparatus of a display device, which are used in transmitting an image signal through an optical fiber to synchronize the display clock of the display device.

In general, with the development of electronic technology, many flat panel display (FPD) devices have been developed. In display devices such as television receivers and monitors, display screens displaying predetermined images are used instead of bulky and heavy cathode ray tubes. The tendency to adopt thin and light flat panel display elements is increasing.

A flat panel display element is divided into the element using an inorganic substance, and the element using an organic substance based on the substance used. Examples of devices using inorganic materials include plasma display panels (PDPs) using PL (photo luminescence) and field emission display (FED) devices using cathode luminescence (CL), and organic materials are used. Examples of the device include a liquid crystal display element (LCD), an organic EL display element, and the like, which are widely used in various fields.

Among these flat panel display devices, PDP has high brightness and high luminescence efficiency, wide viewing angle, and can be manufactured at a relatively low manufacturing price compared to other flat panel display devices, and has excellent heat and cold resistance characteristics and earthquake resistance characteristics. Since full color is easy to implement and has a light weight, it is widely adopted as a display screen in display devices such as television receivers and monitors with the appearance of large PDPs. In addition, since the display device adopting the PDP as the display screen is light in weight and thin in thickness, many display devices have been developed as wall-mounted devices.

In order to input a video signal and an audio signal output from a source device such as a set top box to a display device employing a PDP as described above, a display device and a source are conventionally used so that the display device outputs video and audio. Connect the devices with each other by coaxial cable so that the video and audio signals of the source device can be transmitted to the display device via the wire, and the display device and the source device can transmit predetermined control signals to each other via the wire. have.

1 is a diagram illustrating a connection relationship between a conventional display device and a source device as an example. Here, reference numeral 100 denotes, for example, a wall-mounted display device such as a wall-mounted monitor or wall-mounted television receiver using a PDP as a display screen.

Reference numeral 110 denotes a digital apparatus such as a digital VTR (Video Tape Recorder) or a DVD (Digital Video Disc) player that reproduces a predetermined playback medium and outputs a transport packet stream of a digital video signal and an audio signal. Reference numeral 120 is an analog device such as a VTR or computer system that reproduces a playback medium such as a video tape and outputs an analog video signal and an analog audio signal.

Reference numeral 130 receives a digital broadcast signal, selectively receives a transmission packet stream output from the digital device 110 and analog video and audio signals output from the analog device 120, and selectively switches the converted signal. A source device such as a set top box to transmit to the display device 100.

In the conventional apparatus having such a configuration, the plurality of digital devices 110 and the source device 130 are connected by a wire such as, for example, an IEEE 1394 cable, and the digital device 110 reproduces a predetermined playback medium or the like. The digital video signal and the audio signal are output as a transmission packet stream, and the output predetermined transmission packet stream is transmitted to the source device 130 through a wire such as an IEEE 1394 cable.

In addition, the analog device 120 and the source device 130 are connected by a wire such as a coaxial cable, and the analog device 120 reproduces a predetermined playback medium so that the analog video signal or the analog R, G, and B signals, and the analog audio signal. The signal is generated, and the generated analog video signal or analog R, G, and B signals and the analog audio signal are transmitted to the source device 130 through a wire such as a coaxial cable.

The source device 130 receives a digital broadcast signal through an ATSC (Advanced Television Systems Committee) tuner or the like, transmits a packet packet stream of the received digital broadcast signal, and a transmission packet input from the digital device 110. Converts the stream into analog video signals and analog audio signals, selectively converts the converted analog video signals and analog audio signals, and analog video signals and audio signals input from the analog device 120 according to a user's selection And transmit it to the display device 130.

Here, the source device 130 transmits the analog R, G, B signals and the audio signals of the L channel and the R channel to the display device 100 through the respective cables, or through the dedicated integrated wired cable, the analog R, G signals. , And transmits the B signal and the analog audio signals of the L channel and the R channel to the display device 100.

In addition, a separate control / response cable is connected between the display device 100 and the source device 130, and a predetermined control signal and a response signal according to the control signal are transmitted to each other through the control / response cable. have.

However, in the above-described conventional technology, since the display device 100 and the source device 130 are connected by a predetermined cable, the display device 100 is mounted on a wall or the like as a wall-mounted type, and the source device 130 is installed on a shelf or the like. In this case, a cable for transmitting analog R, G and B signals and an analog audio signal, a cable for transmitting a control signal and a response signal, etc. are exposed on a wall between the display device 100 and the source device 130. The exposed cable is thick and does not look good.

Therefore, in Patent Application No. 2002-5941 filed by the present applicant, the display device and the source device are connected by a thin fiber, and the source device is a video signal, an audio signal, a control signal, an image mode information, an audio mode information, and the like. Is transmitted as an optical signal to the display device through the optical fiber, and the display device receives and processes the optical signal.

When optical signals are transmitted / received by connecting a source device and a display device with optical fibers, a clock used for processing an image signal at the source device, for example, 74.25 MHz at 720p and a clock used for optical fiber transmission are different from each other. Therefore, the source device needs to transmit the video signal synchronized with the video signal clock to the clock used in the optical fiber, and the display device uses the video signal synchronized with the clock used in the optical fiber in the display device. It is necessary to synchronize with the signal processing clock.

Accordingly, the present invention has been developed according to the above needs, when transmitting a video signal from the source device to the display device connected by the optical fiber, the source device transmits the video signal in synchronization with the clock used in the optical fiber according to the mode, It is an object of the present invention to provide an image signal processing apparatus of a source device and a display device, which are used when transmitting an image signal through an optical fiber to display an image signal synchronized with a clock used in the synchronous display with a display clock of the corresponding display device.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

First, as shown in FIG. 2, an image signal processing apparatus of a source device according to an embodiment of the present invention includes an image mode determiner 200 that determines a corresponding image mode of an image signal to be transmitted to a display device, and an image processor (shown in FIG. 2). And a memory controller 201 for controlling parsing and recording the video information input from the video mode determination unit 200 in units of horizontal sync signal sections determined by the video mode determination unit 200, and the memory controller 201. Memory 202 for recording the image information in units of a horizontal synchronization signal section under the control of;) and the image information stored in the memory 202 according to the image mode determined by the image mode discrimination unit 200. Optical transmission video synchronization read in section units and output to an optical signal transmitter (not shown) in synchronization with an optical clock signal L_CLK input from the outside. Section 203.

In the present invention thus made, first, the image mode determination unit 200 is connected to an image processing unit (not shown) in a source device during one unit vertical synchronization signal period by using a horizontal synchronization signal and a vertical synchronization signal input therefrom. Detects the corresponding video mode of the video signal to be transmitted to the display device by detecting the number of pulses of the horizontal sync signal generated, or connects with the CPU (not shown) to pre-determine binary bit information related to the video mode input therefrom. Compared with the stored information, the corresponding video mode is determined according to the comparison result.

The memory controller 201 records the image signal input from the image processor (not shown) in the memory 202 in units of corresponding horizontal synchronization signal sections of the image mode determined by the image mode determiner 200. .

 Then, the optical transmission image synchronizer 203 reads image information stored in the memory 202 in units of horizontal synchronization signal intervals according to the image mode determined by the image mode determination unit 200, thereby reproducing an external clock generator (not shown). Output to the optical signal transmitter (not shown) in synchronization with the optical clock signal L_CLK generated in the second embodiment.

3A illustrates a first embodiment of the image mode determination unit 200 using horizontal and vertical synchronization signals. When the horizontal synchronization signal period detector 230 receives a horizontal synchronization signal from an image processor (not shown), Counts the synchronous clock signal S_CLK input through an external clock generator (not shown) and resets when the next horizontal synchronous signal is input, thereby detecting the number of clocks generated during one horizontal synchronous signal period. .

Then, the vertical synchronizing signal period detecting unit starts counting the horizontal synchronizing signal according to the input of the vertical synchronizing signal, resets the next vertical synchronizing signal, and resets the pulse of the horizontal synchronizing signal generated during one vertical synchronizing signal period. Detect the number.

Then, the image mode detection unit 232 detects a specific image mode according to the number of pulses detected by the vertical synchronization signal period detection unit, and the image mode detection unit 232 is, for example, horizontal synchronization belonging to one vertical synchronization signal section. It is preferable to use a register that stores the number of pulses of the signals in a table for each specific image mode.

3B is a detailed circuit diagram of FIG. 3A, which is a first embodiment of the image mode determination unit. As shown in FIG. 3, the horizontal synchronization signal period detection unit 230 is generated by an external clock generator (not shown). A first D flip-flop D1 for receiving the synchronous clock signal S_CLK to the corresponding clock terminal CK, receiving the horizontal synchronous signal to the input terminal D, and firstly delaying the horizontal synchronous pulse; The synchronous clock signal S_CLK is input to the corresponding clock terminal CK, the first delayed horizontal synchronization signal is input to the corresponding input terminal D, and the first delayed horizontal synchronization signal is secondly delayed and then inverted. A first NAND gate 233 which negatively multiplies the second D flip-flop D2 to be output, the first delayed horizontal sync signal and the second delayed and inverted horizontal sync signal to generate a first reset pulse; The synchronous clock signal S_ And a first counter 234 that resets the count value at the falling edge of the first reset pulse and resumes the count operation at the rising edge of the first reset pulse.

The vertical synchronizing signal period detecting unit 231 receives the horizontal synchronizing signal through the corresponding clock terminal CK, receives the vertical synchronizing pulse through the input terminal D, and outputs the first vertical synchronizing signal by delaying the vertical synchronizing signal. A third D flip-flop D3 and the horizontal synchronization signal to the clock terminal CK, the first delayed vertical synchronization signal to the input terminal D, and the first delayed vertical synchronization signal to the second terminal. Generating a second reset pulse by negatively multiplying the fourth D flip-flop D4 outputted after the difference is delayed, the first delayed vertical sync signal, and the second delayed and inverted vertical sync signal. By counting the number of pulses of the horizontal synchronization signal with the second NAND gate 235, the count value is reset on the falling edge of the second reset pulse, and the count operation is performed on the rising edge of the second reset pulse. ashes Article made of a second counter (236) to.

Meanwhile, FIG. 4 is a second embodiment of the image mode determination unit 200. As shown therein, a binary bit signal related to an image mode is input from a CPU (not shown) in a source device such as a set top box. The counter 240 counts the synchronous clock signal S_CLK input from the external clock generator according to the input binary bit signal, and stores the image modes in advance by coding the respective binary bits into specific binary bits and registers corresponding to the binary bits. The comparison result of the register 241 which periodically outputs a signal, the comparator 242 which compares the signal counted by the counter 240, and the register signal output from the register 241, and the comparator 242. Accordingly, the image mode signal processor 243 determines the image mode information and outputs the image mode determination signal corresponding thereto.

In the image mode determination unit 200 configured as described above, when the binary bit information related to the image mode is input from a CPU (not shown) in the source device, the counter 240 inputs an external clock generator according to the input binary bit data. The number of pulses of the synchronous clock signal S_CLK is counted. The synchronous clock signal S_CLK is a synchronous signal used to process an image signal in a source device, for example, 74.25 MHz for 720p and 27 MHz for 480p. .

In addition, the comparator 242 periodically receives a register signal corresponding to specific image modes precoded with a specific binary bit from the register 241 and compares it with a signal counted and output from the counter 240. The image mode signal processor 243 determines corresponding image mode information according to the comparison result of the comparator 242, and outputs the image mode determination signal corresponding thereto to the memory controller 201 and the optical transmission image synchronizer 203, respectively. Done.

Next, another image signal processing apparatus of the display device according to the present invention will be described with reference to FIG. 5.

As shown in FIG. 5, the image signal processing apparatus of the display device includes an optical reception image mode recognition unit 500 that recognizes a corresponding image mode of an image signal transmitted from a source device, and the optical reception image mode recognition unit ( A memory controller 510 for controlling parsing and recording of image information synchronized with an optical clock signal input from the outside in units of a horizontal synchronization signal section of the image mode recognized by 500; A memory 520 for recording image information synchronized with the optical clock signal in units of a horizontal synchronizing signal section under control, and stored in the memory 520 according to an image mode recognized by the optical receiving image mode recognition unit 500. The image information is read by the unit horizontal synchronization signal section and synchronized with the display clock signal D_CLK inputted through an external clock generator (not shown). And a display image synchronizer 530 for outputting to the display image.

The optical reception image mode recognizer 500 in the display device may include, for example, an image mode header recognizer 501 that recognizes an image mode header of a transport packet stream, and a parser that parses the image mode header information. And a video mode information detection unit 503 that detects video mode information from a result of parsing by the parser unit 502.

In the video signal processing apparatus of the display device, the demultiplexer (not shown) of the optical transmitting / receiving unit (not shown) first corresponds to the video information, audio information, control information, video mode information, and audio mode information carried in the transport stream. The image mode header recognizer 501 of the optical reception image mode recognizer 500 recognizes and receives a header of the image mode information distributed to the demultiplexer, and the header is an image mode. Depending on the number of bits.

Next, when the parser unit 502 parses the header of the image mode, the image mode information detector 503 detects the image mode information from the header information parsed by the parser unit 502, and then the memory controller 510. And output to the display image synchronizer 530. For example, a binary bit value obtained by counting binary bits parsed from header information and a binary bit value related to a preset video mode are compared with each other, and the voice mode information is determined according to the comparison result. Is detected, and a corresponding detection signal is output to the memory controller 510 and the display image synchronizer 530.

Then, the memory controller 510 writes the image information distributed by the demultiplexer (not shown) to the memory 520 in units of corresponding horizontal synchronization signal sections of the image mode recognized by the image mode recognizer 500. .

The optical transmission image synchronizer 530 reads image information stored in the memory 520 in units of horizontal synchronization signal sections of a corresponding video mode recognized by the image mode recognizer 500, and uses an external clock generator ( (Not shown) in synchronization with the display clock signal D_CLK generated in the display device (not shown). The display clock signal D_CLK varies depending on the display device, for example, 720p. MHz, and 480p, 27 MHz.

As described in detail above, an image signal processing apparatus of a source device and an image signal processing apparatus of a display device, which are used when transmitting an image signal through an optical fiber of the present invention, when transmitting an image signal from a source device to a display device connected to an optical fiber, The source device synchronizes the image signal to the clock used in the optical fiber according to the mode, and transmits the image signal synchronized with the clock used in the optical fiber to the display clock of the display device. This can solve the sync problem that occurs when connecting.

Although the invention has been described in detail only with respect to the specific examples described, it will be apparent to those skilled in the art that various modifications and variations are possible within the spirit of the invention, and such modifications and variations belong to the appended claims.

1 is a view showing a connection relationship between a conventional source device and a display device as an example,

2 is an image signal processing apparatus of a source device used when transmitting an image signal through an optical fiber of the present invention,

3A is a diagram illustrating a first embodiment of an image mode determining unit applied to an image signal processing apparatus of a source device according to the present invention;

3b is a detailed circuit diagram of FIG.

4 is a diagram illustrating a second embodiment of an image mode determination unit applied to an image signal processing apparatus of a source device;

5 is a view showing an image signal processing apparatus of a display device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: light transmission image mode discrimination unit 201, 510: memory control unit

202, 520: memory 203: optical transmission image synchronizer

500: light receiving image mode recognition unit 530: display image synchronization unit

Claims (8)

An image mode determination unit for determining a corresponding image mode with respect to an image signal to be transmitted to a display device; A memory for recording constant image information in units of horizontal synchronization signal sections; A memory controller for parsing the image information input from the outside in units of horizontal sync signal sections of the image mode determined by the image mode determination unit and writing the same to the memory; An image through an optical fiber made up of an optical transmission image synchronizer which reads image information stored in the memory in units of corresponding horizontal synchronization signal sections according to the image mode determined by the image mode determination unit, and outputs the image information in synchronization with an optical clock signal input from the outside; An image signal processing apparatus of a source device used for signal transmission. The apparatus of claim 1, wherein the image mode determination unit; A counter for counting the synchronous clock signal S_CLK according to an image mode-related binary bit signal input from the outside; A register for coding and storing a plurality of image modes into specific binary bits in advance and periodically outputting a resist signal corresponding to the corresponding binary bits; A comparator for comparing the signal counted by the counter with a register signal output from the register; An image signal processing apparatus of a source device used when transmitting an image signal through an optical fiber, characterized in that the image mode signal processing unit for determining the corresponding image mode information according to the comparison result of the comparator and outputs a corresponding image mode determination signal. . The apparatus of claim 1, wherein the image mode determination unit; A horizontal synchronizing signal period detection unit which starts counting the synchronizing clock signal S_CLK according to the input of the horizontal synchronizing signal and resets the next horizontal synchronizing signal when it is input, and detects the number of clocks generated during one horizontal synchronizing signal period; ; The vertical synchronization signal period detection unit detects the number of pulses of the horizontal synchronization signal generated during one vertical synchronization signal period by starting to count the horizontal synchronization signal and resetting the next vertical synchronization signal according to the input of the vertical synchronization signal. Wow; And an image mode detection unit for detecting an image mode according to the number of pulses detected by the vertical synchronization signal period detection unit. The apparatus of claim 3, wherein the horizontal synchronization signal period detector comprises: a horizontal synchronization signal period detector; A first D flip-flop that receives the synchronous clock signal S_CLK generated by an external clock generator through the corresponding clock terminal CK, receives the horizontal synchronization signal through the corresponding input terminal D, and delays the horizontal synchronization pulse by a first order. and; The synchronous clock signal S_CLK is input to the corresponding clock terminal CK, the first delayed horizontal synchronization signal is input to the corresponding input terminal D, and the first delayed horizontal synchronization signal is secondly delayed and inverted. A second D flip-flop to output; A NAND gate negatively multiplying the first delayed horizontal sync signal with the second delayed and inverted horizontal sync signal to generate a reset pulse; Counting the synchronous clock signal S_CLK, wherein the counter resets the count value at the falling edge of the reset pulse and resumes the count operation at the rising edge of the reset pulse. An image signal processing apparatus of a source device used for signal transmission. 4. The apparatus of claim 3, wherein the vertical synchronization signal period detection unit; A third D flip-flop that receives the horizontal synchronizing signal through a corresponding clock terminal CK, receives the vertical synchronizing pulse through an input terminal D, and outputs the primary synchronizing signal by first delaying the vertical synchronizing signal; A fourth outputting the horizontal synchronization signal to the clock terminal CK and a first delayed vertical synchronization signal to the input terminal D, a second delay of the primary delayed vertical synchronization signal, and inverting the first synchronization signal D flip-flop; A NAND gate generating a reset pulse by negating the first delayed vertical synchronization signal and the second delayed and inverted vertical synchronization signal; Counting the number of pulses of the horizontal synchronizing signal, wherein the counter resets the count value at the falling edge of the reset pulse and resumes the count operation at the rising edge of the reset pulse. An image signal processing apparatus of a source device used for signal transmission. The apparatus of claim 3, wherein the image mode detector comprises: an image mode detector; An image signal processing apparatus of a source device used when transmitting an image signal through an optical fiber, characterized in that a register for storing the table number of the pulses of the horizontal synchronization signals belonging to one vertical synchronization signal interval for each specific image mode. An optical reception image mode recognition unit recognizing a corresponding image mode of the image signal transmitted from the source device; A memory controller configured to parse and record image information synchronized with an optical clock signal input from an external unit in a corresponding horizontal synchronization signal section unit of an image mode recognized by the optical receiving image mode recognizer; A memory for recording image information synchronized with the optical clock signal in units of horizontal synchronization signals under the control of the memory controller; A display for reading image information stored in the memory in units of horizontal synchronization signal sections according to an image mode recognized by the optical receiving image mode recognition unit, and outputting the image information in synchronization with a display clock signal D_CLK input through an external clock generator. An image signal processing apparatus of a display device used when transmitting an image signal through an optical fiber comprising an image synchronizer. The apparatus of claim 7, wherein the light receiving image mode recognizer; An image mode header recognition unit recognizing an image mode header of a transport packet stream transmitted from a source device; A parser unit for parsing image mode header information recognized by the image mode header recognizer; And an image mode information detection unit for detecting image mode information from a result of parsing of the parser.