KR100502403B1 - Decoder of mpeg-2 - Google Patents

Abstract

The present invention relates to an MPEG-2 decoding apparatus, comprising: a variable length decoding unit for extracting a variable length coded DCT coefficient, an inverse scan unit for outputting one-dimensional data as two-dimensional data, an inverse quantizer for multiplying a quantization coefficient, and an inverse DCT And a motion compensator for extracting and compensating for the motion of the image. The inverse quantizer prevents errors from accumulating by correcting an inconsistency error after ORing the image blocks.

Description

Decoders by MPEG {Decoder of MPEG-2}

The present invention relates to a decoder, and more particularly, to a decoding apparatus for decoding data compressed and encoded according to MPEG-2.

Recently, the technology of the Moving Picture Experts Group (MPEG) for compressing, restoring, and reproducing moving image video and audio signals into digital data is generally used.

MPEG is broadly used, for example, MPEG-1 and MPEG-2. The difference between MPEG-2 (ISO / IEC 13818-2) and MPEG-1 is as follows.

MPEG-2 supports various video formats, provides tools for realizing high definition, provides scalability, actively supports trick modes, enhances error tolerance, and supports profiles and levels. The decoding function by is classified.

Such MPEG encodes signals (video and audio) to be stored or transmitted, and then multiplexes them to be stored in a medium or transmitted through a transmission path. Meanwhile, in order to reproduce data stored in a medium or a signal received through a transmission path, demux and decoding are performed.

Here, the decoding process will be described in detail with reference to FIG. 1. In the drawing, reference numeral 10 denotes a variable length decoding unit, 20 inverse scan unit, 30 inverse quantization unit, 40 inverse DCT unit, 50 indicates a motion compensation unit, and 60 indicates a frame memory.

For MPEG-2, see JTC 1 / SC 29 N, 0981 Rev. ISO / IEC, issued March 31, 1995. pp. It is described in 7.

Here, the dequantization unit 30 dequantizes the data quantized in the coding step.

FIG. 2 is a diagram illustrating the inverse quantization unit 30 shown in FIG. 1 in detail. In the drawings, reference numeral 70 denotes an inverse quantization calculator, 80 denotes a saturation processor, and 90 denotes a mismatch controller.

As shown in the figure, the inverse quantization operation unit 70 processes the data from the inverse scan unit 20 by multiplying the weight matrix W [w] [v] [u] and the quantization proportional coefficient (quantizer_scale). (F "[v] [u]) The processing operation of the inverse quantization operation unit 70 can be expressed by the following equation.

Here, QF [v] [u] represents data processed from the inverse scan unit 20.

Subsequently, the saturation processing unit 80 processes the data processed by the inverse quantization operation unit 70 so as not to deviate from a predetermined range (-2048 to +2047). Such a process can be represented by the following equation.

Subsequently, the mismatch controller 90 adds all coefficients (data) to the data processed by the saturation processor 80 as in the following equation.

The mismatch controller 90 processes as follows according to whether the result of Equation 3 is odd or even. Here, u and v are assumed to be 7.

The data processed in this way is input to the inverse DCT unit 40.

The routine for processing Equation 3 of the mismatch controller 90 may be represented as follows.

sum = 0;

for (v = 0; v <8; v ++) {

for (u = 0; u <8; u ++) {

sum = sum + F '[v] [u];

}

}

Therefore, when u and v are M, a total of M²-1 combinations are performed.

Therefore, 8²-1 = 63 operations must be performed here.

As described above, according to the conventional embodiment, as the number of bits and rows to be mismatched in the mismatch controller 90 increases, the summation step is increased by M²-1, which is a heavy load on the real-time processing.

Accordingly, an object of the present invention is to provide an MPEG-2 decoding apparatus that can solve the above-mentioned problems and can quickly perform mismatch processing because the operation step can be reduced.

According to a feature of the present invention proposed to achieve the above object, the MPEG-2 decoding apparatus includes a variable length decoding unit for extracting and decoding a variable length coded DCT coefficient from the input bit stream data to output as one-dimensional data; ; An inverse scan unit converting the one-dimensional data output from the variable length decoding unit according to a predetermined scanning method and outputting the two-dimensional data; An inverse quantization unit which inversely quantizes two-dimensional data from the inverse scan unit and restores the actual DCT coefficient value, and then corrects and outputs an inconsistency error with an exclusive OR of the image block; An inverse DCT unit for inversely converting and outputting data output from the inverse quantization unit; And a motion compensator for compensating and extracting a predetermined region of a part having a motion from the previous screen.

In an exemplary embodiment of the present invention, the inverse quantization unit inversely quantizes the data from the inverse scan unit with a weight matrix and a quantization proportional coefficient to dequantize and output the actual DCT coefficient value; A saturation processing unit for processing data output from the inverse quantization operation unit so as not to exceed a predetermined counting range; And an inconsistency control unit that corrects the coefficients of the data output from the saturation processing unit for each row of the image block, and then corrects them to prevent the inconsistency errors from accumulating.

In a preferred embodiment of this aspect, the mismatch control section includes n registers of m bits.

In a preferred embodiment of this aspect, the inconsistency control unit exclusively ORs each bit of the i-1 th register corresponding to each bit of the i th register and stores it in the corresponding bit of the i th register; Each bit of the nth register is output with an exclusive OR.

The present invention relates to an MPEG-2 decoding apparatus, comprising: a variable length decoding unit for extracting a variable length coded DCT coefficient, an inverse scan unit for outputting one-dimensional data as two-dimensional data, an inverse quantizer for multiplying a quantization coefficient, and an inverse DCT And a motion compensator for extracting and compensating for the motion of the image. The inverse quantizer prevents errors from accumulating by correcting an inconsistency error after ORing the image blocks.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 5.

Referring to FIG. 3, the novel MPEG-2 decoding apparatus of the present invention can reduce the computational step and can quickly perform mismatch processing.

First, it is assumed that the mismatch controller 90 performs an operation on an 8 × 8 picture block. Here, each register in the picture block has a size of 16 bits, which is called a scalar register.

One row of registers in the picture block has a size of 16x8 bits, which is called a vector register.

Here, if the column number is represented by? (0≤ι≤7) and the row number is represented by k (0≤k≤7), each vector register is represented as follows.

Where e _kl represents each scalar register in the vector register.

3 is a diagram illustrating an operation of a register of a mismatch controller according to an exemplary embodiment of the present invention.

As shown in the drawing, when the operation is started, first, an exclusive logical operation is performed (VXOR) on the vector register VR ₀ of the first column and the vector register VR ₁ of the second column, and the result is a vector of the second column. It is stored in the register (VR _1). Subsequently, and stores in the second series of vector registers (VR ₁₎ and the third column the vector register (VR ₂₎ performing (VXOR) an exclusive-OR operation on the third column the vector register (VR _2).

In this manner, exclusive logical operations are sequentially performed on all the vector registers up to the vector register VR _{7 of} the eighth column.

Finally, an exclusive logical operation is performed (VXORALL) on each scalar register of the vector register VR ₈ of the eighth column to store the result value.

Such operation is performed by the following command.

VXOR VR1, VR0, VR1

VXOR VR2, VR1, VR2

VXOR VR3, VR2, VR3

VXOR VR4, VR3, VR4

VXOR VR5, VR4, VR5

VXOR VR6, VR5, VR6

VXOR VR7, VR6, VR7

VXORALL VR7, SRO

Here, the first parameter of the VXOR instruction indicates a destination, and the second and third parameters indicate a source. The first parameter of the VXORALL instruction indicates a source, and the second parameter indicates a destination.

According to the embodiment of the present invention as described above, it is possible to perform the combined operation of the disagreement control unit 90 in eight operation instructions.

4 is a view showing in detail the operation of the exclusive logical sum in the operation shown in Figure 3 according to an embodiment of the present invention.

As shown in the figure, the value of each scalar register of the vector register VRn of the nth column is exclusive ORed with the corresponding scalar register of the vector register VRn-1 of the nth column, so as to obtain the vector register of the nth column. It is stored in the corresponding scalar register of VRn).

FIG. 5 is a view illustrating an operation of an exclusive OR of the last register (for example, the vector register of the k-th column) in the operation shown in FIG. 3.

As shown in the figure, each scalar register of the vector register VRk in the kth column is exclusively ORed and stored in the result register SR0.

The present invention solves the problem that the decoding operation increases the load by M²-1 as the number of bits and rows to be mismatched in the mismatch control unit increases. It can be reduced so that the inconsistency can be performed quickly.

1 is a diagram showing a configuration of a decoding unit of MPEG-2;

FIG. 2 is a block diagram specifically showing the inverse quantization unit shown in FIG. 1; FIG.

3 is a diagram illustrating an operation of a register of a mismatch control unit shown in FIG. 2 according to an exemplary embodiment of the present invention;

4 is a view showing in detail the operation of the exclusive logical sum in the operation shown in Figure 3 according to an embodiment of the present invention;

FIG. 5 is a view showing the operation of the exclusive OR of the last register in the operation shown in FIG. 3; FIG.

<Explanation of symbols for the main parts of the drawings>

10: variable length decoding unit 20: reverse scan unit

30: inverse quantization unit 40: inverse DCT unit

50: motion compensation unit 60: frame memory

70: inverse quantization operation unit 80: saturation processing unit

90: discrepancy control unit

Claims (4)

In an MPEG-2 decoder that handles mismatches for m-bit, n-row picture blocks: A variable length decoding unit 10 for extracting and decoding a variable length coded DCT coefficient from the input bitstream data and outputting the decoded DCT coefficient as one-dimensional data QF [n]; An inverse scan unit 20 for converting the one-dimensional data QF [n] output from the variable length decoding unit 10 according to a predetermined scanning method and outputting the two-dimensional data QF [v] [u]; ; The inverse quantization of the two-dimensional data QF [v] [u] from the inverse scan unit 20 is inversely quantized and restored to the actual DCT coefficient value F [v] [u], and then exclusive to the image block. An inverse quantization unit 30 for correcting and outputting a mismatch error by a logical sum; An inverse DCT unit 40 which inverses DCT the data F [v] [u] output from the inverse quantization unit 30 and outputs f [y] [x]; MPEG-2 decoding apparatus comprising a motion compensator (50) for compensating and extracting a predetermined region of a portion having a motion in the previous screen. The method of claim 1, The inverse quantization unit 30 calculates the data QF [v] [u] from the inverse scan unit 20 by a weight matrix W [w] [v] [u] and a quantization scale factor (quantizer_scale). An inverse quantization operation unit 70 which multiplies by and inversely quantizes the actual DCT coefficient to output F ″ [v] [u]; A saturation processing unit (80) for processing such that data F "[v] [u] output from said inverse quantization operation unit (70) does not exceed a predetermined counting range; The inconsistency control unit 90 corrects the coefficients of the data F '[v] [u] output from the saturation processing unit 80 to perform an exclusive OR for each row of the image block, and then corrects the mismatch error to be accumulated. MPEG-2 decoding apparatus comprising a. The method of claim 2, The inconsistency control unit (90) comprises n registers of m bits. The method of claim 2, The mismatch controller 90 exclusively ORs each bit of the i-1 th register corresponding to each bit of the i th register and stores it in the corresponding bit of the i th register (i = 2, ..., n); MPEG-2 decoding apparatus characterized by outputting the exclusive OR of all the bits of the n-th register.

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